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sim: mips: Add simulator support for mips32r6/mips64r6

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2022-02-01  Ali Lown  <ali.lown@imgtec.com>
	    Andrew Bennett  <andrew.bennett@imgtec.com>
	    Dragan Mladjenovic  <dragan.mladjenovic@rt-rk.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/common/ChangeLog:
	* sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21,
	EXTEND26): New macros.

sim/mips/ChangeLog:
	* Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen.
	* configure: Regenerate.
	* configure.ac: Support mipsisa32r6 and mipsisa64r6.
	(sim_engine_run): Pick simulator model from processor specified
	in e_flags.
	* cp1.c (value_fpr): Handle fmt_dc32.
	(fp_unary, fp_binary): Zero initialize locals.
	(update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac,
	fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub):
	New functions.
	(sim_fpu_class_mips_mapping): New.
	* cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define.
	* interp.c (MIPSR6_P): New.
	(load_word): Allow unaligned memory access for MIPSR6.
	* micromips.igen (sc, scd): Adapt to new do_sc* helper signature.
	* mips.igen: Add *r6 models.
	(signal_if_cti, forbiddenslot32): New helpers.
	(delayslot32): Use signal_if_cti.
	(do_sc, do_scd); Add store_ll_bit parameter.
	(sc, scd): Adapt to previous change.
	(nal, beq, bal): New definitions for *r6.
	(sll): Split nop and ssnop cases into ...
	(nop, ssnop): New definitions.
	(loadstore_ea): Use the 32-bit compatibility adressing.
	(cache): Split logic into ...
	(do_cache): New helper.
	(check_fpu): Select IEEE 754-2008 mode for R6.
	(not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add,
	li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd,
	daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra,
	dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr,
	jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror,
	rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav,
	srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt,
	tltu, tne, xor, xori, check_fmt_p, do_load_double,
	do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT,
	cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1,
	dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT,
	mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT,
	sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f,
	bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp,
	tlbr, tlbwi, tlbwr): Enable on *r6 models.
	* mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu,
	dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr,
	wsbh): Likewise.
	* mips3264r6.igen: New file.
	* sim-main.h (FP_formats): Add fmt_dc32.
	(FORBIDDEN_SLOT): New macros.
	(simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines.
	(fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina,
	fp_maxa, fp_fmadd, fp_fmsub): New declarations.
	(R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA,
	MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping
	previous declarations.

sim/testsuite/mips/ChangeLog:
	* basic.exp: Add r6-*.s tests.
	(run_r6_removed_test): New function.
	(run_endian_tests): New function.
	* hilo-hazard-3.s: Skip for mips*r6.
	* r2-fpu.s: New test.
	* r6-64.s: New test.
	* r6-branch.s: New test.
	* r6-forbidden.s: New test.
	* r6-fpu.s: New test.
	* r6-llsc-dp.s: New test.
	* r6-llsc-wp.s: New test.
	* r6-removed.csv: New test.
	* r6-removed.s: New test.
	* r6.s: New test.
	* utils-r6.inc: New inc.
This commit is contained in:
Faraz Shahbazker 2022-02-02 11:17:25 +01:00 committed by Mike Frysinger
parent fc3c199fac
commit 06c441ccef
26 changed files with 3749 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sim/common/sim-bits.h
View File

@ -500,12 +500,17 @@ INLINE_SIM_BITS(unsigned_word) MSINSERTED (unsigned_word val, int start, int sto
#define EXTEND5(X) (LSSEXT ((X), 4))
#define EXTEND6(X) (LSSEXT ((X), 5))
#define EXTEND8(X) ((signed_word)(int8_t)(X))
#define EXTEND9(X) (LSSEXT ((X), 8))
#define EXTEND11(X) (LSSEXT ((X), 10))
#define EXTEND12(X) (LSSEXT ((X), 11))
#define EXTEND15(X) (LSSEXT ((X), 14))
#define EXTEND16(X) ((signed_word)(int16_t)(X))
#define EXTEND18(X) (LSSEXT ((X), 17))
#define EXTEND19(X) (LSSEXT ((X), 18))
#define EXTEND21(X) (LSSEXT ((X), 20))
#define EXTEND24(X) (LSSEXT ((X), 23))
#define EXTEND25(X) (LSSEXT ((X), 24))
#define EXTEND26(X) (LSSEXT ((X), 25))
#define EXTEND32(X) ((signed_word)(int32_t)(X))
#define EXTEND64(X) ((signed_word)(int64_t)(X))

1
sim/mips/Makefile.in
View File

@ -98,6 +98,7 @@ IGEN_INCLUDE=\
$(srcdir)/dsp.igen \
$(srcdir)/dsp2.igen \
$(srcdir)/mips3264r2.igen \
$(srcdir)/mips3264r6.igen \
# NB: Since these can be built by a number of generators, care
# must be taken to ensure that they are only dependant on

22
sim/mips/configure vendored
View File

@ -1871,7 +1871,8 @@ case "${target}" in
sim_gen=MULTI
sim_multi_configs="\
micromips:micromips64,micromipsdsp:32,64,f:mips_micromips\
mips64r2:mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,64,f:mipsisa64r2"
mipsisa64r2:mips64r2,mips16,mips16e,mdmx,dsp,dsp2,mips3d,smartmips:32,64,f:mipsisa32r2,mipsisa64r2,mipsisa32r5,mipsisa64r5\
mipsisa64r6:mips64r6:32,64,f:mipsisa32r6,mipsisa64r6"
sim_multi_default=mipsisa64r2
;;
mips64*-*-*) sim_igen_filter="32,64,f"
@ -1887,6 +1888,11 @@ case "${target}" in
mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f:mipsisa32r2"
sim_multi_default=mipsisa32r2
;;
mipsisa32r6*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips32r6"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32r6"
;;
mipsisa32*-*-*) sim_gen=M16
sim_igen_machine="-M mips32,mips16,mips16e,smartmips"
sim_m16_machine="-M mips16,mips16e,mips32"
@ -1899,6 +1905,11 @@ case "${target}" in
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r2"
;;
mipsisa64r6*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64r6"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r6"
;;
mipsisa64sb1*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,mips3d,sb1"
sim_igen_filter="32,64,f"
@ -1963,7 +1974,7 @@ if test ${sim_gen} = MULTI; then
cat << __EOF__ > multi-run.c
/* Main entry point for MULTI simulators.
Copyright (C) 2003-2021 Free Software Foundation, Inc.
Copyright (C) 2003-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -1985,6 +1996,7 @@ if test ${sim_gen} = MULTI; then
#include "sim-main.h"
#include "multi-include.h"
#include "elf-bfd.h"
#include "elfxx-mips.h"
#include "elf/mips.h"
#define SD sd
@ -2004,7 +2016,11 @@ sim_engine_run (SIM_DESC sd,
& EF_MIPS_ARCH_ASE_MICROMIPS)
mach = bfd_mach_mips_micromips;
else
mach = STATE_ARCHITECTURE (SD)->mach;
{
mach = _bfd_elf_mips_mach (elf_elfheader (STATE_PROG_BFD (sd))->e_flags);
if (!mach)
mach = STATE_ARCHITECTURE (SD)->mach;
}
switch (mach)
{

20
sim/mips/configure.ac
View File

@ -102,7 +102,8 @@ case "${target}" in
sim_gen=MULTI
sim_multi_configs="\
micromips:micromips64,micromipsdsp:32,64,f:mips_micromips\
mips64r2:mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,64,f:mipsisa64r2"
mipsisa64r2:mips64r2,mips16,mips16e,mdmx,dsp,dsp2,mips3d,smartmips:32,64,f:mipsisa32r2,mipsisa64r2,mipsisa32r5,mipsisa64r5\
mipsisa64r6:mips64r6:32,64,f:mipsisa32r6,mipsisa64r6"
sim_multi_default=mipsisa64r2
;;
mips64*-*-*) sim_igen_filter="32,64,f"
@ -118,6 +119,11 @@ case "${target}" in
mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f:mipsisa32r2"
sim_multi_default=mipsisa32r2
;;
mipsisa32r6*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips32r6"
sim_igen_filter="32,f"
sim_mach_default="mipsisa32r6"
;;
mipsisa32*-*-*) sim_gen=M16
sim_igen_machine="-M mips32,mips16,mips16e,smartmips"
sim_m16_machine="-M mips16,mips16e,mips32"
@ -130,6 +136,11 @@ case "${target}" in
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r2"
;;
mipsisa64r6*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64r6"
sim_igen_filter="32,64,f"
sim_mach_default="mipsisa64r6"
;;
mipsisa64sb1*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,mips3d,sb1"
sim_igen_filter="32,64,f"
@ -216,6 +227,7 @@ if test ${sim_gen} = MULTI; then
#include "sim-main.h"
#include "multi-include.h"
#include "elf-bfd.h"
#include "elfxx-mips.h"
#include "elf/mips.h"
#define SD sd
@ -235,7 +247,11 @@ sim_engine_run (SIM_DESC sd,
& EF_MIPS_ARCH_ASE_MICROMIPS)
mach = bfd_mach_mips_micromips;
else
mach = STATE_ARCHITECTURE (SD)->mach;
{
mach = _bfd_elf_mips_mach (elf_elfheader (STATE_PROG_BFD (sd))->e_flags);
if (!mach)
mach = STATE_ARCHITECTURE (SD)->mach;
}
switch (mach)
{

432
sim/mips/cp1.c
View File

@ -100,6 +100,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
#define FPQNaN_PS (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE))
static void update_fcsr (sim_cpu *, address_word, sim_fpu_status);
static const char *fpu_format_name (FP_formats fmt);
#ifdef DEBUG
static const char *fpu_rounding_mode_name (int rm);
@ -127,7 +129,7 @@ value_fpr (sim_cpu *cpu,
}
/* For values not yet accessed, set to the desired format. */
if (fmt < fmt_uninterpreted)
if (fmt < fmt_uninterpreted && fmt != fmt_dc32)
{
if (FPR_STATE[fpr] == fmt_uninterpreted)
{
@ -137,7 +139,10 @@ value_fpr (sim_cpu *cpu,
fpu_format_name (fmt));
#endif /* DEBUG */
}
else if (fmt != FPR_STATE[fpr])
else if (fmt != FPR_STATE[fpr]
&& !(fmt == fmt_single
&& FPR_STATE[fpr] == fmt_double
&& (FGR[fpr] == 0 || FGR[fpr] == 0xFFFFFFFF)))
{
sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
fpr, fpu_format_name (FPR_STATE[fpr]),
@ -166,6 +171,7 @@ value_fpr (sim_cpu *cpu,
case fmt_uninterpreted_32:
case fmt_single:
case fmt_word:
case fmt_dc32:
value = (FGR[fpr] & 0xFFFFFFFF);
break;
@ -557,8 +563,8 @@ fp_test(uint64_t op1,
if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
{
if ((cond & (1 << 3)) ||
sim_fpu_is_snan (&wop1) || sim_fpu_is_snan (&wop2))
if ((cond & (1 << 3))
|| sim_fpu_is_snan (&wop1) || sim_fpu_is_snan (&wop2))
status = sim_fpu_status_invalid_snan;
less = 0;
equal = 0;
@ -581,6 +587,109 @@ fp_test(uint64_t op1,
return status;
}
static const int sim_fpu_class_mips_mapping[] = {
FP_R6CLASS_SNAN, /* SIM_FPU_IS_SNAN = 1, Noisy not-a-number */
FP_R6CLASS_QNAN, /* SIM_FPU_IS_QNAN = 2, Quiet not-a-number */
FP_R6CLASS_NEGINF, /* SIM_FPU_IS_NINF = 3, -infinity */
FP_R6CLASS_POSINF, /* SIM_FPU_IS_PINF = 4, +infinity */
FP_R6CLASS_NEGNORM, /* SIM_FPU_IS_NNUMBER = 5, -num - [-MAX .. -MIN] */
FP_R6CLASS_POSNORM, /* SIM_FPU_IS_PNUMBER = 6, +num - [+MIN .. +MAX] */
FP_R6CLASS_NEGSUB, /* SIM_FPU_IS_NDENORM = 7, -denorm - (MIN .. 0) */
FP_R6CLASS_POSSUB, /* SIM_FPU_IS_PDENORM = 8, +denorm - (0 .. MIN) */
FP_R6CLASS_NEGZERO, /* SIM_FPU_IS_NZERO = 9, -0 */
FP_R6CLASS_POSZERO /* SIM_FPU_IS_PZERO = 10, +0 */
};
uint64_t
fp_classify (sim_cpu *cpu,
address_word cia,
uint64_t op,
FP_formats fmt)
{
sim_fpu wop;
switch (fmt)
{
case fmt_single:
sim_fpu_32to (&wop, op);
break;
case fmt_double:
sim_fpu_64to (&wop, op);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
return sim_fpu_class_mips_mapping[sim_fpu_classify (&wop) - 1];
}
int
fp_rint (sim_cpu *cpu,
address_word cia,
uint64_t op,
uint64_t *ans,
FP_formats fmt)
{
sim_fpu wop = {0}, wtemp = {0}, wmagic = {0}, wans = {0};
int64_t intermediate;
int status = 0;
sim_fpu_round round = rounding_mode (GETRM());
switch (fmt)
{
case fmt_single:
sim_fpu_32to (&wop, op);
sim_fpu_32to (&wmagic, 0x4b000000);
break;
case fmt_double:
sim_fpu_64to (&wop, op);
sim_fpu_64to (&wmagic, 0x4330000000000000);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
if (sim_fpu_is_nan (&wop) || sim_fpu_is_infinity (&wop))
{
status = sim_fpu_status_invalid_cvi;
update_fcsr (cpu, cia, status);
return status;
}
switch (fmt)
{
case fmt_single:
if (sim_fpu_is_ge (&wop, &wmagic))
wans = wop;
else
{
sim_fpu_add (&wtemp, &wop, &wmagic);
sim_fpu_round_32 (&wtemp, round, sim_fpu_denorm_default);
sim_fpu_sub (&wans, &wtemp, &wmagic);
}
sim_fpu_to32 ((uint32_t *) ans, &wans);
break;
case fmt_double:
if (sim_fpu_is_ge (&wop, &wmagic))
wans = wop;
else
{
sim_fpu_add (&wtemp, &wop, &wmagic);
sim_fpu_round_64 (&wtemp, round, sim_fpu_denorm_default);
sim_fpu_sub (&wans, &wtemp, &wmagic);
}
sim_fpu_to64 (ans, &wans);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
if (*ans != op && status == 0)
status = sim_fpu_status_inexact;
update_fcsr (cpu, cia, status);
return status;
}
void
fp_cmp(sim_cpu *cpu,
address_word cia,
@ -620,11 +729,91 @@ fp_cmp(sim_cpu *cpu,
break;
}
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
}
uint64_t
fp_r6_cmp (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
FP_formats fmt,
int cond)
{
sim_fpu wop1, wop2;
int result = 0;
int signalling = cond & 0x8;
switch (fmt)
{
case fmt_single:
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
break;
case fmt_double:
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
switch (cond)
{
case FP_R6CMP_AF:
result = 0;
break;
case FP_R6CMP_UN:
result = sim_fpu_is_un (&wop1, &wop2);
break;
case FP_R6CMP_OR:
result = sim_fpu_is_or (&wop1, &wop2);
break;
case FP_R6CMP_EQ:
result = sim_fpu_is_eq (&wop1, &wop2);
break;
case FP_R6CMP_NE:
result = sim_fpu_is_ne (&wop1, &wop2);
break;
case FP_R6CMP_LT:
result = sim_fpu_is_lt (&wop1, &wop2);
break;
case FP_R6CMP_LE:
result = sim_fpu_is_le (&wop1, &wop2);
break;
case FP_R6CMP_UEQ:
result = sim_fpu_is_un (&wop1, &wop2) || sim_fpu_is_eq (&wop1, &wop2);
break;
case FP_R6CMP_UNE:
result = sim_fpu_is_un (&wop1, &wop2) || sim_fpu_is_ne (&wop1, &wop2);
break;
case FP_R6CMP_ULT:
result = sim_fpu_is_un (&wop1, &wop2) || sim_fpu_is_lt (&wop1, &wop2);
break;
case FP_R6CMP_ULE:
result = sim_fpu_is_un (&wop1, &wop2) || sim_fpu_is_le (&wop1, &wop2);
break;
default:
update_fcsr (cpu, cia, sim_fpu_status_invalid_cmp);
break;
}
if (result)
{
switch (fmt)
{
case fmt_single:
return 0xFFFFFFFF;
case fmt_double:
return 0xFFFFFFFFFFFFFFFF;
default:
sim_io_error (SD, "Bad switch\n");
}
}
else
return 0;
}
/* Basic arithmetic operations. */
@ -635,7 +824,7 @@ fp_unary(sim_cpu *cpu,
uint64_t op,
FP_formats fmt)
{
sim_fpu wop;
sim_fpu wop = {0};
sim_fpu ans;
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_denorm denorm = denorm_mode (cpu);
@ -680,8 +869,7 @@ fp_unary(sim_cpu *cpu,
break;
}
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status);
@ -696,9 +884,9 @@ fp_binary(sim_cpu *cpu,
uint64_t op2,
FP_formats fmt)
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
sim_fpu wop1 = {0};
sim_fpu wop2 = {0};
sim_fpu ans = {0};
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_denorm denorm = denorm_mode (cpu);
sim_fpu_status status = 0;
@ -746,8 +934,7 @@ fp_binary(sim_cpu *cpu,
break;
}
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status);
@ -786,7 +973,7 @@ inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
ans.normal_exp += scale;
status |= sim_fpu_round_32 (&ans, round, denorm);
wop1 = ans;
op_status = 0;
op_status = 0;
sim_fpu_32to (&wop2, op3);
op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
op_status |= sim_fpu_round_32 (&ans, round, denorm);
@ -812,7 +999,7 @@ inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
ans.normal_exp += scale;
status |= sim_fpu_round_64 (&ans, round, denorm);
wop1 = ans;
op_status = 0;
op_status = 0;
sim_fpu_64to (&wop2, op3);
op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
op_status |= sim_fpu_round_64 (&ans, round, denorm);
@ -881,8 +1068,89 @@ fp_mac(sim_cpu *cpu,
break;
}
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status);
return result;
}
/* Common FMAC code for .s, .d. Defers setting FCSR to caller. */
static sim_fpu_status
inner_fmac (sim_cpu *cpu,
int (*sim_fpu_op) (sim_fpu *, const sim_fpu *, const sim_fpu *),
uint64_t op1,
uint64_t op2,
uint64_t op3,
sim_fpu_round round,
sim_fpu_denorm denorm,
FP_formats fmt,
uint64_t *result)
{
sim_fpu wop1, wop2, ans;
sim_fpu_status status = 0;
sim_fpu_status op_status;
uint32_t t32 = 0;
uint64_t t64 = 0;
switch (fmt)
{
case fmt_single:
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
status |= sim_fpu_mul (&ans, &wop1, &wop2);
wop1 = ans;
op_status = 0;
sim_fpu_32to (&wop2, op3);
op_status |= (*sim_fpu_op) (&ans, &wop2, &wop1);
op_status |= sim_fpu_round_32 (&ans, round, denorm);
status |= op_status;
sim_fpu_to32 (&t32, &ans);
t64 = t32;
break;
case fmt_double:
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
status |= sim_fpu_mul (&ans, &wop1, &wop2);
wop1 = ans;
op_status = 0;
sim_fpu_64to (&wop2, op3);
op_status |= (*sim_fpu_op) (&ans, &wop2, &wop1);
op_status |= sim_fpu_round_64 (&ans, round, denorm);
status |= op_status;
sim_fpu_to64 (&t64, &ans);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
*result = t64;
return status;
}
static uint64_t
fp_fmac (sim_cpu *cpu,
address_word cia,
int (*sim_fpu_op) (sim_fpu *, const sim_fpu *, const sim_fpu *),
uint64_t op1,
uint64_t op2,
uint64_t op3,
FP_formats fmt)
{
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_denorm denorm = denorm_mode (cpu);
sim_fpu_status status = 0;
uint64_t result = 0;
switch (fmt)
{
case fmt_single:
case fmt_double:
status = inner_fmac (cpu, sim_fpu_op, op1, op2, op3,
round, denorm, fmt, &result);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status);
@ -972,8 +1240,7 @@ fp_inv_sqrt(sim_cpu *cpu,
break;
}
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status);
@ -1039,6 +1306,94 @@ fp_div(sim_cpu *cpu,
return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt);
}
uint64_t
fp_min (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
FP_formats fmt)
{
return fp_binary (cpu, cia, &sim_fpu_min, op1, op2, fmt);
}
uint64_t
fp_max (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
FP_formats fmt)
{
return fp_binary (cpu, cia, &sim_fpu_max, op1, op2, fmt);
}
uint64_t
fp_mina (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
FP_formats fmt)
{
uint64_t ret;
sim_fpu wop1 = {0}, wop2 = {0}, waop1, waop2, wans;
sim_fpu_status status = 0;
switch (fmt)
{
case fmt_single:
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
break;
case fmt_double:
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
status |= sim_fpu_abs (&waop1, &wop1);
status |= sim_fpu_abs (&waop2, &wop2);
status |= sim_fpu_min (&wans, &waop1, &waop2);
ret = (sim_fpu_is_eq (&wans, &waop1)) ? op1 : op2;
update_fcsr (cpu, cia, status);
return ret;
}
uint64_t
fp_maxa (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
FP_formats fmt)
{
uint64_t ret;
sim_fpu wop1 = {0}, wop2 = {0}, waop1, waop2, wans;
sim_fpu_status status = 0;
switch (fmt)
{
case fmt_single:
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
break;
case fmt_double:
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
break;
default:
sim_io_error (SD, "Bad switch\n");
}
status |= sim_fpu_abs (&waop1, &wop1);
status |= sim_fpu_abs (&waop2, &wop2);
status |= sim_fpu_max (&wans, &waop1, &waop2);
ret = (sim_fpu_is_eq (&wans, &waop1)) ? op1 : op2;
update_fcsr (cpu, cia, status);
return ret;
}
uint64_t
fp_recip(sim_cpu *cpu,
address_word cia,
@ -1088,6 +1443,28 @@ fp_msub(sim_cpu *cpu,
return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt);
}
uint64_t
fp_fmadd (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
uint64_t op3,
FP_formats fmt)
{
return fp_fmac (cpu, cia, &sim_fpu_add, op1, op2, op3, fmt);
}
uint64_t
fp_fmsub (sim_cpu *cpu,
address_word cia,
uint64_t op1,
uint64_t op2,
uint64_t op3,
FP_formats fmt)
{
return fp_fmac (cpu, cia, &sim_fpu_sub, op1, op2, op3, fmt);
}
uint64_t
fp_nmadd(sim_cpu *cpu,
address_word cia,
@ -1394,8 +1771,7 @@ convert (sim_cpu *cpu,
status = sim_fpu_i64to (&wop, op, round);
break;
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
/* Convert sim_fpu format into the output */
@ -1430,8 +1806,7 @@ convert (sim_cpu *cpu,
break;
default:
result64 = 0;
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status);
@ -1481,8 +1856,7 @@ pack_ps(sim_cpu *cpu,
break;
}
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
return result;
@ -1517,8 +1891,7 @@ convert_ps (sim_cpu *cpu,
sim_fpu_32to (&wop_l, FP_PS_lower(op));
break;
default:
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
/* Convert sim_fpu format into the output */
@ -1538,8 +1911,7 @@ convert_ps (sim_cpu *cpu,
break;
default:
result = 0;
sim_io_eprintf (SD, "Bad switch\n");
abort ();
sim_io_error (SD, "Bad switch\n");
}
update_fcsr (cpu, cia, status_u | status_l);

2
sim/mips/cp1.h
View File

@ -43,6 +43,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* FCSR bits for IEEE754-2008 compliance. */
#define fcsr_NAN2008_mask (0x00040000)
#define fcsr_NAN2008_shift (18)
#define fcsr_ABS2008_mask (0x00080000)
#define fcsr_ABS2008_shift (19)
#define fenr_FS (0x00000004)

6
sim/mips/interp.c
View File

@ -1549,6 +1549,10 @@ store_word (SIM_DESC sd,
}
}
#define MIPSR6_P(abfd) \
((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6 \
|| (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6)
/* Load a word from memory. */
static signed_word
@ -1557,7 +1561,7 @@ load_word (SIM_DESC sd,
address_word cia,
uword64 vaddr)
{
if ((vaddr & 3) != 0)
if ((vaddr & 3) != 0 && !MIPSR6_P (STATE_PROG_BFD (sd)))
{
SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
}

4
sim/mips/micromips.igen
View File

@ -1761,7 +1761,7 @@
*micromips32:
*micromips64:
{
do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0);
do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0, 1);
}
@ -3074,7 +3074,7 @@
*micromips64:
{
check_u64 (SD_, instruction_0);
do_scd (SD_, RT, OFFSET, BASE);
do_scd (SD_, RT, OFFSET, BASE, 1);
}
110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD

380
sim/mips/mips.igen
View File

File diff suppressed because it is too large Load Diff

30
sim/mips/mips3264r2.igen
View File

@ -193,6 +193,7 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dext (SD_, RT, RS, LSB, SIZE);
@ -201,6 +202,7 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dextm (SD_, RT, RS, LSB, SIZE);
@ -209,6 +211,7 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dextu (SD_, RT, RS, LSB, SIZE);
@ -219,7 +222,9 @@
"di":RT == 0
"di r<RT>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_di (SD_, RT);
}
@ -228,6 +233,7 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dins (SD_, RT, RS, LSB, MSB);
@ -236,6 +242,7 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dinsm (SD_, RT, RS, LSB, MSB);
@ -244,6 +251,7 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dinsu (SD_, RT, RS, LSB, MSB);
@ -253,6 +261,7 @@
011111,00000,5.RT,5.RD,00010,100100::64::DSBH
"dsbh r<RD>, r<RT>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dsbh (SD_, RD, RT);
@ -261,6 +270,7 @@
011111,00000,5.RT,5.RD,00101,100100::64::DSHD
"dshd r<RD>, r<RT>"
*mips64r2:
*mips64r6:
{
check_u64 (SD_, instruction_0);
do_dshd (SD_, RD, RT);
@ -270,7 +280,9 @@
"ei":RT == 0
"ei r<RT>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_ei (SD_, RT);
}
@ -279,7 +291,9 @@
011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
"ext r<RT>, r<RS>, <LSB>, <SIZE+1>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_ext (SD_, RT, RS, LSB, SIZE);
}
@ -288,7 +302,9 @@
010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1
"mfhc1 r<RT>, f<FS>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_mfhc1 (SD_, RT, FS);
}
@ -296,7 +312,9 @@
010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
"mthc1 r<RT>, f<FS>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_mthc1 (SD_, RT, FS);
}
@ -305,7 +323,9 @@
011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
"ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_ins (SD_, RT, RS, LSB, MSB);
}
@ -314,7 +334,9 @@
011111,00000,5.RT,5.RD,10000,100000::32::SEB
"seb r<RD>, r<RT>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_seb (SD_, RD, RT);
}
@ -322,7 +344,9 @@
011111,00000,5.RT,5.RD,11000,100000::32::SEH
"seh r<RD>, r<RT>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_seh (SD_, RD, RT);
}
@ -331,7 +355,9 @@
000001,5.BASE,11111,16.OFFSET::32::SYNCI
"synci <OFFSET>(r<BASE>)"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
// sync i-cache - nothing to do currently
}
@ -340,7 +366,9 @@
011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
"rdhwr r<RT>, r<RD>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_rdhwr (SD_, RT, RD);
}
@ -349,7 +377,9 @@
011111,00000,5.RT,5.RD,00010,100000::32::WSBH
"wsbh r<RD>, r<RT>"
*mips32r2:
*mips32r6:
*mips64r2:
*mips64r6:
{
do_wsbh (SD_, RD, RT);
}

1226
sim/mips/mips3264r6.igen Normal file
View File

File diff suppressed because it is too large Load Diff

94
sim/mips/sim-main.h
View File

@ -26,6 +26,8 @@ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ER
#include "sim-basics.h"
#include "sim-base.h"
#include "bfd.h"
#include "elf-bfd.h"
#include "elf/mips.h"
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
@ -72,6 +74,9 @@ typedef enum {
fmt_word = 4,
fmt_long = 5,
fmt_ps = 6,
/* The following is a special case for FP conditions where only
the lower 32bits are considered. This is a HACK. */
fmt_dc32 = 7,
/* The following are well outside the normal acceptable format
range, and are used in the register status vector. */
fmt_unknown = 0x10000000,
@ -261,6 +266,7 @@ struct _sim_cpu {
#define DSPC ((CPU)->dspc)
#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
#define FORBIDDEN_SLOT() { NIA = forbiddenslot32 (SD_); }
#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
@ -271,15 +277,16 @@ struct _sim_cpu {
#define DSSTATE ((CPU)->dsstate)
/* Flags in the "state" variable: */
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
#define simPCOC0 (1 << 17) /* COC[1] from current */
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
#define simTRACE (1 << 8) /* 1 = trace address activity */
#define simPCOC0 (1 << 17) /* COC[1] from current */
#define simPCOC1 (1 << 18) /* COC[1] from previous */
#define simDELAYSLOT (1 << 24) /* 1 = delay slot entry exists */
#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
#define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */
#ifndef ENGINE_ISSUE_PREFIX_HOOK
#define ENGINE_ISSUE_PREFIX_HOOK() \
@ -532,6 +539,10 @@ struct mips_sim_state {
/* Bits reserved for implementations: */
#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
/* From R6 onwards, some instructions (e.g. ADDIUPC) change behaviour based
* on the Status.UX bits to either sign extend, or act as full 64 bit. */
#define status_optional_EXTEND32(x) ((SR & status_UX) ? x : EXTEND32(x))
#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
#define cause_CE_mask 0x30000000 /* Coprocessor exception */
@ -719,8 +730,55 @@ void test_fcsr (SIM_STATE);
/* FPU operations. */
void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, int abs, int cond, int cc);
#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
/* Non-signalling */
#define FP_R6CMP_AF 0x0
#define FP_R6CMP_EQ 0x2
#define FP_R6CMP_LE 0x6
#define FP_R6CMP_LT 0x4
#define FP_R6CMP_NE 0x13
#define FP_R6CMP_OR 0x11
#define FP_R6CMP_UEQ 0x3
#define FP_R6CMP_ULE 0x7
#define FP_R6CMP_ULT 0x5
#define FP_R6CMP_UN 0x1
#define FP_R6CMP_UNE 0x12
/* Signalling */
#define FP_R6CMP_SAF 0x8
#define FP_R6CMP_SEQ 0xa
#define FP_R6CMP_SLE 0xe
#define FP_R6CMP_SLT 0xc
#define FP_R6CMP_SNE 0x1b
#define FP_R6CMP_SOR 0x19
#define FP_R6CMP_SUEQ 0xb
#define FP_R6CMP_SULE 0xf
#define FP_R6CMP_SULT 0xd
#define FP_R6CMP_SUN 0x9
#define FP_R6CMP_SUNE 0x1a
/* FPU Class */
#define FP_R6CLASS_SNAN (1<<0)
#define FP_R6CLASS_QNAN (1<<1)
#define FP_R6CLASS_NEGINF (1<<2)
#define FP_R6CLASS_NEGNORM (1<<3)
#define FP_R6CLASS_NEGSUB (1<<4)
#define FP_R6CLASS_NEGZERO (1<<5)
#define FP_R6CLASS_POSINF (1<<6)
#define FP_R6CLASS_POSNORM (1<<7)
#define FP_R6CLASS_POSSUB (1<<8)
#define FP_R6CLASS_POSZERO (1<<9)
void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt,
int abs, int cond, int cc);
#define Compare(op1,op2,fmt,cond,cc) \
fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
uint64_t fp_r6_cmp (SIM_STATE, uint64_t op1, uint64_t op2,
FP_formats fmt, int cond);
#define R6Compare(op1,op2,fmt,cond) fp_r6_cmp(SIM_ARGS, op1, op2, fmt, cond)
uint64_t fp_classify(SIM_STATE, uint64_t op, FP_formats fmt);
#define Classify(op, fmt) fp_classify(SIM_ARGS, op, fmt)
int fp_rint(SIM_STATE, uint64_t op, uint64_t *ans, FP_formats fmt);
#define RoundToIntegralExact(op, ans, fmt) fp_rint(SIM_ARGS, op, ans, fmt)
uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt);
#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt);
@ -733,6 +791,14 @@ uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
uint64_t fp_min (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Min(op1,op2,fmt) fp_min(SIM_ARGS, op1, op2, fmt)
uint64_t fp_max (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Max(op1,op2,fmt) fp_max(SIM_ARGS, op1, op2, fmt)
uint64_t fp_mina (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define MinA(op1,op2,fmt) fp_mina(SIM_ARGS, op1, op2, fmt)
uint64_t fp_maxa (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define MaxA(op1,op2,fmt) fp_maxa(SIM_ARGS, op1, op2, fmt)
uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt);
#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt);
@ -741,6 +807,12 @@ uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt);
#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2,
uint64_t op3, FP_formats fmt);
#define FusedMultiplyAdd(op1,op2,op3,fmt) fp_fmadd(SIM_ARGS, op1, op2, op3, fmt)
uint64_t fp_fmadd (SIM_STATE, uint64_t op1, uint64_t op2,
uint64_t op3, FP_formats fmt);
#define FusedMultiplySub(op1,op2,op3,fmt) fp_fmsub(SIM_ARGS, op1, op2, op3, fmt)
uint64_t fp_fmsub (SIM_STATE, uint64_t op1, uint64_t op2,
uint64_t op3, FP_formats fmt);
#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2,
uint64_t op3, FP_formats fmt);

72
sim/testsuite/mips/basic.exp
View File

@ -35,13 +35,61 @@ proc run_micromips_test { name requested_machs } {
unset ASFLAGS_FOR_TARGET
}
# Runs endian tests
proc run_endian_tests { name requested_machs } {
global ASFLAGS_FOR_TARGET
global LDFLAGS_FOR_TARGET
run_sim_test $name $requested_machs
set ASFLAGS_FOR_TARGET "-EL"
set LDFLAGS_FOR_TARGET "-EL"
run_sim_test $name $requested_machs
unset ASFLAGS_FOR_TARGET
unset LDFLAGS_FOR_TARGET
}
# Runs all specified tests
proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } {
run_sim_test $name $requested_machs
run_micromips_test $name $requested_micromips_machs
}
# Runs the combination of instructions removed in R6 through the testsuite
proc run_r6_removed_test {testfile models} {
global subdir srcdir
set fd [open "$srcdir/$subdir/r6-removed.csv" r]
set file_data [read $fd]
close $fd
set data [split $file_data "\n"]
foreach line $data {
set line_contents [split $line ","]
set mnemonic [lindex $line_contents 0]
set insn [lindex $line_contents 1]
if {[string compare $insn ""] == 1} {
set contents ""
append contents ".macro removed_instr\n"
append contents ".word $insn\n"
append contents "nop\n"
append contents ".endm"
verbose -log "r6-removed test: $mnemonic\n$contents"
set file [open r6-removed.inc w]
puts $file $contents
close $file
run_sim_test $testfile $models
}
}
}
if {[istarget *]} {
# Used to locate the `run` program.
global arch
set arch "mips"
set dspmodels ""
set mdmxmodels ""
set micromipsmodels ""
@ -51,18 +99,24 @@ if {[istarget *]} {
set models "sb1"
set submodels "mips1 mips2 mips3 mips4 mips32 mips64"
append mdmxmodels " mips64"
} elseif {[istarget mipsisa64r6*-*-elf]} {
set models "mips32r6 mips64r6"
set submodels ""
} elseif {[istarget mipsisa64*-*-elf]} {
set models "mips32 mips64 mips32r2 mips64r2"
set submodels "mips1 mips2 mips3 mips4"
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
} elseif {[istarget mips*-sde-elf*] || [istarget mips*-mti-elf*]} {
set models "mips32 mips64 mips32r2 mips64r2"
set models "mips32 mips64 mips32r2 mips64r2 mips32r6 mips64r6"
set submodels ""
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
append micromipsmodels " mips32r2"
append dspmodels " mips32r2 mips64r2 mips32r6 mips64r6"
append mdmxmodels " mips64 mips32r2 mips64r2 mips32r6 mips64r6"
append micromipsmodels " mips32r2 mips64r2"
append micromipsdspmodels " mips32r2 mips64r2"
} elseif {[istarget mipsisa32r6*-*-elf]} {
set models "mips32r6"
set submodels ""
} elseif {[istarget mipsisa32*-*-elf]} {
set models "mips32 mips32r2"
set submodels "mips1 mips2"
@ -102,4 +156,14 @@ if {[istarget *]} {
run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels
run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels
run_sim_test r2-fpu.s $models
run_sim_test r6-fpu.s $models
run_sim_test r6.s $models
run_sim_test r6-forbidden.s $models
run_r6_removed_test r6-removed.s $models
run_sim_test r6-64.s $models
run_sim_test r6-branch.s $models
run_endian_tests r6-llsc-wp.s $models
run_endian_tests r6-llsc-dp.s $models
}

2
sim/testsuite/mips/hilo-hazard-3.s
View File

@ -1,6 +1,6 @@
# Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
#
# mach: all
# mach: -mips32r6 -mips64r6 all
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: pass\\n

31
sim/testsuite/mips/r2-fpu.s Normal file
View File

@ -0,0 +1,31 @@
# mips r2 fpu tests
# mach: mips32r2 mips64r2
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test qNaN format is 754-1985"
li $6, 0x7fbfffff
mtc1 $0, $f2
mtc1 $0, $f4
div.s $f6, $f2, $f4
mfc1 $8, $f6
beq $8, $6, L1
nop
fail
L1:
#TODO: More tests?
pass
.end DIAG

157
sim/testsuite/mips/r6-64.s Normal file
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@ -0,0 +1,157 @@
# mips64 specific r6 tests (non FPU)
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
.data
d0: .dword 0
dval: .dword 0xaa55bb66cc77dd88
d1: .dword 0xaaaabbbbccccdddd
d2: .dword 256
dlo: .dword 0xaabbbbccccdddd00
dhi: .dword 0xffffffffffffffaa
dhiu: .dword 0x00000000000000aa
d3: .dword 0xffaaaabbbbccccde
d4: .dword 0xffffffffffffffdd
d5: .dword 0x00000000000000dd
d6: .dword 0x00aaaabbbbccccdd
d7: .dword 0xeeeeffff00001111
d8: .dword 0xbbccccddddeeeeff
d9: .dword 0x000000ddaaaabbbb
d10: .dword 0x5555dddd3333bbbb
d11: .dword 0x9999999999999999
d12: .dword 56
d13: .dword 8
d14: .dword 57
d15: .dword 0x000000ddaaaac98b
d16: .dword 0xffffffffdead00dd
d17: .dword 0xffffffffc0de0000
d18: .dword 0x0000123400000000
d19: .dword 0xffffabcddead00dd
d20: .dword 0xc0de000000000000
d21: .dword 0x8000abcddead00dd
dmask:.dword 0xffffffffffff0000
dval1: .word 0x1234abcd
dval2: .word 0xffee0000
dval3: .dword 0xffffffffffffffff
.fill 240,1,0
dval4: .dword 0x5555555555555555
.fill 264,1,0
dval5: .dword 0xaaaaaaaaaaaaaaaa
.text
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test DMUL"
r6ck_2r dmul, 6, 5, 30
r6ck_2r dmul, -7, 9, -63
r6ck_2r dmul, -1, 1, -1
r6ck_2dr dmul, d1, d2, dlo
writemsg "[2] Test DMUH"
r6ck_2r dmuh, 6, 5, 0
r6ck_2r dmuh, -7, 9, 0xffffffffffffffff
r6ck_2r dmuh, -1, 1, -1
r6ck_2dr dmuh, d1, d2, dhi
writemsg "[3] Test DMULU"
r6ck_2r dmulu, 12, 10, 120
r6ck_2r dmulu, -1, 1, -1
r6ck_2dr dmulu, d1, d2, dlo
writemsg "[4] Test DMUHU"
r6ck_2r dmuhu, 12, 10, 0
r6ck_2r dmuhu, -1, 1, 0
r6ck_2dr dmuhu, d1, d2, dhiu
writemsg "[5] Test DDIV"
r6ck_2r ddiv, 10001, 10, 1000
r6ck_2r ddiv, -123456, 560, -220
r6ck_2dr ddiv, d1, d2, d3
writemsg "[6] Test DMOD"
r6ck_2r dmod, 10001, 10, 1
r6ck_2r dmod, -123456, 560, 0xffffffffffffff00
r6ck_2dr dmod, d1, d2, d4
writemsg "[7] Test DDIVU"
r6ck_2r ddivu, 9, 100, 0
r6ck_2dr ddivu, d1, d2, d6
writemsg "[8] Test DMODU"
r6ck_2r dmodu, 9, 100, 9
r6ck_2dr dmodu, d1, d2, d5
writemsg "[9] Test DALIGN"
r6ck_2dr1i dalign, d7, d1, 3, d8
r6ck_2dr1i dalign, d1, d5, 4, d9
writemsg "[10] Test DBITSWAP"
r6ck_1dr dbitswap, d1, d10
r6ck_1dr dbitswap, d11, d11
writemsg "[11] Test DCLZ"
r6ck_1dr dclz, d5, d12
r6ck_1dr dclz, d6, d13
writemsg "[12] Test DCLO"
r6ck_1dr dclo, d5, d0
r6ck_1dr dclo, dhi, d14
writemsg "[13] Test DLSA"
r6ck_2r1i dlsa, 0x82, 0x2000068, 4, 0x2000888
r6ck_2dr1i dlsa, d5, d9, 4, d15
writemsg "[14] Test DAUI"
r6ck_1dr1i daui, d5, 0xdead, d16
r6ck_1dr1i daui, d0, 0xc0de, d17
writemsg "[15] Test DAHI"
r6ck_0dr1i dahi, d0, 0x1234, d18
r6ck_0dr1i dahi, d16, 0xabce, d19
writemsg "[16] Test DATI"
r6ck_0dr1i dati, d0, 0xc0de, d20
r6ck_0dr1i dati, d19, 0x8001, d21
writemsg "[17] Test LDPC"
ld $5, dval
nop
ldpc $4, dval
fp_assert $4, $5
writemsg "[18] Test LWUPC"
lwu $5, dval1
lwupc $4, dval1
fp_assert $4, $5
lwu $5, dval2
lwupc $4, dval2
fp_assert $4, $5
writemsg "[19] Test LLD"
ld $5, dval3
dla $3, dval4
lld $4, -248($3)
fp_assert $4, $5
writemsg "[20] Test SCD"
lld $4, -248($3)
dli $4, 0xafaf
scd $4, -248($3)
ld $5, dval3
dli $4, 0xafaf
fp_assert $4, $5
pass
.end DIAG

291
sim/testsuite/mips/r6-branch.s Normal file
View File

@ -0,0 +1,291 @@
# mips r6 branch tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
li $14, 0xffffffff
li $13, 0x123
li $12, 0x45
li $7, 0x45
li $8, 0xfffffffe
li $9, 2147483647
li $11, 0
writemsg "[1] Test BOVC"
bovc $12, $13, Lfail
nop
bovc $9, $13, L2
nop
fail
L2:
writemsg "[2] Test BNVC"
bnvc $9, $13, Lfail
nop
bnvc $12, $13, L3
nop
fail
L3:
writemsg "[3] Test BEQC"
beqc $12, $13, Lfail
nop
beqc $12, $7, L4
nop
fail
L4:
writemsg "[4] Test BNEC"
bnec $12, $7, Lfail
nop
bnec $12, $13, L5
nop
fail
L5:
writemsg "[5] Test BLTC"
bltc $13, $12, Lfail
nop
bltc $12, $13, L6
nop
fail
L6:
# writemsg "[6] Test BLEC"
# blec $13, $12, Lfail
# nop
# blec $7, $12, L7
# nop
# fail
L7:
writemsg "[7] Test BGEC"
bgec $12, $13, Lfail
nop
bgec $13, $12, L8
nop
fail
L8:
# writemsg "[8] Test BGTC"
# bgtc $12, $13, Lfail
# nop
# bgtc $13, $12, L9
# nop
# fail
L9:
writemsg "[9] Test BLTUC"
bltuc $14, $13, Lfail
nop
bltuc $8, $14, L10
nop
fail
L10:
# writemsg "[10] Test BLEUC"
# bleuc $14, $13, Lfail
# nop
# bleuc $8, $14, L11
# nop
# fail
L11:
writemsg "[11] Test BGEUC"
bgeuc $13, $14, Lfail
nop
bgeuc $14, $8, L12
nop
fail
L12:
# writemsg "[12] Test BGTUC"
# bgtuc $13, $14, Lfail
# nop
# bgtuc $14, $8, L13
# nop
# fail
L13:
writemsg "[13] Test BLTZC"
bltzc $13, Lfail
nop
bltzc $11, Lfail
nop
bltzc $14, L14
nop
fail
L14:
writemsg "[14] Test BLEZC"
blezc $13, Lfail
nop
blezc $11, L145
nop
fail
L145:
blezc $14, L15
nop
fail
L15:
writemsg "[15] Test BGEZC"
bgezc $8, Lfail
nop
bgezc $11, L155
nop
fail
L155:
bgezc $13, L16
nop
fail
L16:
writemsg "[16] Test BGTZC"
bgtzc $8, Lfail
nop
bgtzc $11, Lfail
nop
bgtzc $13, L17
nop
fail
li $10, 0
L17:
writemsg "[17] Test BLEZALC"
blezalc $12, Lfail
nop
blezalc $11, Lret
li $10, 1
beqzc $10, L175
nop
fail
L175:
blezalc $14, Lret
li $10, 1
beqzc $10, L18
nop
fail
L18:
writemsg "[18] Test BGEZALC"
bgezalc $14, Lfail
nop
bgezalc $11, Lret
li $10, 1
beqzc $10, L185
nop
fail
L185:
bgezalc $12, Lret
li $10, 1
beqzc $10, L19
nop
fail
L19:
writemsg "[19] Test BGTZALC"
bgtzalc $14, Lfail
nop
bgtzalc $11, Lfail
nop
bgtzalc $12, Lret
li $10, 1
beqzc $10, L20
nop
fail
L20:
writemsg "[20] Test BLTZALC"
bltzalc $12, Lfail
nop
bltzalc $11, Lfail
nop
bltzalc $14, Lret
li $10, 1
beqzc $10, L21
nop
fail
L21:
writemsg "[21] Test BC"
bc L22
fail
L22:
writemsg "[22] Test BALC"
balc Lret
li $10, 1
beqzc $10, L23
nop
fail
L23:
writemsg "[23] Test JIC"
jal GetPC
nop
jic $6, 4
nop
fail
L24:
writemsg "[24] Test JIALC"
li $10, 1
jal GetPC
nop
jialc $6, 20
nop
beqzc $10, L25
nop
fail
LJIALCRET:
li $10, 0
jr $ra
nop
L25:
writemsg "[25] Test NAL"
jal GetPC
nop
move $11, $6
nal
nop
addiu $11, 12
beqc $11, $31, L26
nop
fail
L26:
writemsg "[26] Test BAL"
balc Lret
li $10, 1
beqzc $10, Lend
nop
fail
Lend:
pass
Lfail:
fail
.end DIAG
Lret:
li $10, 0
addiu $ra, 4
jr $ra
nop

51
sim/testsuite/mips/r6-forbidden.s Normal file
View File

@ -0,0 +1,51 @@
# mips r6 test for forbidden slot behaviour
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\nReservedInstruction at PC = *\\nprogram stopped with signal 4 (Illegal instruction).\\n
# xerror:
.include "testutils.inc"
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test if FS is ignored when branch is taken"
li $4, 0
beqzalc $4, L1
bc L2
L2:
fail
L1:
writemsg "[2] Test if FS is used when branch is not taken"
li $4, 1
blezc $4, L3
addiu $4, $4, 1
li $2, 2
beq $4, $2, L4
L3:
nop
fail
L4:
writemsg "[3] Test if FS causes an error when it contains a branch"
li $4, 3
beqzalc $4, L6
bc L5
L5:
nop
fail
L6:
#There is no passing condition here, all routes to the end indicate failure
fail
.end DIAG

446
sim/testsuite/mips/r6-fpu.s Normal file
View File

@ -0,0 +1,446 @@
# mips r6 fpu test for FMADD/FMSUB etc.
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test qNaN format is 754-2008"
li $4, 0x0
li $5, 0x0
li $6, 0x7fc00000
mtc1 $4, $f2
mtc1 $5, $f4
div.s $f6, $f2, $f4
mfc1 $8, $f6
fp_assert $6, $8
writemsg "[2] Test maddf.s"
r6ck_3s maddf.s, 0x0, 0x0, 0x0, 0x0
r6ck_3s maddf.s, 0x3f800000, 0x3f800000, 0x3f800000, 0x40000000
r6ck_3s maddf.s, 0xc0b1f5c3, 0x40490fd0, 0x402df854, 0x403e9f5d
writemsg "[3] Test maddf.d"
r6ck_3d maddf.d, 0x0, 0x0, 0x0, 0x0
r6ck_3d maddf.d, 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000, 0x4000000000000000
r6ck_3d maddf.d, 0xc0163eb851eb851f, 0x400921f9f01b866e, 0x4005bf0a8b24919b, 0x4007d3ebc14f6cee
writemsg "[4] Test msubf.s"
r6ck_3s msubf.s, 0x0, 0x0, 0x0, 0x0
r6ck_3s msubf.s, 0x3f800000, 0x3f800000, 0x3f800000, 0x0
r6ck_3s msubf.s, 0xc0b1f5c3, 0x40490fd0, 0x402df854, 0xc1619d9a
writemsg "[5] Test msubf.d"
r6ck_3d msubf.d, 0x0, 0x0, 0x0, 0x0
r6ck_3d msubf.d, 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d msubf.d, 0xc0163eb851eb851f, 0x400921f9f01b866e, 0x4005bf0a8b24919b, 0xc02c33b3423f605b
writemsg "[6] Test CMP.af.s"
r6ck_3s cmp.af.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.af.s, 0x0, 0x00000000, 0x3f800000, 0x0
writemsg "[7] Test CMP.af.d"
r6ck_3d cmp.af.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.af.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0
writemsg "[8] Test CMP.eq.s"
r6ck_3s cmp.eq.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.eq.s, 0x0, 0x00000000, 0x3f800000, 0x0
r6ck_3s cmp.eq.s, 0x0, 0x80000000, 0x00000000, 0xffffffff
r6ck_3s cmp.eq.s, 0x0, 0x7fc00000, 0x7fc00000, 0x0
r6ck_3s cmp.eq.s, 0x0, 0x7fc00000, 0xffc00000, 0x0
r6ck_3s cmp.eq.s, 0x0, 0x7fa00000, 0x7fa00000, 0x0
r6ck_3s cmp.eq.s, 0x0, 0x7fa00000, 0x7fc00000, 0x0
r6ck_3s cmp.eq.s, 0x0, 0x7f800000, 0x7f800000, 0xffffffff
r6ck_3s cmp.eq.s, 0x0, 0xff800000, 0xff800000, 0xffffffff
writemsg "[9] Test CMP.eq.d"
r6ck_3d cmp.eq.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.eq.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.eq.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0xffffffffffffffff
r6ck_3d cmp.eq.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0x0
r6ck_3d cmp.eq.d, 0x0, 0x7ff8000000000000, 0xffc0000000000000, 0x0
r6ck_3d cmp.eq.d, 0x0, 0x7fa0000000000000, 0x7fa0000000000000, 0xffffffffffffffff
r6ck_3d cmp.eq.d, 0x0, 0x7fa0000000000000, 0x7ff8000000000000, 0x0
r6ck_3d cmp.eq.d, 0x0, 0x7ff0000000000000, 0x7ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.eq.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0xffffffffffffffff
writemsg "[10] Test CMP.ne.s"
r6ck_3s cmp.ne.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ne.s, 0x0, 0x80000000, 0x00000000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0x7fc00000, 0x7fc00000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0x7fc00000, 0xffc00000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0x7fa00000, 0x7fa00000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0x7fa00000, 0x7fc00000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0x7f800000, 0x7f800000, 0x0
r6ck_3s cmp.ne.s, 0x0, 0xff800000, 0xff800000, 0x0
writemsg "[11] Test CMP.ne.d"
r6ck_3d cmp.ne.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ne.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0x7ff8000000000000, 0xffc0000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0x7fa0000000000000, 0x7fa0000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0x7fa0000000000000, 0x7ff8000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0x7ff0000000000000, 0x7ff0000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0x0
r6ck_3d cmp.ne.d, 0x0, 0xab19546120965720, 0x92452014f194abc3, 0xffffffffffffffff
writemsg "[12] Test CMP.lt.s"
r6ck_3s cmp.lt.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.lt.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
r6ck_3s cmp.lt.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.lt.s, 0x0, 0x3f800000, 0xbf800000, 0x0
r6ck_3s cmp.lt.s, 0x0, 0xff800000, 0xbf800000, 0xffffffff
r6ck_3s cmp.lt.s, 0x0, 0xbf800000, 0x7f800000, 0xffffffff
r6ck_3s cmp.lt.s, 0x0, 0xbf800000, 0xff800000, 0x0
r6ck_3s cmp.lt.s, 0x0, 0x7f800000, 0xbf800000, 0x0
writemsg "[13] Test CMP.lt.d"
r6ck_3d cmp.lt.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.lt.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.lt.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.lt.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
r6ck_3d cmp.lt.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.lt.d, 0x0, 0xbff0000000000000, 0x7ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.lt.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0x0
r6ck_3d cmp.lt.d, 0x0, 0x7ff0000000000000, 0xbff0000000000000, 0x0
writemsg "[14] Test CMP.le.s"
r6ck_3s cmp.le.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.le.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
r6ck_3s cmp.le.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.le.s, 0x0, 0x3f800000, 0xbf800000, 0x0
r6ck_3s cmp.le.s, 0x0, 0xff800000, 0xbf800000, 0xffffffff
r6ck_3s cmp.le.s, 0x0, 0xbf800000, 0x7f800000, 0xffffffff
r6ck_3s cmp.le.s, 0x0, 0xbf800000, 0xff800000, 0x0
r6ck_3s cmp.le.s, 0x0, 0x7f800000, 0xbf800000, 0x0
writemsg "[15] Test CMP.le.d"
r6ck_3d cmp.le.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.le.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.le.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.le.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
r6ck_3d cmp.le.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.le.d, 0x0, 0xbff0000000000000, 0x7ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.le.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0x0
r6ck_3d cmp.le.d, 0x0, 0x7ff0000000000000, 0xbff0000000000000, 0x0
writemsg "[16] Test CMP.un.s"
r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0xbf800000, 0x0
r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.un.s, 0x0, 0x7fc01234, 0x7fc00000, 0xffffffff
r6ck_3s cmp.un.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0xff800000, 0x0
r6ck_3s cmp.un.s, 0x0, 0x3f800000, 0x7f800000, 0x0
writemsg "[17] Test CMP.un.d"
r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.un.d, 0x0, 0x7fc0123400000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.un.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0xfff0000000000000, 0x0
r6ck_3d cmp.un.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x0
writemsg "[18] Test CMP.or.s"
r6ck_3s cmp.or.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.or.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.or.s, 0x0, 0x3f800000, 0x7fc00000, 0x0
r6ck_3s cmp.or.s, 0x0, 0x7fc00000, 0x3f800000, 0x0
r6ck_3s cmp.or.s, 0x0, 0xffc00000, 0x3f800000, 0x0
r6ck_3s cmp.or.s, 0x0, 0x7fc01234, 0x7fc00000, 0x0
r6ck_3s cmp.or.s, 0x0, 0xff800000, 0x00000000, 0xffffffff
r6ck_3s cmp.or.s, 0x0, 0x00000000, 0x7f800000, 0xffffffff
r6ck_3s cmp.or.s, 0x0, 0x00000000, 0xff800000, 0xffffffff
r6ck_3s cmp.or.s, 0x0, 0x7f800000, 0x00000000, 0xffffffff
r6ck_3s cmp.or.s, 0x0, 0x7f800000, 0x00000000, 0xffffffff
writemsg "[19] Test CMP.or.d"
r6ck_3d cmp.or.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.or.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.or.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0x0
r6ck_3d cmp.or.d, 0x0, 0x7ff8000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.or.d, 0x0, 0xfff8000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.or.d, 0x0, 0x7ff8123492134352, 0x7ff8000000000000, 0x0
r6ck_3d cmp.or.d, 0x0, 0xfff0000000000000, 0x0000000000000000, 0xffffffffffffffff
r6ck_3d cmp.or.d, 0x0, 0x0000000000000000, 0x7ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.or.d, 0x0, 0x0000000000000000, 0xfff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.or.d, 0x0, 0x7ff0000000000000, 0x0000000000000000, 0xffffffffffffffff
r6ck_3d cmp.or.d, 0x0, 0x7ff0000000000000, 0x0000000000000000, 0xffffffffffffffff
writemsg "[20] Test CMP.ueq.s"
r6ck_3s cmp.ueq.s, 0x0, 0x3f800000, 0x00000000, 0x0
r6ck_3s cmp.ueq.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ueq.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ueq.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ueq.s, 0x0, 0x00000000, 0x3f800000, 0x0
r6ck_3s cmp.ueq.s, 0x0, 0x80000000, 0x00000000, 0xffffffff
r6ck_3s cmp.ueq.s, 0x0, 0x7f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ueq.s, 0x0, 0xff800000, 0xff800000, 0xffffffff
writemsg "[21] Test CMP.ueq.d"
r6ck_3d cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x0000000000000000, 0x0
r6ck_3d cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ueq.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ueq.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ueq.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.ueq.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0xffffffffffffffff
r6ck_3d cmp.ueq.d, 0x0, 0x7ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ueq.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0xffffffffffffffff
writemsg "[22] Test CMP.une.s"
r6ck_3s cmp.une.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.une.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.une.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.une.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.une.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
r6ck_3s cmp.une.s, 0x0, 0x80000000, 0x00000000, 0x0
r6ck_3s cmp.une.s, 0x0, 0x7f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.une.s, 0x0, 0xff800000, 0xff800000, 0x0
writemsg "[23] Test CMP.une.d"
r6ck_3d cmp.une.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.une.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.une.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.une.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.une.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.une.d, 0x0, 0x8000000000000000, 0x0000000000000000, 0x0
r6ck_3d cmp.une.d, 0x0, 0x7ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.une.d, 0x0, 0xfff0000000000000, 0xfff0000000000000, 0x0
writemsg "[24] Test CMP.ult.s"
r6ck_3s cmp.ult.s, 0x0, 0x3f800000, 0x3f800000, 0x0
r6ck_3s cmp.ult.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ult.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ult.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ult.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ult.s, 0x0, 0x3f800000, 0xbf800000, 0x0
writemsg "[25] Test CMP.ult.d"
r6ck_3d cmp.ult.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0x0
r6ck_3d cmp.ult.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ult.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ult.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ult.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ult.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
writemsg "[26] Test CMP.ule.s"
r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ule.s, 0x0, 0x7fc00000, 0x7fc00000, 0xffffffff
r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ule.s, 0x0, 0x00000000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ule.s, 0x0, 0xbf800000, 0x3f800000, 0xffffffff
r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0xbf800000, 0x0
r6ck_3s cmp.ule.s, 0x0, 0x3f800000, 0xff800000, 0x0
writemsg "[27] Test CMP.ule.d"
r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ule.d, 0x0, 0x7ff8000000000000, 0x7ff8000000000000, 0xffffffffffffffff
r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ule.d, 0x0, 0x0000000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ule.d, 0x0, 0xbff0000000000000, 0x3ff0000000000000, 0xffffffffffffffff
r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0xbff0000000000000, 0x0
r6ck_3d cmp.ule.d, 0x0, 0x3ff0000000000000, 0xfff0000000000000, 0x0
writemsg "[28] Test rint.s"
r6ck_2s rint.s, 0x0, 0x3fbf10cb, 0x3f800000
r6ck_2s rint.s, 0x0, 0xb9011423, 0x0
r6ck_2s rint.s, 0x0, 0x43fa4687, 0x43fa8000
r6ck_2s rint.s, 0x0, 0x41380000, 0x41400000
r6ck_2s rint.s, 0x0, 0x3ff33333, 0x40000000
writemsg "[29] Test rint.d"
r6ck_2d rint.d, 0x0, 0x3ff1f9a6b50b0f28, 0x3ff0000000000000
r6ck_2d rint.d, 0x0, 0xbf543bf727136a40, 0x0
r6ck_2d rint.d, 0x0, 0x407f48d0e5604189, 0x407f500000000000
r6ck_2d rint.d, 0x0, 0x5b7c2d43b93b0a8c, 0x5b7c2d43b93b0a8c,
writemsg "[30] Test class.s"
r6ck_2s class.s, 0x0, 0x7f800010, 0x1
r6ck_2s class.s, 0x0, 0x7fc00000, 0x2
r6ck_2s class.s, 0x0, 0xff800000, 0x4
r6ck_2s class.s, 0x0, 0xbf800000, 0x8
r6ck_2s class.s, 0x0, 0x80000001, 0x10
r6ck_2s class.s, 0x0, 0x80000000, 0x20
r6ck_2s class.s, 0x0, 0x7f800000, 0x40
r6ck_2s class.s, 0x0, 0x3f800000, 0x80
r6ck_2s class.s, 0x0, 0x00000001, 0x100
r6ck_2s class.s, 0x0, 0x00000000, 0x200
writemsg "[31] Test class.d"
r6ck_2d class.d, 0x0, 0x7ff0000000000010, 0x1
r6ck_2d class.d, 0x0, 0x7ff8000000000000, 0x2
r6ck_2d class.d, 0x0, 0xfff0000000000000, 0x4
r6ck_2d class.d, 0x0, 0xbff0000000000000, 0x8
r6ck_2d class.d, 0x0, 0x8000000000000001, 0x10
r6ck_2d class.d, 0x0, 0x8000000000000000, 0x20
r6ck_2d class.d, 0x0, 0x7ff0000000000000, 0x40
r6ck_2d class.d, 0x0, 0x3ff0000000000000, 0x80
r6ck_2d class.d, 0x0, 0x0000000000000001, 0x100
r6ck_2d class.d, 0x0, 0x0000000000000000, 0x200
writemsg "[32] Test min.s"
r6ck_3s min.s, 0x0, 0x3f800000, 0x0, 0x0
r6ck_3s min.s, 0x0, 0x0, 0x3f800000, 0x0
r6ck_3s min.s, 0x0, 0x7f800000, 0x3f800000, 0x3f800000
r6ck_3s min.s, 0x0, 0x3f800000, 0x7f800000, 0x3f800000
r6ck_3s min.s, 0x0, 0xff800000, 0xbf800000, 0xff800000
r6ck_3s min.s, 0x0, 0xbf800000, 0xff800000, 0xff800000
r6ck_3s min.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
r6ck_3s min.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
writemsg "[33] Test min.d"
r6ck_3d min.d, 0x0, 0x3ff0000000000000, 0x0, 0x0
r6ck_3d min.d, 0x0, 0x0, 0x3ff0000000000000, 0x0
r6ck_3d min.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d min.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x3ff0000000000000
r6ck_3d min.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfff0000000000000
r6ck_3d min.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xfff0000000000000
r6ck_3d min.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d min.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
writemsg "[34] Test max.s"
r6ck_3s max.s, 0x0, 0x3f800000, 0x0, 0x3f800000
r6ck_3s max.s, 0x0, 0x0, 0x3f800000, 0x3f800000
r6ck_3s max.s, 0x0, 0x7f800000, 0x3f800000, 0x7f800000
r6ck_3s max.s, 0x0, 0x3f800000, 0x7f800000, 0x7f800000
r6ck_3s max.s, 0x0, 0xff800000, 0xbf800000, 0xbf800000
r6ck_3s max.s, 0x0, 0xbf800000, 0xff800000, 0xbf800000
r6ck_3s max.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
r6ck_3s max.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
writemsg "[35] Test max.d"
r6ck_3d max.d, 0x0, 0x3ff0000000000000, 0x0, 0x3ff0000000000000
r6ck_3d max.d, 0x0, 0x0, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d max.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x7ff0000000000000
r6ck_3d max.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000
r6ck_3d max.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xbff0000000000000
r6ck_3d max.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xbff0000000000000
r6ck_3d max.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d max.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
writemsg "[36] Test mina.s"
r6ck_3s mina.s, 0x0, 0x3f800000, 0x0, 0x0
r6ck_3s mina.s, 0x0, 0x0, 0x3f800000, 0x0
r6ck_3s mina.s, 0x0, 0x7f800000, 0x3f800000, 0x3f800000
r6ck_3s mina.s, 0x0, 0x3f800000, 0x7f800000, 0x3f800000
r6ck_3s mina.s, 0x0, 0xff800000, 0xbf800000, 0xbf800000
r6ck_3s mina.s, 0x0, 0xbf800000, 0xff800000, 0xbf800000
r6ck_3s mina.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
r6ck_3s mina.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
r6ck_3s mina.s, 0x0, 0xc0000000, 0x3f800000, 0x3f800000
r6ck_3s mina.s, 0x0, 0x3f800000, 0xc0000000, 0x3f800000
writemsg "[37] Test mina.d"
r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0x0, 0x0
r6ck_3d mina.d, 0x0, 0x0, 0x3ff0000000000000, 0x0
r6ck_3d mina.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x3ff0000000000000
r6ck_3d mina.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xbff0000000000000
r6ck_3d mina.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xbff0000000000000
r6ck_3d mina.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
r6ck_3d mina.d, 0x0, 0xc000000000000000, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d mina.d, 0x0, 0x3ff0000000000000, 0xc000000000000000, 0x3ff0000000000000
writemsg "[38] Test maxa.s"
r6ck_3s maxa.s, 0x0, 0x3f800000, 0x0, 0x3f800000
r6ck_3s maxa.s, 0x0, 0x0, 0x3f800000, 0x3f800000
r6ck_3s maxa.s, 0x0, 0x7f800000, 0x3f800000, 0x7f800000
r6ck_3s maxa.s, 0x0, 0x3f800000, 0x7f800000, 0x7f800000
r6ck_3s maxa.s, 0x0, 0xff800000, 0xbf800000, 0xff800000
r6ck_3s maxa.s, 0x0, 0xbf800000, 0xff800000, 0xff800000
r6ck_3s maxa.s, 0x0, 0x7fffffff, 0x3f800000, 0x3f800000
r6ck_3s maxa.s, 0x0, 0x3f800000, 0x7fffffff, 0x3f800000
r6ck_3s maxa.s, 0x0, 0xc0000000, 0x3f800000, 0xc0000000
r6ck_3s maxa.s, 0x0, 0x3f800000, 0xc0000000, 0xc0000000
writemsg "[39] Test maxa.d"
r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0x0, 0x3ff0000000000000
r6ck_3d maxa.d, 0x0, 0x0, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d maxa.d, 0x0, 0x7ff0000000000000, 0x3ff0000000000000, 0x7ff0000000000000
r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000
r6ck_3d maxa.d, 0x0, 0xfff0000000000000, 0xbff0000000000000, 0xfff0000000000000
r6ck_3d maxa.d, 0x0, 0xbff0000000000000, 0xfff0000000000000, 0xfff0000000000000
r6ck_3d maxa.d, 0x0, 0x7fffffffffffffff, 0x3ff0000000000000, 0x3ff0000000000000
r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0x7fffffffffffffff, 0x3ff0000000000000
r6ck_3d maxa.d, 0x0, 0xc000000000000000, 0x3ff0000000000000, 0xc000000000000000
r6ck_3d maxa.d, 0x0, 0x3ff0000000000000, 0xc000000000000000, 0xc000000000000000
writemsg "[40] Test sel.s"
r6ck_3s sel.s, 0x0, 0xabcdef12, 0x12345678, 0xabcdef12
r6ck_3s sel.s, 0x1, 0xdeadbeef, 0xcafe1234, 0xcafe1234
r6ck_3s sel.s, 0xfffffffe, 0xbadcafe0, 0x12345678, 0xbadcafe0
r6ck_3s sel.s, 0xffffffff, 0xdeadbeef, 0xcadf00ab, 0xcadf00ab
writemsg "[41] Test sel.d"
r6ck_3d sel.d, 0x0, 0xabcdef123456789, 0x12345678abcdefa, 0xabcdef123456789
r6ck_3d sel.d, 0x1, 0xdeadbeef1534567, 0xcafe12340145279, 0xcafe12340145279
r6ck_3d sel.d, 0xfffffffffffffffe, 0xbadcafe00efacdab, 0x1234567887654321, 0xbadcafe00efacdab
r6ck_3d sel.d, 0xffffffffffffffff, 0xdeadbeeffeebdaed, 0xcadf00abba00fdac, 0xcadf00abba00fdac
writemsg "[42] Test seleqz.s"
r6ck_3s seleqz.s, 0x0, 0x1234abcd, 0x0, 0x1234abcd
r6ck_3s seleqz.s, 0x0, 0xabcdef01, 0x1, 0x0
r6ck_3s seleqz.s, 0x0, 0xffeebbcc, 0xfffffffe, 0xffeebbcc
r6ck_3s seleqz.s, 0x0, 0x12345678, 0xffffffff, 0
writemsg "[43] Test seleqz.d"
r6ck_3d seleqz.d, 0x0, 0x1234abcddcba4321, 0x0, 0x1234abcddcba4321
r6ck_3d seleqz.d, 0x0, 0xabcdef0110fedcba, 0x1, 0x0
r6ck_3d seleqz.d, 0x0, 0xffeebbccccbbeeff, 0xfffffffffffffffe, 0xffeebbccccbbeeff
r6ck_3d seleqz.d, 0x0, 0x1234567887654321, 0xffffffffffffffff, 0x0
writemsg "[44] Test selnez.s"
r6ck_3s selnez.s, 0x0, 0x1234abcd, 0x0, 0x0
r6ck_3s selnez.s, 0x0, 0xabcdef01, 0x1, 0xabcdef01
r6ck_3s selnez.s, 0x0, 0xffeebbcc, 0xfffffffe, 0x0
r6ck_3s selnez.s, 0x0, 0x12345678, 0xffffffff, 0x12345678
writemsg "[45] Test selnez.d"
r6ck_3d selnez.d, 0x0, 0x1234abcddcba4321, 0x0, 0x0
r6ck_3d selnez.d, 0x0, 0xabcdef0110fedcba, 0x1, 0xabcdef0110fedcba
r6ck_3d selnez.d, 0x0, 0xffeebbccccbbeeff, 0xfffffffffffffffe, 0x0
r6ck_3d selnez.d, 0x0, 0x1234567887654321, 0xffffffffffffffff, 0x1234567887654321
writemsg "[46] Test bc1eqz"
li $10, 0x01
mtc1 $10, $f2
mtc1 $0, $f4
bc1eqz $f2, L1
nop
bc1eqz $f4, L2
nop
fail
L1:
fail
L2:
writemsg "[47] Test bc1nez"
bc1nez $f4, L3
nop
bc1nez $f2, L4
nop
fail
L3:
fail
L4:
pass
.end DIAG

57
sim/testsuite/mips/r6-llsc-dp.s Normal file
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@ -0,0 +1,57 @@
# mips64 specific r6 tests - paired LL/SC variants
# mach: mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
.data
.align 16
test_data:
.word 0xaaaaaaaa
.word 0xbbbbbbbb
.word 0xcccccccc
.word 0xdddddddd
end_check:
.byte 0
.byte 0
.byte 0
.byte 0x1
.text
setup
.ent DIAG
DIAG:
writemsg "[1] Test LLWP"
llwp $2, $3, test_data
checkpair_dword $2, $3, test_data, end_check
sll $2, $2, 1
srl $3, $3, 1
move $s0, $2
scwp $2, $3, test_data
check32 $2, 1
checkpair_dword $s0, $3, test_data, end_check
writemsg "[2] Test SCWP, done"
writemsg "[3] Test LLDP"
lldp $2, $3, test_data
checkpair_qword $2, $3, test_data, end_check
dsll $2, $2, 1
dsrl $3, $3, 1
move $s0, $2
scdp $2, $3, test_data
check32 $2, 1
checkpair_qword $s0, $3, test_data, end_check
writemsg "[4] Test SCDP, done"
pass
.end DIAG

41
sim/testsuite/mips/r6-llsc-wp.s Normal file
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@ -0,0 +1,41 @@
# mips32 specific r6 tests - paired LL/SC variants
# mach: mips32r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
.data
.align 8
test_data:
.word 0xaaaaaaaa
.word 0xbbbbbbbb
end_check:
.byte 0
.byte 0
.byte 0
.byte 0x1
.text
setup
.ent DIAG
DIAG:
writemsg "[1] Test LLWP"
llwp $2, $3, test_data
checkpair_dword $2, $3, test_data, end_check
sll $2, $2, 1
srl $3, $3, 1
move $s0, $2
scwp $2, $3, test_data
check32 $2, 1
checkpair_dword $s0, $3, test_data, end_check
writemsg "[2] Test SCWP, done"
pass
.end DIAG

68
sim/testsuite/mips/r6-removed.csv Normal file
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@ -0,0 +1,68 @@
BC1F,0x45000000
BEQL,0x50000000
BGEZAL,0x04310000
BGEZALL,0x04130000
BGEZL,0x04030000
BLTZALL,0x04120000
BLTZL,0x04020000
BNEL,0x54000000
C.DEQ.D,0x44000030
CACHE,0xbc000000
CVT.PS.S,0x46000026
CVT.S.PL,0x46c00028
CVT.S.PU,0x46c00020
DCLO,0x70000025
DCLZ,0x70000024
LDL,0x68000000
LDR,0x6c000000
LDXC1,0x4c000001
LL,0xc0000000
LLD,0xd0000000
LUXC1,0x4c000005
LWL,0x88000000
LWLE,0x7c000019
LWR,0x98000000
LWRE,0x7c00001a
LWXC1,0x4c000000
MADD,0x70000000
MADD.D,0x4c000020
MADDU,0x70000001
MOVF,0x00000001
MOVF.D,0x44000011
MOVN.D,0x44000013
MOVT,0x00010001
MOVT.D,0x44010011
MOVZ.D,0x44000012
MSUB,0x70000004
MSUB.D,0x4c000028
MSUBU,0x70000005
MUL,0x70000002
NEG.S,0x44000007
NMADD.D,0x4c000030
NMSUB.D,0x4c000038
PLL.PS,0x46c0002c
PLU.PS,0x46c0002d
PREF,0xcc000000
PREFX,0x4c00000f
PUL.PS,0x46c0005e
PUU.PS,0x46c0002f
RINT.fmt,0x4400001a
SC,0xe0000000
SCD,0xf0000000
SDBBP,0x7000003f
SDL,0xb0000000
SDR,0xb4000000
SDXC1,0x4c000009
SUB.D,0x44000001
SUXC1,0x4c00000d
SWL,0xa8000000
SWLE,0x7c000021
SWR,0xb8000000
SWRE,0x7c000022
SWXC1,0x4c000008
TEQI,0x040c0000
TGEI,0x04080000
TGEIU,0x04090000
TLTI,0x040a0000
TLTIU,0x040b0000
TNEI,0x040c0000
1 BC1F 0x45000000
2 BEQL 0x50000000
3 BGEZAL 0x04310000
4 BGEZALL 0x04130000
5 BGEZL 0x04030000
6 BLTZALL 0x04120000
7 BLTZL 0x04020000
8 BNEL 0x54000000
9 C.DEQ.D 0x44000030
10 CACHE 0xbc000000
11 CVT.PS.S 0x46000026
12 CVT.S.PL 0x46c00028
13 CVT.S.PU 0x46c00020
14 DCLO 0x70000025
15 DCLZ 0x70000024
16 LDL 0x68000000
17 LDR 0x6c000000
18 LDXC1 0x4c000001
19 LL 0xc0000000
20 LLD 0xd0000000
21 LUXC1 0x4c000005
22 LWL 0x88000000
23 LWLE 0x7c000019
24 LWR 0x98000000
25 LWRE 0x7c00001a
26 LWXC1 0x4c000000
27 MADD 0x70000000
28 MADD.D 0x4c000020
29 MADDU 0x70000001
30 MOVF 0x00000001
31 MOVF.D 0x44000011
32 MOVN.D 0x44000013
33 MOVT 0x00010001
34 MOVT.D 0x44010011
35 MOVZ.D 0x44000012
36 MSUB 0x70000004
37 MSUB.D 0x4c000028
38 MSUBU 0x70000005
39 MUL 0x70000002
40 NEG.S 0x44000007
41 NMADD.D 0x4c000030
42 NMSUB.D 0x4c000038
43 PLL.PS 0x46c0002c
44 PLU.PS 0x46c0002d
45 PREF 0xcc000000
46 PREFX 0x4c00000f
47 PUL.PS 0x46c0005e
48 PUU.PS 0x46c0002f
49 RINT.fmt 0x4400001a
50 SC 0xe0000000
51 SCD 0xf0000000
52 SDBBP 0x7000003f
53 SDL 0xb0000000
54 SDR 0xb4000000
55 SDXC1 0x4c000009
56 SUB.D 0x44000001
57 SUXC1 0x4c00000d
58 SWL 0xa8000000
59 SWLE 0x7c000021
60 SWR 0xb8000000
61 SWRE 0x7c000022
62 SWXC1 0x4c000008
63 TEQI 0x040c0000
64 TGEI 0x04080000
65 TGEIU 0x04090000
66 TLTI 0x040a0000
67 TLTIU 0x040b0000
68 TNEI 0x040c0000

18
sim/testsuite/mips/r6-removed.s Normal file
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@ -0,0 +1,18 @@
# Tests the instructions removed in R6 are correctly invalidated
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: ReservedInstruction at PC = *\nprogram stopped with signal 4 (Illegal instruction).\n
# xerror:
.include "testutils.inc"
.include "r6-removed.inc"
setup
.set noreorder
.ent DIAG
DIAG:
removed_instr
fail
.end DIAG

163
sim/testsuite/mips/r6.s Normal file
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@ -0,0 +1,163 @@
# mips r6 tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.data
dval1: .word 0xabcd1234
dval2: .word 0x1234eeff
.fill 248,1,0
dval3: .word 0x55555555
.fill 260,1,0
dval4: .word 0xaaaaaaaa
.text
.set noreorder
.ent DIAG
DIAG:
writemsg "[1] Test MUL"
r6ck_2r mul, 7, 9, 63
r6ck_2r mul, -7, -9, 63
r6ck_2r mul, 61, -11, -671
r6ck_2r mul, 1001, 1234, 1235234
r6ck_2r mul, 123456789, 999999, 0x7eb1e22b
r6ck_2r mul, 0xaaaabbbb, 0xccccdddd, 0x56787f6f
writemsg "[2] Test MUH"
r6ck_2r muh, 61, -11, 0xffffffff
r6ck_2r muh, 1001, 1234, 0
r6ck_2r muh, 123456789, 999999, 0x7048
r6ck_2r muh, 0xaaaabbbb, 0xccccdddd, 0x111107f7
writemsg "[3] Test MULU"
r6ck_2r mulu, 7, 9, 63
r6ck_2r mulu, -7, -9, 63
r6ck_2r mulu, 61, -11, -671
r6ck_2r mulu, 1001, 1234, 1235234
r6ck_2r mulu, 123456789, 999999, 0x7eb1e22b
r6ck_2r mulu, 0xaaaabbbb, 0xccccdddd, 0x56787f6f
writemsg "[4] Test MUHU"
r6ck_2r muhu, 1001, 1234, 0
r6ck_2r muhu, 123456789, 999999, 0x7048
r6ck_2r muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f
r6ck_2r muhu, 0xaaaabbbb, 0xccccdddd, 0x8888a18f
writemsg "[5] Test DIV"
r6ck_2r div, 10001, 10, 1000
r6ck_2r div, -123456, 560, -220
r6ck_2r div, 9, 100, 0
writemsg "[6] Test MOD"
r6ck_2r mod, 10001, 10, 1
r6ck_2r mod, -123456, 560, 0xffffff00
r6ck_2r mod, 9, 100, 9
writemsg "[7] Test DIVU"
r6ck_2r divu, 10001, 10, 1000
r6ck_2r divu, -123456, 560, 0x750674
r6ck_2r divu, 9, 100, 0
r6ck_2r divu, 0xaaaabbbb, 3, 0x38e393e9
writemsg "[8] Test MODU"
r6ck_2r modu, 10001, 10, 1
r6ck_2r modu, -123456, 560, 0
r6ck_2r modu, 9, 100, 9
r6ck_2r modu, 0xaaaabbbb, 5, 4
writemsg "[9] Test LSA"
r6ck_2r1i lsa, 1, 2, 2, 6
r6ck_2r1i lsa, 0x8000, 0xa000, 1, 0x1a000
r6ck_2r1i lsa, 0x82, 0x2000068, 4, 0x2000888
writemsg "[10] Test AUI"
r6ck_1r1i aui, 0x0000c0de, 0xdead, 0xdeadc0de
r6ck_1r1i aui, 0x00005678, 0x1234, 0x12345678
r6ck_1r1i aui, 0x0000eeff, 0xabab, 0xababeeff
writemsg "[11] Test SELEQZ"
r6ck_2r seleqz, 0x1234, 0, 0x1234
r6ck_2r seleqz, 0x1234, 4, 0
r6ck_2r seleqz, 0x80010001, 0, 0x80010001
writemsg "[12] Test SELNEZ"
r6ck_2r selnez, 0x1234, 0, 0
r6ck_2r selnez, 0x1234, 1, 0x1234
r6ck_2r selnez, 0x80010001, 0xffffffff, 0x80010001
writemsg "[13] Test ALIGN"
r6ck_2r1i align, 0xaabbccdd, 0xeeff0011, 1, 0xff0011aa
r6ck_2r1i align, 0xaabbccdd, 0xeeff0011, 3, 0x11aabbcc
writemsg "[14] Test BITSWAP"
r6ck_1r bitswap, 0xaabbccdd, 0x55dd33bb
r6ck_1r bitswap, 0x11884422, 0x88112244
writemsg "[15] Test CLZ"
r6ck_1r clz, 0x00012340, 15
r6ck_1r clz, 0x80012340, 0
r6ck_1r clz, 0x40012340, 1
writemsg "[16] Test CLO"
r6ck_1r clo, 0x00123050, 0
r6ck_1r clo, 0xff123050, 8
r6ck_1r clo, 0x8f123050, 1
writemsg "[17] Test ADDIUPC"
jal GetPC
nop
addiu $4, $6, 8
addiupc $5, 4
fp_assert $4, $5
writemsg "[18] Test AUIPC"
jal GetPC
nop
addiu $4, $6, 8
aui $4, $4, 8
auipc $5, 8
fp_assert $4, $5
writemsg "[19] Test ALUIPC"
jal GetPC
nop
addiu $4, $6, 16
aui $4, $4, 8
li $7, 0xffff0000
and $4, $4, $7
aluipc $5, 8
fp_assert $4, $5
writemsg "[20] Test LWPC"
lw $5, dval1
lwpc $4, dval1
fp_assert $4, $5
lw $5, dval2
lwpc $4, dval2
fp_assert $4, $5
writemsg "[21] Test LL"
lw $5, dval2
la $3, dval3
ll $4, -252($3)
fp_assert $4, $5
writemsg "[22] Test SC"
ll $4, -252($3)
li $4, 0xafaf
sc $4, -252($3)
lw $5, dval2
li $4, 0xafaf
fp_assert $4, $5
pass
.end DIAG

55
sim/testsuite/mips/testutils.inc
View File

@ -148,3 +148,58 @@ _dowrite:
checkreg \reg, $1
.set pop
.endm
# Check hi-lo register pair against data stored at base+o1 and base+o2
# Clobbers $1 - $5
.macro checkpair lo, hi, base, w, o1, o2
move $2, \lo
move $3, \hi
.set noat
la $1, \base
l\w $4, \o1($1)
l\w $5, \o2($1)
.set at
checkreg $2, $4
checkreg $3, $5
.endm
.macro checkpair_le_d lo, hi, base
checkpair \lo, \hi, \base, w, 0, 4
.endm
.macro checkpair_be_d lo, hi, base
checkpair \lo, \hi, \base, w, 4, 0
.endm
.macro checkpair_le_q lo, hi, base
checkpair \lo, \hi, \base, d, 0, 8
.endm
.macro checkpair_be_q lo, hi, base
checkpair \lo, \hi, \base, d, 8, 0
.endm
# Endian-ness for comparison is determined by reading a word at ec
.macro checkpair_xendian lo, hi, base, ec, w
.set noat
lw $1, \ec
andi $1, $1, 0x1
# check endianess
beqz $1, 2f
.set at
1: # big endian
checkpair_be_\w \lo, \hi, \base
b 3f
2: # little endian
checkpair_le_\w \lo, \hi, \base
3:
.endm
.macro checkpair_qword lo, hi, base, oe
checkpair_xendian \lo, \hi, \base, \oe, q
.endm
.macro checkpair_dword lo, hi, base, oe
checkpair_xendian \lo, \hi, \base, \oe, d
.endm

150
sim/testsuite/mips/utils-r6.inc Normal file
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.macro fp_assert a, b
beq \a, \b, 1f
nop
j _fail
nop
1:
.endm
.macro r6ck_1r inst, a, ret
li $4, \a
li $6, \ret
\inst $7, $4
fp_assert $6, $7
.endm
.macro r6ck_1dr inst, a, ret
ld $4, \a
ld $6, \ret
\inst $7, $4
fp_assert $6, $7
.endm
.macro r6ck_2r inst, a, b, ret
li $4, \a
li $5, \b
li $6, \ret
\inst $7, $4, $5
fp_assert $6, $7
.endm
.macro r6ck_2dr inst, a, b, ret
ld $4, \a
ld $5, \b
ld $6, \ret
\inst $7, $4, $5
fp_assert $6, $7
.endm
.macro r6ck_2dr1i inst, a, b, imm, ret
ld $4, \a
ld $5, \b
ld $6, \ret
\inst $7, $4, $5, \imm
fp_assert $6, $7
.endm
.macro r6ck_1r1i inst, a, imm, ret
li $4, \a
li $6, \ret
\inst $7, $4, \imm
fp_assert $6, $7
.endm
.macro r6ck_1dr1i inst, a, imm, ret
ld $4, \a
ld $6, \ret
\inst $7, $4, \imm
fp_assert $6, $7
.endm
.macro r6ck_0dr1i inst, a, imm, ret
ld $4, \a
ld $6, \ret
\inst $4, $4, \imm
fp_assert $6, $4
.endm
.macro r6ck_2r1i inst, a, b, imm, ret
li $4, \a
li $5, \b
li $6, \ret
\inst $7, $4, $5, \imm
fp_assert $6, $7
.endm
.macro r6ck_3s inst, a, b, c, ret
li $4, \a
li $5, \b
li $6, \c
li $7, \ret
mtc1 $4, $f2
mtc1 $5, $f4
mtc1 $6, $f6
\inst $f2, $f4, $f6
mfc1 $8, $f2
fp_assert $7, $8
.endm
.macro r6ck_2s inst, a, b, ret
li $4, \a
li $5, \b
li $6, \ret
mtc1 $4, $f2
mtc1 $5, $f4
\inst $f2, $f4
mfc1 $7, $f2
fp_assert $6, $7
.endm
.macro r6ck_2d inst, a, b, ret
.data
1: .dword \a
2: .dword \b
3: .dword \ret
.text
la $4, 1b
la $5, 2b
la $6, 3b
ldc1 $f2, 0($4)
ldc1 $f4, 0($5)
lw $7, 0($6)
lw $8, 4($6)
\inst $f2, $f4
#simulate dmfc1
mfhc1 $9, $f2
mfc1 $10, $f2
fp_assert $7, $9
fp_assert $8, $10
.endm
.macro r6ck_3d inst, a, b, c, ret
.data
1: .dword \a
2: .dword \b
3: .dword \c
4: .dword \ret
.text
la $4, 1b
la $5, 2b
la $6, 3b
la $2, 4b
ldc1 $f2, 0($4)
ldc1 $f4, 0($5)
ldc1 $f6, 0($6)
lw $7, 0($2)
lw $8, 4($2)
\inst $f2, $f4, $f6
#simulate dmfc1
mfhc1 $9, $f2
mfc1 $10, $f2
fp_assert $7, $9
fp_assert $8, $10
.endm
.text
GetPC:
move $6, $ra
jr $ra