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* p{1,3}.c (sim_resume): when running on dos, any character typed to

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the keyboard will cause a simulated exception.
This commit is contained in:
Steve Chamberlain 1993-01-04 20:55:22 +00:00
parent ce1a2ef4ca
commit 06137fcb39
4 changed files with 41 additions and 49 deletions
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5
sim/h8300/ChangeLog
View File

@ -1,3 +1,8 @@
Mon Jan 4 12:32:35 1993 Steve Chamberlain (sac@wahini.cygnus.com)
* p1.c (sim_resume): when running on dos, any character typed to
the keyboard will cause a simulated exception.
Sun Jan 3 14:15:07 1993 Steve Chamberlain (sac@thepub.cygnus.com)
* p1.c, p3.c, run.c, writecode.c: all used h8/300 opcodes in and

19
sim/h8300/Makefile.in
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@ -57,8 +57,9 @@ INCDIR = $(srcdir)/../include
CSEARCH = -I. -I$(srcdir) -I$(INCDIR) -I$(srcdir)/../bfd
DEP = mkdep
#### host, target, and site specific Makefile frags come in here.
TARGETLIB = libsim.a
all: run
run: code.o run.o
$(CC) -o run code.o run.o ../bfd/libbfd.a ../libiberty/libiberty.a
@ -72,7 +73,7 @@ p2.c:writecode
writecode:writecode.c
$(CC_FOR_BUILD) -o writecode -g $(CSEARCH) -c $(srcdir)/writecode.c
$(CC_FOR_BUILD) -o writecode -g $(CSEARCH) $(srcdir)/writecode.c
@ -98,13 +99,6 @@ FLAGS_TO_PASS = \
$(CC) -c $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHES) $<
# C source files that correspond to .o's.
CFILES = z8k-dis.c
STAGESTUFF = $(TARGETLIB) $(OFILES)
all: $(TARGETLIB)
.NOEXPORT:
@ -117,13 +111,6 @@ install-info:
# HDEPFILES comes from the host config; TDEPFILES from the target config.
$(TARGETLIB): $(OFILES)
rm -f $(TARGETLIB)
$(AR) $(AR_FLAGS) $(TARGETLIB) $(OFILES)
$(RANLIB) $(TARGETLIB)
# Circumvent Sun Make bug with VPATH.
sparc-opc.o: sparc-opc.c
tags etags: TAGS

57
sim/h8300/p1.c
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@ -58,32 +58,6 @@ int exception;
static unsigned char *mem;
void
control_c (sig, code, scp, addr)
int sig;
int code;
char *scp;
char *addr;
{
exception = SIGINT;
}
void
sim_store_register (reg, val)
int reg;
int val;
{
saved_state.reg[reg] = val;
}
void
sim_fetch_register (reg, buf)
int reg;
char *buf;
{
buf[0] = saved_state.reg[reg] >> 8;
buf[1] = saved_state.reg[reg];
}
static union
{
@ -108,7 +82,6 @@ meminit ()
mem = calloc (1024, 64);
littleendian.i = 1;
/* initialze the array of pointers to byte registers */
for (tmp = 0; tmp < 8; tmp++)
{
@ -143,6 +116,35 @@ meminit ()
}
}
void
control_c (sig, code, scp, addr)
int sig;
int code;
char *scp;
char *addr;
{
exception = SIGINT;
}
void
sim_store_register (reg, val)
int reg;
int val;
{
saved_state.reg[reg] = val;
}
void
sim_fetch_register (reg, buf)
int reg;
char *buf;
{
meminit();
buf[0] = saved_state.reg[reg] >> 8;
buf[1] = saved_state.reg[reg];
}
void
sim_write (to, from, len)
int to;
@ -221,7 +223,6 @@ int sig;
}
do
{
dst = 0xfeedface;
b0 = pc[0];
b1 = pc[1];

9
sim/h8300/p3.c
View File

@ -1,24 +1,20 @@
movflags8:
if (dst == 0xfeedface) abort();
n = dst & 0x80;
z = !(dst & 0xff);
v = 0;
goto next;
movflags16:
if (dst == 0xfeedface) abort();
n = dst & 0x8000;
z = !(dst & 0xffff);
v = 0;
goto next;
aluflags8:
if (dst == 0xfeedface) abort();
n = dst & 0x80;
z = !(dst & 0xff);
v = ((srca & 0x80) == (srcb & 0x80)) && ((srca & 0x80) != (dst & 0x80));
c = dst & 0x100;
goto next;
aluflags16:
if (dst == 0xfeedface) abort();
n = dst & 0x8000;
z = !(dst & 0xffff);
v = ((srca & 0x8000) == (srcb & 0x8000)) && ((srca & 0x8000) != (dst & 0x8000));
@ -31,12 +27,15 @@ break;
shiftflags:
v = 0;
incflags:
if (dst == 0xfeedface) abort();
z = !(dst & 0xff);
n = dst & 0x80;
goto next;
next: ;
pc = npc;
#ifdef __GO32__
if (kbhit())
exception = SIGINT;
#endif
} while (!exception);
saved_state.cycles = cycles;