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bpf: Update atomic instruction pseudo-C syntax
This patch updates the pseudo-C dialect templates for the BPF v3 atomic instructions. The templates match the strings emitted by clang -S for these instructions. The tests and documentation are updated accordingly. gas/ * doc/c-bpf.texi (BPF Instructions): Update entries for atomic and 32-bit atomic instructions. * testsuite/gas/bpf/atomic.s: Test AAND, AAND32, AOR, AOR32, AXOR, AXOR32, AFADD, AFADD32, AFAND, AFAND32, AFOR, AFOR32, AFXOR and AFXOR32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-v1.s: New test. * testsuite/gas/bpf/atomic-v1.d: Likewise. * testuiste/gas/bpf/atomic-v1-be.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-opc.c (bpf_opcodes): Update pseudo-C dialect templates for: BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR, BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR, BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32, BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, and BPF_INSN_AFXOR32 instructions.
This commit is contained in:
David Faust
parent
695776dc2f
commit
055a4c8e0f
@ -750,43 +750,41 @@ for swapping 64-bit quantities and another for 32-bit quantities.
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@table @code
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@item aadd [rd + offset16], rs
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@itemx *(u64 *)(rd + offset16) = rs
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@itemx lock *(u64 *)(rd + offset16) = rs
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Atomic add instruction.
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@item aor [rd + offset16], rs
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@itemx *(u64 *) (rd + offset16) |= rs
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@itemx lock *(u64 *) (rd + offset16) |= rs
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Atomic or instruction.
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@item aand [rd + offset16], rs
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@itemx *(u64 *) (rd + offset16) &= rs
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@itemx lock *(u64 *) (rd + offset16) &= rs
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Atomic and instruction.
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@item axor [rd + offset16], rs
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@itemx *(u64 *) (rd + offset16) ^= rs
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Atomic xor instruction
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@item xaddw [%d+offset16],%s
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Exchange-and-add a 32-bit value at the specified location.
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@itemx lock *(u64 *) (rd + offset16) ^= rs
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Atomic xor instruction.
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@end table
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@noindent
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The following variants perform fetching before the atomic operation.
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@table @code
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@item afadd [dr + offset16], rs
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@itemx ???
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@item afadd [rd + offset16], rs
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@itemx rs = atomic_fetch_add ((u64 *)(rd + offset16), rs)
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Atomic fetch-and-add instruction.
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@item afor [dr + offset16], rs
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@itemx ???
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@item afor [rd + offset16], rs
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@itemx rs = atomic_fetch_or ((u64 *)(rd + offset16), rs)
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Atomic fetch-and-or instruction.
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@item afand [dr + offset16], rs
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@itemx ???
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@item afand [rd + offset16], rs
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@itemx rs = atomic_fetch_and ((u64 *)(rd + offset16), rs)
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Atomic fetch-and-and instruction.
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@item afxor [dr + offset16], rs
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@itemx ???
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Atomic fetch-and-or instruction
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@item afxor [rd + offset16], rs
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@itemx rs = atomic_fetch_xor ((u64 *)(rd + offset16), rs)
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Atomic fetch-and-or instruction.
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@end table
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The above instructions were introduced in the V3 of the BPF
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@ -805,19 +803,19 @@ for swapping 32-bit quantities and another for 32-bit quantities.
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@table @code
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@item aadd32 [rd + offset16], rs
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@itemx *(u32 *)(rd + offset16) = rs
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@itemx lock *(u32 *)(rd + offset16) = rs
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Atomic add instruction.
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@item aor32 [rd + offset16], rs
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@itemx *(u32 *) (rd + offset16) |= rs
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@itemx lock *(u32 *) (rd + offset16) |= rs
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Atomic or instruction.
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@item aand32 [rd + offset16], rs
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@itemx *(u32 *) (rd + offset16) &= rs
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@itemx lock *(u32 *) (rd + offset16) &= rs
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Atomic and instruction.
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@item axor32 [rd + offset16], rs
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@itemx *(u32 *) (rd + offset16) ^= rs
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@itemx lock *(u32 *) (rd + offset16) ^= rs
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Atomic xor instruction
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@end table
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@ -826,19 +824,19 @@ The following variants perform fetching before the atomic operation.
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@table @code
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@item afadd32 [dr + offset16], rs
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@itemx ???
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@itemx ws = atomic_fetch_add ((u32 *)(rd + offset16), ws)
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Atomic fetch-and-add instruction.
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@item afor32 [dr + offset16], rs
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@itemx ???
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@itemx ws = atomic_fetch_or ((u32 *)(rd + offset16), ws)
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Atomic fetch-and-or instruction.
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@item afand32 [dr + offset16], rs
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@itemx ???
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@itemx ws = atomic_fetch_and ((u32 *)(rd + offset16), ws)
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Atomic fetch-and-and instruction.
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@item afxor32 [dr + offset16], rs
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@itemx ???
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@itemx ws = atomic_fetch_xor ((u32 *)(rd + offset16), ws)
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Atomic fetch-and-or instruction
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@end table
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@ -8,5 +8,21 @@
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Disassembly of section .text:
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0+ <.text>:
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0: db 12 1e ef 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2
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8: c3 12 1e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2
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0: db 12 1e ef 00 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
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8: c3 12 1e ef 00 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
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10: db 12 1e ef 00 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
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18: c3 12 1e ef 00 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
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20: db 12 1e ef 00 00 00 50 lock \*\(u64\*\)\(r1\+0x1eef\)\&=r2
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28: c3 12 1e ef 00 00 00 50 lock \*\(u32\*\)\(r1\+0x1eef\)\&=r2
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30: db 12 1e ef 00 00 00 40 lock \*\(u64\*\)\(r1\+0x1eef\)\|=r2
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38: c3 12 1e ef 00 00 00 40 lock \*\(u32\*\)\(r1\+0x1eef\)\|=r2
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40: db 12 1e ef 00 00 00 a0 lock \*\(u64\*\)\(r1\+0x1eef\)\^=r2
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48: c3 12 1e ef 00 00 00 a0 lock \*\(u32\*\)\(r1\+0x1eef\)\^=r2
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50: db 12 1e ef 00 00 00 01 r2=atomic_fetch_add\(\(u64\*\)\(r1\+0x1eef\),r2\)
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58: c3 12 1e ef 00 00 00 01 w2=atomic_fetch_add\(\(u32\*\)\(r1\+0x1eef\),w2\)
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60: db 12 1e ef 00 00 00 51 r2=atomic_fetch_and\(\(u64\*\)\(r1\+0x1eef\),r2\)
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68: c3 12 1e ef 00 00 00 51 w2=atomic_fetch_and\(\(u32\*\)\(r1\+0x1eef\),w2\)
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70: db 12 1e ef 00 00 00 41 r2=atomic_fetch_or\(\(u64\*\)\(r1\+0x1eef\),r2\)
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78: c3 12 1e ef 00 00 00 41 w2=atomic_fetch_or\(\(u32\*\)\(r1\+0x1eef\),w2\)
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80: db 12 1e ef 00 00 00 a1 r2=atomic_fetch_xor\(\(u64\*\)\(r1\+0x1eef\),r2\)
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88: c3 12 1e ef 00 00 00 a1 w2=atomic_fetch_xor\(\(u32\*\)\(r1\+0x1eef\),w2\)
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@ -1,6 +1,6 @@
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#as: -EB -mdialect=normal
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#source: atomic.s
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#objdump: -dr -M hex,v1
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#objdump: -dr -M hex
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#name: eBPF atomic instructions, big endian
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.*: +file format .*bpf.*
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@ -8,5 +8,19 @@
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Disassembly of section .text:
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0+ <.text>:
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0: db 12 1e ef 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
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8: c3 12 1e ef 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
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0: db 12 1e ef 00 00 00 00 aadd \[%r1\+0x1eef\],%r2
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8: c3 12 1e ef 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2
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10: db 12 1e ef 00 00 00 50 aand \[%r1\+0x1eef\],%r2
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18: c3 12 1e ef 00 00 00 50 aand32 \[%r1\+0x1eef\],%r2
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20: db 12 1e ef 00 00 00 40 aor \[%r1\+0x1eef\],%r2
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28: c3 12 1e ef 00 00 00 40 aor32 \[%r1\+0x1eef\],%r2
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30: db 12 1e ef 00 00 00 a0 axor \[%r1\+0x1eef\],%r2
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38: c3 12 1e ef 00 00 00 a0 axor32 \[%r1\+0x1eef\],%r2
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40: db 12 1e ef 00 00 00 01 afadd \[%r1\+0x1eef\],%r2
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48: c3 12 1e ef 00 00 00 01 afadd32 \[%r1\+0x1eef\],%r2
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50: db 12 1e ef 00 00 00 51 afand \[%r1\+0x1eef\],%r2
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58: c3 12 1e ef 00 00 00 51 afand32 \[%r1\+0x1eef\],%r2
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60: db 12 1e ef 00 00 00 41 afor \[%r1\+0x1eef\],%r2
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68: c3 12 1e ef 00 00 00 41 afor32 \[%r1\+0x1eef\],%r2
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70: db 12 1e ef 00 00 00 a1 afxor \[%r1\+0x1eef\],%r2
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78: c3 12 1e ef 00 00 00 a1 afxor32 \[%r1\+0x1eef\],%r2
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@ -8,5 +8,21 @@
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Disassembly of section .text:
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0+ <.text>:
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0: db 21 ef 1e 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2
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8: c3 21 ef 1e 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2
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0: db 21 ef 1e 00 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
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8: c3 21 ef 1e 00 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
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10: db 21 ef 1e 00 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
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18: c3 21 ef 1e 00 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
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20: db 21 ef 1e 50 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\&=r2
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28: c3 21 ef 1e 50 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\&=r2
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30: db 21 ef 1e 40 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\|=r2
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38: c3 21 ef 1e 40 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\|=r2
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40: db 21 ef 1e a0 00 00 00 lock \*\(u64\*\)\(r1\+0x1eef\)\^=r2
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48: c3 21 ef 1e a0 00 00 00 lock \*\(u32\*\)\(r1\+0x1eef\)\^=r2
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50: db 21 ef 1e 01 00 00 00 r2=atomic_fetch_add\(\(u64\*\)\(r1\+0x1eef\),r2\)
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58: c3 21 ef 1e 01 00 00 00 w2=atomic_fetch_add\(\(u32\*\)\(r1\+0x1eef\),w2\)
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60: db 21 ef 1e 51 00 00 00 r2=atomic_fetch_and\(\(u64\*\)\(r1\+0x1eef\),r2\)
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68: c3 21 ef 1e 51 00 00 00 w2=atomic_fetch_and\(\(u32\*\)\(r1\+0x1eef\),w2\)
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70: db 21 ef 1e 41 00 00 00 r2=atomic_fetch_or\(\(u64\*\)\(r1\+0x1eef\),r2\)
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78: c3 21 ef 1e 41 00 00 00 w2=atomic_fetch_or\(\(u32\*\)\(r1\+0x1eef\),w2\)
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80: db 21 ef 1e a1 00 00 00 r2=atomic_fetch_xor\(\(u64\*\)\(r1\+0x1eef\),r2\)
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88: c3 21 ef 1e a1 00 00 00 w2=atomic_fetch_xor\(\(u32\*\)\(r1\+0x1eef\),w2\)
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@ -1,4 +1,20 @@
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# Test for eBPF ADDW and ADDDW pseudo-C instructions
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# Test for eBPF atomic pseudo-C instructions.
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.text
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*(u64 *)(r1 + 7919) += r2
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*(u32 *)(r1 + 7919) += r2
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lock *(u64 *)(r1 + 0x1eef) += r2
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lock *(u32 *)(r1 + 0x1eef) += r2
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lock *(u64*)(r1+0x1eef)+=r2
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lock *(u32*)(r1+0x1eef)+=r2
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lock *(u64*)(r1+0x1eef)&=r2
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lock *(u32*)(r1+0x1eef)&=r2
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lock *(u64*)(r1+0x1eef)|=r2
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lock *(u32*)(r1+0x1eef)|=r2
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lock *(u64*)(r1+0x1eef)^=r2
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lock *(u32*)(r1+0x1eef)^=r2
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r2 = atomic_fetch_add((u64*)(r1+0x1eef),r2)
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w2 = atomic_fetch_add((u32*)(r1+0x1eef),w2)
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r2 = atomic_fetch_and((u64*)(r1+0x1eef),r2)
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w2 = atomic_fetch_and((u32*)(r1+0x1eef),w2)
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r2 = atomic_fetch_or((u64*)(r1+0x1eef),r2)
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w2 = atomic_fetch_or((u32*)(r1+0x1eef),w2)
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r2 = atomic_fetch_xor((u64*)(r1+0x1eef),r2)
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w2 = atomic_fetch_xor((u32*)(r1+0x1eef),w2)
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12
gas/testsuite/gas/bpf/atomic-v1-be.d
Normal file
12
gas/testsuite/gas/bpf/atomic-v1-be.d
Normal file
@ -0,0 +1,12 @@
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#as: -EB -mdialect=normal
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#source: atomic-v1.s
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#objdump: -dr -M hex,v1
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#name: eBPF atomic instructions, big endian
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.*: +file format .*bpf.*
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Disassembly of section .text:
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0+ <.text>:
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0: db 12 1e ef 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
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8: c3 12 1e ef 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
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12
gas/testsuite/gas/bpf/atomic-v1.d
Normal file
12
gas/testsuite/gas/bpf/atomic-v1.d
Normal file
@ -0,0 +1,12 @@
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#as: -EL -mdialect=normal
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#source: atomic-v1.s
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#objdump: -dr -M hex,v1
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#name: eBPF atomic instructions, little endian
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.*: +file format .*bpf.*
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Disassembly of section .text:
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0+ <.text>:
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0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
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8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
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5
gas/testsuite/gas/bpf/atomic-v1.s
Normal file
5
gas/testsuite/gas/bpf/atomic-v1.s
Normal file
@ -0,0 +1,5 @@
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# Test for eBPF XADDW and XADDDW instructions.
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.text
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xadddw [%r1+0x1eef], %r2
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xaddw [%r1+0x1eef], %r2
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@ -10,3 +10,17 @@ Disassembly of section .text:
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0+ <.text>:
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0: db 21 ef 1e 00 00 00 00 aadd \[%r1\+0x1eef\],%r2
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8: c3 21 ef 1e 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2
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10: db 21 ef 1e 50 00 00 00 aand \[%r1\+0x1eef\],%r2
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18: c3 21 ef 1e 50 00 00 00 aand32 \[%r1\+0x1eef\],%r2
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20: db 21 ef 1e 40 00 00 00 aor \[%r1\+0x1eef\],%r2
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28: c3 21 ef 1e 40 00 00 00 aor32 \[%r1\+0x1eef\],%r2
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30: db 21 ef 1e a0 00 00 00 axor \[%r1\+0x1eef\],%r2
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38: c3 21 ef 1e a0 00 00 00 axor32 \[%r1\+0x1eef\],%r2
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40: db 21 ef 1e 01 00 00 00 afadd \[%r1\+0x1eef\],%r2
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48: c3 21 ef 1e 01 00 00 00 afadd32 \[%r1\+0x1eef\],%r2
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50: db 21 ef 1e 51 00 00 00 afand \[%r1\+0x1eef\],%r2
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58: c3 21 ef 1e 51 00 00 00 afand32 \[%r1\+0x1eef\],%r2
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60: db 21 ef 1e 41 00 00 00 afor \[%r1\+0x1eef\],%r2
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68: c3 21 ef 1e 41 00 00 00 afor32 \[%r1\+0x1eef\],%r2
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70: db 21 ef 1e a1 00 00 00 afxor \[%r1\+0x1eef\],%r2
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78: c3 21 ef 1e a1 00 00 00 afxor32 \[%r1\+0x1eef\],%r2
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@ -1,5 +1,19 @@
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# Test for eBPF ADDW and ADDDW instructions
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# Test for eBPF atomic instructions
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.text
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aadd [%r1+0x1eef], %r2
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aadd32 [%r1+0x1eef], %r2
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aand [%r1+0x1eef], %r2
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aand32 [%r1+0x1eef], %r2
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aor [%r1+0x1eef], %r2
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aor32 [%r1+0x1eef], %r2
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axor [%r1+0x1eef], %r2
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axor32 [%r1+0x1eef], %r2
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afadd [%r1+0x1eef], %r2
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afadd32 [%r1+0x1eef], %r2
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afand [%r1+0x1eef], %r2
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afand32 [%r1+0x1eef], %r2
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afor [%r1+0x1eef], %r2
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afor32 [%r1+0x1eef], %r2
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afxor [%r1+0x1eef], %r2
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afxor32 [%r1+0x1eef], %r2
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@ -34,6 +34,7 @@ if {[istarget bpf*-*-*]} {
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run_dump_test jump-pseudoc
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run_dump_test jump32
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run_dump_test jump32-pseudoc
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run_dump_test atomic-v1
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run_dump_test atomic
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run_dump_test atomic-pseudoc
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run_dump_test indcall-1
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@ -55,6 +56,7 @@ if {[istarget bpf*-*-*]} {
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run_dump_test jump-be-pseudoc
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run_dump_test jump32-be
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run_dump_test jump32-be-pseudoc
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run_dump_test atomic-v1-be
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run_dump_test atomic-be
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run_dump_test atomic-be-pseudoc
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}
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||||
@ -364,43 +364,43 @@ const struct bpf_opcode bpf_opcodes[] =
|
||||
BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_K},
|
||||
|
||||
/* Atomic instructions. */
|
||||
{BPF_INSN_AADD, "aadd%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
|
||||
{BPF_INSN_AADD, "aadd%W[ %dr %o16 ] , %sr", "lock%w* ( u64 * ) ( %dr %o16 ) += %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
|
||||
{BPF_INSN_AOR, "aor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) |= %sr",
|
||||
{BPF_INSN_AOR, "aor%W[ %dr %o16 ] , %sr", "lock%w* ( u64 * ) ( %dr %o16 ) |= %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
|
||||
{BPF_INSN_AAND, "aand%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) &= %sr",
|
||||
{BPF_INSN_AAND, "aand%W[ %dr %o16 ] , %sr", "lock%w* ( u64 * ) ( %dr %o16 ) &= %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
|
||||
{BPF_INSN_AXOR, "axor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) ^= %sr",
|
||||
{BPF_INSN_AXOR, "axor%W[ %dr %o16 ] , %sr", "lock%w* ( u64 * ) ( %dr %o16 ) ^= %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
|
||||
|
||||
/* Atomic instructions with fetching. */
|
||||
{BPF_INSN_AFADD, "afadd%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFADD, "afadd%W[ %dr %o16 ] , %sr", "%sr = atomic_fetch_add ( ( u64 * ) ( %dr %o16 ) , %sr )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
|
||||
{BPF_INSN_AFOR, "afor%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFOR, "afor%W[ %dr %o16 ] , %sr", "%sr = atomic_fetch_or ( ( u64 * ) ( %dr %o16 ) , %sr )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
|
||||
{BPF_INSN_AFAND, "afand%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFAND, "afand%W[ %dr %o16 ] , %sr", "%sr = atomic_fetch_and ( ( u64 * ) ( %dr %o16 ) , %sr )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
|
||||
{BPF_INSN_AFXOR, "afxor%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFXOR, "afxor%W[ %dr %o16 ] , %sr", "%sr = atomic_fetch_xor ( ( u64 * ) ( %dr %o16 ) , %sr )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
|
||||
|
||||
/* Atomic instructions (32-bit.) */
|
||||
{BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
|
||||
{BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) += %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
|
||||
{BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) |= %sr",
|
||||
{BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) |= %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
|
||||
{BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) &= %sr",
|
||||
{BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) &= %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
|
||||
{BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) ^= %sr",
|
||||
{BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) ^= %sr",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
|
||||
|
||||
/* Atomic instructions with fetching (32-bit.) */
|
||||
{BPF_INSN_AFADD32, "afadd32 %W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFADD32, "afadd32%W[ %dr %o16 ] , %sr", "%sw = atomic_fetch_add ( ( u32 * ) ( %dr %o16 ) , %sw )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
|
||||
{BPF_INSN_AFOR32, "afor32%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFOR32, "afor32%W[ %dr %o16 ] , %sr", "%sw = atomic_fetch_or ( ( u32 * ) ( %dr %o16 ) , %sw )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
|
||||
{BPF_INSN_AFAND32, "afand32%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFAND32, "afand32%W[ %dr %o16 ] , %sr", "%sw = atomic_fetch_and ( ( u32 * ) ( %dr %o16 ) , %sw )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
|
||||
{BPF_INSN_AFXOR32, "afxor32%W[ %dr %o16 ] , %sr", "???",
|
||||
{BPF_INSN_AFXOR32, "afxor32%W[ %dr %o16 ] , %sr", "%sw = atomic_fetch_xor ( ( u32 * ) ( %dr %o16 ) , %sw )",
|
||||
BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
|
||||
|
||||
/* Old versions of aadd and aadd32. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user