diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 50fc8deb409..db3527bf302 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2016-08-19  Yao Qi  <yao.qi@linaro.org>
+
+	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
+	based STP instruction.
+
 2016-08-19  Yao Qi  <yao.qi@linaro.org>
 
 	* completer.c (linespec_location_completer): Make file_to_match
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e97e2f41ddb..3b7e954424e 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -322,10 +322,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 			 is64 ? 8 : 4, regs[rt]);
 	}
       else if ((inst.opcode->iclass == ldstpair_off
-		|| inst.opcode->iclass == ldstpair_indexed)
-	       && inst.operands[2].addr.preind
+		|| (inst.opcode->iclass == ldstpair_indexed
+		    && inst.operands[2].addr.preind))
 	       && strcmp ("stp", inst.opcode->name) == 0)
 	{
+	  /* STP with addressing mode Pre-indexed and Base register.  */
 	  unsigned rt1 = inst.operands[0].reg.regno;
 	  unsigned rt2 = inst.operands[1].reg.regno;
 	  unsigned rn = inst.operands[2].addr.base_regno;