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Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when zero.

Browse Source 
PR binutils/19157
opcodes	* rl78-decode.opc: Add 'a' print operator to mov instructions
	using stack pointer plus index addressing.
	* rl78-decode.c: Regenerate.

tests	* gas/rl78: New directory.
	* gas/rl78/rl78.exp: New test driver.
	* gas/rl78/pr19157.s: New test source file.
	* gas/rl78/pr19157.d: New test case.
This commit is contained in:
Vinay Kumar 2015-10-27 14:00:40 +00:00 committed by Nick Clifton
parent c6486df5f1
commit 02f12cd466
7 changed files with 86 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gas/testsuite/ChangeLog
View File

@ -1,3 +1,11 @@
2015-10-27 Nick Clifton <nickc@redhat.com>
PR binutils/19157
* gas/rl78: New directory.
* gas/rl78/rl78.exp: New test driver.
* gas/rl78/pr19157.s: New test source file.
* gas/rl78/pr19157.d: New test case.
2015-10-22 Nick Clifton <nickc@redhat.com>
* gas/msp430/errata_fixes.s: New test source file.

15
gas/testsuite/gas/rl78/pr19157.d Normal file
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@ -0,0 +1,15 @@
#objdump: -d --prefix-addresses --show-raw-insn
#name: PR19157: RL78: zero offset omitted
.*: +file format .*rl78.*
Disassembly of section .text:
0x0+000 88 00[ ]+mov[ ]+a, \[sp\+0\]
0x0+002 88 00[ ]+mov[ ]+a, \[sp\+0\]
0x0+004 88 01[ ]+mov[ ]+a, \[sp\+1\]
0x0+006 a8 00[ ]+movw[ ]+ax, \[sp\+0\]
0x0+008 a8 00[ ]+movw[ ]+ax, \[sp\+0\]
0x0+00a a8 02[ ]+movw[ ]+ax, \[sp\+2\]
0x0+00c c8 00 09[ ]+mov[ ]+\[sp\+0\], #9
0x0+00f c8 00 09[ ]+mov[ ]+\[sp\+0\], #9
0x0+012 c8 01 09[ ]+mov[ ]+\[sp\+1\], #9

13
gas/testsuite/gas/rl78/pr19157.s Normal file
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@ -0,0 +1,13 @@
.text
mov a, [sp]
mov a, [sp + 0]
mov a, [sp + 1]
movw ax, [sp]
movw ax, [sp + 0]
movw ax, [sp + 2]
mov [sp], # 9
mov [sp + 0], # 9
mov [sp + 1], # 9
.end

23
gas/testsuite/gas/rl78/rl78.exp Normal file
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@ -0,0 +1,23 @@
# Copyright (C) 2015 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#
# RL78 tests
#
if [expr [istarget "rl78-*-*"]] then {
run_dump_test "pr19157"
}

7
opcodes/ChangeLog
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@ -1,3 +1,10 @@
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
PR binutils/19157
* rl78-decode.opc: Add 'a' print operator to mov instructions
using stack pointer plus index addressing.
* rl78-decode.c: Regenerate.
2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Fix comment.

30
opcodes/rl78-decode.c
View File

@ -4331,14 +4331,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0x88:
{
/** 1000 1000 mov %0, %e1 */
/** 1000 1000 mov %0, %ea1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1000 1000 mov %0, %e1 */",
"/** 1000 1000 mov %0, %ea1 */",
op[0]);
}
SYNTAX("mov %0, %e1");
SYNTAX("mov %0, %ea1");
#line 666 "rl78-decode.opc"
ID(mov); DR(A); SM(SP, IMMU(1));
@ -4476,14 +4476,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0x98:
{
/** 1001 1000 mov %0, %1 */
/** 1001 1000 mov %a0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1001 1000 mov %0, %1 */",
"/** 1001 1000 mov %a0, %1 */",
op[0]);
}
SYNTAX("mov %0, %1");
SYNTAX("mov %a0, %1");
#line 642 "rl78-decode.opc"
ID(mov); DM(SP, IMMU(1)); SR(A);
@ -4683,14 +4683,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xa8:
{
/** 1010 1000 movw %0, %1 */
/** 1010 1000 movw %0, %a1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1010 1000 movw %0, %1 */",
"/** 1010 1000 movw %0, %a1 */",
op[0]);
}
SYNTAX("movw %0, %1");
SYNTAX("movw %0, %a1");
#line 850 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(SP, IMMU(1));
@ -4889,14 +4889,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xb8:
{
/** 1011 1000 movw %0, %1 */
/** 1011 1000 movw %a0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1011 1000 movw %0, %1 */",
"/** 1011 1000 movw %a0, %1 */",
op[0]);
}
SYNTAX("movw %0, %1");
SYNTAX("movw %a0, %1");
#line 831 "rl78-decode.opc"
ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
@ -5053,14 +5053,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xc8:
{
/** 1100 1000 mov %0, #%1 */
/** 1100 1000 mov %a0, #%1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1100 1000 mov %0, #%1 */",
"/** 1100 1000 mov %a0, #%1 */",
op[0]);
}
SYNTAX("mov %0, #%1");
SYNTAX("mov %a0, #%1");
#line 639 "rl78-decode.opc"
ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));

10
opcodes/rl78-decode.opc
View File

@ -635,10 +635,10 @@ rl78_decode_opcode (unsigned long pc AU,
/** 0110 0001 1111 1001 mov %e0, %1 */
ID(mov); DM2(HL, C, 0); SR(A);
/** 1100 1000 mov %0, #%1 */
/** 1100 1000 mov %a0, #%1 */
ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
/** 1001 1000 mov %0, %1 */
/** 1001 1000 mov %a0, %1 */
ID(mov); DM(SP, IMMU(1)); SR(A);
/** 1000 1111 mov %0, %e!1 */
@ -662,7 +662,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 0110 0001 1110 1001 mov %0, %e1 */
ID(mov); DR(A); SM2(HL, C, 0);
/** 1000 1000 mov %0, %e1 */
/** 1000 1000 mov %0, %ea1 */
ID(mov); DR(A); SM(SP, IMMU(1));
/** 0101 0reg mov %0, #%1 */
@ -827,7 +827,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1011 1100 movw %ea0, %1 */
ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
/** 1011 1000 movw %0, %1 */
/** 1011 1000 movw %a0, %1 */
ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
/** 1010 1111 movw %0, %e!1 */
@ -846,7 +846,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1010 1100 movw %0, %ea1 */
ID(mov); W(); DR(AX); SM(HL, IMMU(1));
/** 1010 1000 movw %0, %1 */
/** 1010 1000 movw %0, %a1 */
ID(mov); W(); DR(AX); SM(SP, IMMU(1));
/** 0011 0rg0 movw %0, #%1 */