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* core.c: Rename to corefile.c

Browse Source 
* core.h:  Rename to corefile.h
	* inline.c: Include corefile.h, renamed from core.h.
	* cpu.h: Include corefile.h, renamed from core.h
	* vm.c: Include corefile.h, renamed from core.h
	* Makefile.in (CPU_H): Change core.h to corefile.h
	(vm.o):  Change dependency to corefile.h
	(LIB_SRC): Change core.c to corefile.c.
	(LIB_OBJ): Change core.o to corefile.o.
	(corefile.o):  Change dependencies to corefile.c, corefile.h.
	* corefile.c: Include corefile.h rather than core.h
	* README.psim (KNOWN PROBLEMS): Change core.* references to corefile.*
	references.
This commit is contained in:
Fred Fish 1995-11-05 05:40:15 +00:00
parent a3d1c56107
commit 01860b7ed1
9 changed files with 108 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sim/ppc/.Sanitize
View File

@ -37,8 +37,8 @@ config.make
config.hdr
configure
configure.in
core.c
core.h
corefile.c
corefile.h
core_n.h
cpu.c
cpu.h

16
sim/ppc/ChangeLog
View File

@ -1,3 +1,19 @@
Sat Nov 4 12:29:45 1995 Fred Fish <fnf@cygnus.com>
* core.c: Rename to corefile.c
* core.h: Rename to corefile.h
* inline.c: Include corefile.h, renamed from core.h.
* cpu.h: Include corefile.h, renamed from core.h
* vm.c: Include corefile.h, renamed from core.h
* corefile.c: Include corefile.h rather than core.h
* README.psim (KNOWN PROBLEMS): Change core.* references to corefile.*
references.
* Makefile.in (CPU_H): Change core.h to corefile.h
(vm.o): Change dependency to corefile.h
(LIB_SRC): Change core.c to corefile.c.
(LIB_OBJ): Change core.o to corefile.o.
(corefile.o): Change dependencies to corefile.c, corefile.h.
Fri Nov 3 11:37:24 1995 Michael Meissner <meissner@tiktok.cygnus.com>
* ppc-instructions (data cache instructions): Make all data cache

10
sim/ppc/Makefile.in
View File

@ -156,7 +156,7 @@ CPU_H = \
$(BASICS_H) \
$(REGISTERS_H) \
device_tree.h \
core.h \
corefile.h \
vm.h \
events.h \
interrupts.h \
@ -191,7 +191,7 @@ LIB_SRC = \
debug.c \
ppc-endian.c \
vm.c \
core.c \
corefile.c \
events.c \
os_emul.c \
emul_generic.c \
@ -220,7 +220,7 @@ LIB_OBJ = \
emul_netbsd.o \
registers.o \
vm.o \
core.o \
corefile.o \
spreg.o \
cpu.o \
interrupts.o \
@ -276,9 +276,9 @@ idecode.o: idecode.c $(CPU_H) $(IDECODE_H) semantics.h
# double.o: double.c dp-bit.c
vm.o: vm.c vm.h vm_n.h $(BASICS_H) $(REGISTERS_H) \
device_tree.h core.h interrupts.h itable.h mon.h
device_tree.h corefile.h interrupts.h itable.h mon.h
core.o: core.c core.h $(BASICS_H) device_tree.h
corefile.o: corefile.c corefile.h $(BASICS_H) device_tree.h
events.o: events.c events.h $(BASICS_H)

2
sim/ppc/README.psim
View File

@ -203,7 +203,7 @@ KNOWN PROBLEMS:
See the ChangeLog file looking for lines taged with the word FIXME.
CORE.C: The implementation of core.c (defined by core.h) isn't the
COREFILE.C: The implementation of corefile.c (defined by corefile.h) isn't the
best. It is intended to be functionaly correct rather than fast.
HTAB (page) code for OEA model untested. Some of the vm code

155
sim/ppc/core.h
View File

@ -1,155 +0,0 @@
/* This file is part of the program psim.
Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CORE_H_
#define _CORE_H_
#ifndef INLINE_CORE
#define INLINE_CORE
#endif
/* basic types */
typedef struct _core core;
typedef struct _core_map core_map;
/* constructor */
INLINE_CORE core *core_create
(void);
INLINE_CORE const device *core_device_create
(core *);
/* the core has three sub mappings that the more efficient
read/write fixed quantity functions use */
INLINE_CORE core_map *core_readable
(core *memory);
INLINE_CORE core_map *core_writeable
(core *memory);
INLINE_CORE core_map *core_executable
(core *memory);
/* operators to add/remove a mapping in the core
callback-memory:
All access are passed onto the specified devices callback routines
after being `translated'. DEFAULT indicates that the specified
memory should be called if all other mappings fail.
For callback-memory, the device must be specified.
raw-memory:
While RAM could be implemented using the callback interface
core instead treats it as the common case including the code
directly in the read/write operators.
For raw-memory, the device is ignored and the core alloc's a
block to act as the memory.
default-memory:
Should, for the core, there be no defined mapping for a given
address then the default map (if present) is called.
For default-memory, the device must be specified. */
INLINE_CORE void core_attach
(core *map,
attach_type attach,
int address_space,
access_type access,
unsigned_word addr,
unsigned nr_bytes, /* host limited */
const device *device); /*callback/default*/
INLINE_CORE void core_detach
(core *map,
attach_type attach,
int address_space,
unsigned_word addr,
unsigned nr_bytes, /* host limited */
access_type access,
const device *device); /*callback/default*/
/* Variable sized read/write:
Transfer (zero) a variable size block of data between the host and
target (possibly byte swapping it). Should any problems occure,
the number of bytes actually transfered is returned. */
INLINE_CORE unsigned core_map_read_buffer
(core_map *map,
void *buffer,
unsigned_word addr,
unsigned nr_bytes);
INLINE_CORE unsigned core_map_write_buffer
(core_map *map,
const void *buffer,
unsigned_word addr,
unsigned nr_bytes);
/* Fixed sized read/write:
Transfer a fixed amout of memory between the host and target. The
memory always being translated and the operation always aborting
should a problem occure */
#define DECLARE_CORE_WRITE_N(N) \
INLINE_CORE void core_map_write_##N \
(core_map *map, \
unsigned_word addr, \
unsigned_##N val, \
cpu *processor, \
unsigned_word cia);
DECLARE_CORE_WRITE_N(1)
DECLARE_CORE_WRITE_N(2)
DECLARE_CORE_WRITE_N(4)
DECLARE_CORE_WRITE_N(8)
DECLARE_CORE_WRITE_N(word)
#define DECLARE_CORE_READ_N(N) \
INLINE_CORE unsigned_##N core_map_read_##N \
(core_map *map, \
unsigned_word addr, \
cpu *processor, \
unsigned_word cia);
DECLARE_CORE_READ_N(1)
DECLARE_CORE_READ_N(2)
DECLARE_CORE_READ_N(4)
DECLARE_CORE_READ_N(8)
DECLARE_CORE_READ_N(word)
#endif

2
sim/ppc/core.c → sim/ppc/corefile.c
View File

@ -29,7 +29,7 @@
#include "basics.h"
#include "device_tree.h"
#include "core.h"
#include "corefile.h"
typedef struct _core_mapping core_mapping;

2
sim/ppc/cpu.h
View File

@ -29,7 +29,7 @@
#include "basics.h"
#include "registers.h"
#include "device_tree.h"
#include "core.h"
#include "corefile.h"
#include "vm.h"
#include "events.h"
#include "interrupts.h"

81
sim/ppc/inline.c Normal file
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@ -0,0 +1,81 @@
/* This file is part of the program psim.
Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _PPC_INLINE_C_
#define _PPC_INLINE_C_
#if ENDIAN_INLINE
#include "ppc-endian.c"
#endif
#if ICACHE_INLINE
#include "icache.c"
#endif
#if CORE_INLINE
#include "corefile.c"
#endif
#if VM_INLINE
#include "vm.c"
#endif
#if CPU_INLINE
#include "cpu.c"
#endif
#if EVENTS_INLINE
#include "events.c"
#endif
#if MON_INLINE
#include "mon.c"
#endif
#if REGISTERS_INLINE
#include "registers.c"
#endif
#if INTERRUPTS_INLINE
#include "interrupts.c"
#endif
#if DEVICE_TREE_INLINE
#include "device_tree.c"
#endif
#if DEVICES_INLINE
#include "devices.c"
#endif
#if SPREG_INLINE
#include "spreg.c"
#endif
#if SEMANTICS_INLINE
#include "semantics.c"
#endif
#if IDECODE_INLINE
#include "idecode.c"
#endif
#endif

2
sim/ppc/vm.c
View File

@ -32,7 +32,7 @@
#include "registers.h"
#include "device_tree.h"
#include "core.h"
#include "corefile.h"
#include "vm.h"