2011-03-06 08:20:21 +08:00
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/* Blackfin Watchpoint (WP) model.
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2021-01-01 16:03:39 +08:00
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Copyright (C) 2010-2021 Free Software Foundation, Inc.
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2011-03-06 08:20:21 +08:00
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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2021-05-02 06:05:23 +08:00
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/* This must come before any other includes. */
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#include "defs.h"
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2011-03-06 08:20:21 +08:00
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_wp.h"
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/* XXX: This is mostly a stub. */
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#define WPI_NUM 6 /* 6 instruction watchpoints. */
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#define WPD_NUM 2 /* 2 data watchpoints. */
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struct bfin_wp
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{
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bu32 base;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 iactl;
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bu32 _pad0[15];
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bu32 ia[WPI_NUM];
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bu32 _pad1[16 - WPI_NUM];
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bu32 iacnt[WPI_NUM];
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bu32 _pad2[32 - WPI_NUM];
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bu32 dactl;
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bu32 _pad3[15];
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bu32 da[WPD_NUM];
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bu32 _pad4[16 - WPD_NUM];
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bu32 dacnt[WPD_NUM];
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bu32 _pad5[32 - WPD_NUM];
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bu32 stat;
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};
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#define mmr_base() offsetof(struct bfin_wp, iactl)
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#define mmr_offset(mmr) (offsetof(struct bfin_wp, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
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2011-03-16 04:44:11 +08:00
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static const char * const mmr_names[] =
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{
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2011-03-06 08:20:21 +08:00
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[mmr_idx (iactl)] = "WPIACTL",
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[mmr_idx (ia)] = "WPIA0", "WPIA1", "WPIA2", "WPIA3", "WPIA4", "WPIA5",
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[mmr_idx (iacnt)] = "WPIACNT0", "WPIACNT1", "WPIACNT2",
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"WPIACNT3", "WPIACNT4", "WPIACNT5",
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[mmr_idx (dactl)] = "WPDACTL",
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[mmr_idx (da)] = "WPDA0", "WPDA1", "WPDA2", "WPDA3", "WPDA4", "WPDA5",
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[mmr_idx (dacnt)] = "WPDACNT0", "WPDACNT1", "WPDACNT2",
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"WPDACNT3", "WPDACNT4", "WPDACNT5",
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[mmr_idx (stat)] = "WPSTAT",
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};
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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static unsigned
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bfin_wp_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_wp *wp = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu32 *valuep;
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2015-12-27 08:02:07 +08:00
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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2011-03-06 08:20:21 +08:00
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value = dv_load_4 (source);
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mmr_off = addr - wp->base;
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valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(iactl):
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case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]):
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case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]):
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case mmr_offset(dactl):
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case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]):
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case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]):
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*valuep = value;
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break;
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case mmr_offset(stat):
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/* Yes, the hardware is this dumb -- clear all bits on any write. */
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*valuep = 0;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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2015-12-27 08:02:07 +08:00
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return 0;
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2011-03-06 08:20:21 +08:00
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}
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return nr_bytes;
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}
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static unsigned
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bfin_wp_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_wp *wp = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu32 *valuep;
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2015-12-27 08:02:07 +08:00
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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2011-03-06 08:20:21 +08:00
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mmr_off = addr - wp->base;
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valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(iactl):
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case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]):
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case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]):
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case mmr_offset(dactl):
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case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]):
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case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]):
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case mmr_offset(stat):
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value = *valuep;
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break;
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default:
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2015-12-27 08:02:07 +08:00
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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2011-03-06 08:20:21 +08:00
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}
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dv_store_4 (dest, value);
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return nr_bytes;
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}
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static void
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attach_bfin_wp_regs (struct hw *me, struct bfin_wp *wp)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_COREMMR_WP_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_WP_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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wp->base = attach_address;
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}
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static void
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bfin_wp_finish (struct hw *me)
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{
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struct bfin_wp *wp;
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wp = HW_ZALLOC (me, struct bfin_wp);
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set_hw_data (me, wp);
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set_hw_io_read_buffer (me, bfin_wp_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_wp_io_write_buffer);
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attach_bfin_wp_regs (me, wp);
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}
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2011-03-16 04:55:11 +08:00
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const struct hw_descriptor dv_bfin_wp_descriptor[] =
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{
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2011-03-06 08:20:21 +08:00
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{"bfin_wp", bfin_wp_finish,},
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{NULL, NULL},
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};
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