2016-11-02 00:45:57 +08:00
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/* BFD backend for RISC-V
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2021-01-01 06:58:58 +08:00
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Copyright (C) 2011-2021 Free Software Foundation, Inc.
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2016-11-02 00:45:57 +08:00
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Contributed by Andrew Waterman (andrew@sifive.com).
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Based on MIPS target.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include "bfd.h"
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#include "libbfd.h"
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2021-01-28 10:45:56 +08:00
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#include "cpu-riscv.h"
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2016-11-02 00:45:57 +08:00
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static const bfd_arch_info_type *
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riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
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{
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if (a->arch != b->arch)
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return NULL;
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/* Machine compatibility is checked in
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_bfd_riscv_elf_merge_private_bfd_data. */
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return a;
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}
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2020-01-28 07:19:30 +08:00
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/* Return TRUE if STRING matches the architecture described by INFO. */
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static bfd_boolean
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riscv_scan (const struct bfd_arch_info *info, const char *string)
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{
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if (bfd_default_scan (info, string))
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return TRUE;
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bfd/riscv: tighten matching rules in riscv_scan
The following GDB behaviour was observed:
(gdb) x/1i 0x0001014a
0x1014a <main+8>: jal 0x10132 <foo>
(gdb) show architecture
The target architecture is set automatically (currently riscv:rv32)
(gdb) set architecture riscv:rv32
The target architecture is assumed to be riscv:rv32
(gdb) x/1i 0x0001014a
0x1014a <main+8>: 0x37e5
(gdb)
Notice that initially we can disassemble the instruction (it's a
compressed jal instruction), but after setting the architecture we can
no longer disassemble the instruction.
This is particularly puzzling as GDB initially thought the
architecture was 'riscv:rv32', but when we force the architecture to
be that, the disassembly stops working.
This issue was introduced with this commit:
commit c35d018b1a5ec604e49a807402c4205530b25ca8
Date: Mon Jan 27 15:19:30 2020 -0800
RISC-V: Fix gdbserver problem with handling arch strings.
In this commit we try to make riscv_scan handle cases where we see
architecture strings like 'riscv:rv32imc' (for example). Normally
this wouldn't match as bfd_default_scan requires an exact match, so we
extended riscv_scan to ignore trailing characters.
Unfortunately the default riscv arch is called 'riscv', is 64-bit,
and has its mach type set to 0, which I think is intended to pair with
code is riscv-dis.c:riscv_disassemble_insn that tries to guess if we
are 32 or 64 bit.
What happens then is that 'riscv:rv32' is first tested against 'riscv'
using bfd_default_scan, this doesn't match, we then compare this to
'riscv', but allowing trailing characters to be ignored, this matches,
and our 'riscv:rv32' matches against the default (64-bit)
architecture.
The solution I propose is to prevent the default architecture from
taking part in this "ignore trailing characters" extra match case,
only the more specific 'riscv:rv32' and 'riscv:rv64' get this extra
matching.
bfd/ChangeLog:
* cpu-riscv.c (riscv_scan): Don't allow shorter matches using the
default architecture.
2020-06-24 06:22:43 +08:00
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/* The incoming STRING might take the form of riscv:rvXXzzz, where XX is
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32 or 64, and zzz are one or more extension characters. As we
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currently only have 3 architectures defined, 'riscv', 'riscv:rv32',
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and 'riscv:rv64', we would like to ignore the zzz for the purpose of
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matching here.
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However, we don't want the default 'riscv' to match over a more
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specific 'riscv:rv32' or 'riscv:rv64', so in the case of the default
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architecture (with the shorter 'riscv' name) we don't allow any
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special matching, but for the 'riscv:rvXX' cases, we allow a match
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with any additional trailing characters being ignored. */
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if (!info->the_default
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&& strncasecmp (string, info->printable_name,
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strlen (info->printable_name)) == 0)
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return TRUE;
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return FALSE;
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}
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2019-09-10 22:20:58 +08:00
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#define N(BITS, NUMBER, PRINT, DEFAULT, NEXT) \
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2016-11-02 00:45:57 +08:00
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{ \
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BITS, /* Bits in a word. */ \
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BITS, /* Bits in an address. */ \
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8, /* Bits in a byte. */ \
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2016-11-02 00:45:57 +08:00
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bfd_arch_riscv, \
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NUMBER, \
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"riscv", \
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PRINT, \
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3, \
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DEFAULT, \
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riscv_compatible, \
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riscv_scan, \
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2016-11-02 00:45:57 +08:00
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bfd_arch_default_fill, \
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NEXT, \
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0 /* Maximum offset of a reloc from the start of an insn. */\
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2016-11-02 00:45:57 +08:00
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}
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/* This enum must be kept in the same order as arch_info_struct. */
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enum
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{
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I_riscv64,
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I_riscv32
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};
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#define NN(index) (&arch_info_struct[(index) + 1])
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/* This array must be kept in the same order as the anonymous enum above,
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and each entry except the last should end with NN (my enum value). */
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)),
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N (32, bfd_mach_riscv32, "riscv:rv32", FALSE, NULL)
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2016-11-02 00:45:57 +08:00
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};
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/* The default architecture is riscv:rv64. */
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const bfd_arch_info_type bfd_riscv_arch =
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N (64, 0, "riscv", TRUE, &arch_info_struct[0]);
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2021-01-28 10:45:56 +08:00
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/* List for all supported ISA spec versions. */
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const struct riscv_spec riscv_isa_specs[] =
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{
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{"2.2", ISA_SPEC_CLASS_2P2},
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{"20190608", ISA_SPEC_CLASS_20190608},
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{"20191213", ISA_SPEC_CLASS_20191213},
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};
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/* List for all supported privileged spec versions. */
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const struct riscv_spec riscv_priv_specs[] =
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{
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{"1.9.1", PRIV_SPEC_CLASS_1P9P1},
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{"1.10", PRIV_SPEC_CLASS_1P10},
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{"1.11", PRIV_SPEC_CLASS_1P11},
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};
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/* Get the corresponding CSR version class by giving privilege
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version numbers. It is usually used to convert the priv
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attribute numbers into the corresponding class. */
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void
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riscv_get_priv_spec_class_from_numbers (unsigned int major,
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unsigned int minor,
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unsigned int revision,
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enum riscv_spec_class *class)
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{
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enum riscv_spec_class class_t = *class;
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char buf[36];
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if (revision != 0)
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snprintf (buf, sizeof (buf), "%u.%u.%u", major, minor, revision);
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else
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snprintf (buf, sizeof (buf), "%u.%u", major, minor);
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RISCV_GET_PRIV_SPEC_CLASS (buf, class_t);
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*class = class_t;
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}
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