2009-05-26 11:19:28 +08:00
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2009-05-26 Alan Modra <amodra@bigpond.net.au>
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* dep-in.sed: Don't modify .o to .lo here. Output one filename
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per line with all lines having continuation backslash. Prefix
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first line with "A", following lines with "B".
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* Makefile.am (DEP): Don't use dep.sed here.
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(DEP1): Run $MKDEP on single files, modify .o to .lo here. Use
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dep.sed here on dependencies, sort and uniq.
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* Makefile.in: Regenerate.
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2009-05-25 20:43:48 +08:00
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2009-05-25 Tristan Gingold <gingold@adacore.com>
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* makefile.vms (OPT): New variable.
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(CFLAGS): Update compilation flags.
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2009-05-23 01:37:45 +08:00
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2009-05-22 DJ Delorie <dj@redhat.com>
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* mep-asm.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mep-desc.h: Regenerate.
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* mep-dis.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mep-opc.c: Regenerate.
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* mep-opc.h: Regenerate.
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2009-05-22 23:57:25 +08:00
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2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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* i386-opc.h (Cpusse5): Delete.
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(i386_cpu_flags): Delete.
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* i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc.
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* i386-opc.tbl: Remove SSE5 instructions.
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* i386-tbl.h: Regenerate.
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* i386-init.h: Regenerate.
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* i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling.
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(print_drex_arg): Delete.
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(OP_DREX4): Delete.
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(OP_DREX3): Delete.
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(OP_DREX_ICMP): Delete.
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(OP_DREX_FCMP): Delete.
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(DREX_*): Delete.
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(THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
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2009-05-22 17:33:16 +08:00
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2009-05-22 Alan Modra <amodra@bigpond.net.au>
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* Makefile.am: Run "make dep-am".
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* Makefile.in: Regenerate.
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* po/POTFILES.in: Regenerate.
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2009-05-20 07:35:47 +08:00
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2009-05-19 DJ Delorie <dj@redhat.com>
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* mep-asm.c: Regenerate.
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* mep-opc.c: Regenerate.
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2009-05-01 05:23:30 +08:00
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2009-04-30 DJ Delorie <dj@redhat.com>
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* mep-asm.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mep-desc.h: Regenerate.
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* mep-dis.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mep-opc.c: Regenerate.
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* mep-opc.h: Regenerate.
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2009-04-18 10:56:43 +08:00
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2009-04-17 DJ Delorie <dj@redhat.com
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* mep-desc.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mep-opc.c: Regenerate.
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* mep-opc.h: Regenerate.
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2009-04-16 23:39:48 +08:00
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2009-04-15 Anthony Green <green@moxielogic.com>
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* moxie-opc.c, moxie-dis.c: Created.
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* Makefile.am: Build the moxie source files.
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* configure.in: Add moxie support.
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* Makefile.in, configure: Rebuilt.
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* disassemble.c (disassembler): Add moxie support.
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(ARCH_moxie): Define.
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2009-04-15 21:31:28 +08:00
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2009-04-15 Jan Beulich <jbeulich@novell.com>
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* i386-opc.tbl (protb, protw, protd, protq): Set opcode
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extension to None.
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(pshab, pshaw, pshad, pshaq): Likewise.
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* i386-tbl.h: Re-generate.
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2009-04-18 09:50:02 +08:00
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2009-04-08 DJ Delorie <dj@redhat.com
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* mep-asm.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mep-desc.h: Regenerate.
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* mep-dis.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mep-opc.c: Regenerate.
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* mep-opc.h: Regenerate.
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2009-04-08 02:28:02 +08:00
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2009-04-07 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva",
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"tlbilx">: Use secondary opcode "18" as per the ISA 2.06 documentation.
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Reorder entries so the extended mnemonics are listed before tlbilx.
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2009-04-02 21:30:56 +08:00
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2009-04-02 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect
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due to -many/-Many.
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(print_insn_powerpc): Make sure we only deprecate instructions using
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the original dialect and not a modified dialect due to -Many handling.
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Move the handling of the condition register and default operands to
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the end of the if/else if/else chain.
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* ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
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instructions from newer processors are listed before older ones.
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<"icblce", "sync", "eieio", "tlbld">: Deprecate for processors
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that have instructions with conflicting opcodes.
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2009-04-02 08:42:29 +08:00
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2009-04-01 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and
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E500MC entries.
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2009-04-01 23:45:13 +08:00
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2009-04-01 Christophe Lyon <christophe.lyon@st.com>
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* arm-dis.c (print_insn): Print BE8 opcodes in little endianness.
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2009-03-30 22:41:31 +08:00
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2009-03-30 Joseph Myers <joseph@codesourcery.com>
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* arm-dis.c (print_insn): Also check section matches in backwards
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search for mapping symbol.
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2009-03-27 08:28:32 +08:00
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2009-03-26 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (get_valid_dis386): Abort on unhandled table.
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2009-03-18 19:27:18 +08:00
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2009-03-18 Alan Modra <amodra@bigpond.net.au>
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2009-03-18 19:47:18 +08:00
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* cgen-opc.c: Include alloca-conf.h rather than alloca.h.
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2009-03-18 19:27:18 +08:00
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* Makefile.am: Run "make dep-am".
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* Makefile.in: Regenerate.
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* openrisc-opc.c: Regenerate.
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2009-03-10 17:21:01 +08:00
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2009-03-10 Nick Clifton <nickc@redhat.com>
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* po/id.po: Updated Indonesian translation.
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2009-03-10 14:53:46 +08:00
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2009-03-10 Alan Modra <amodra@bigpond.net.au>
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* ppc-dis.c: Include "opintl.h".
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(struct ppc_mopt, ppc_opts): New.
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(ppc_parse_cpu): New function.
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(powerpc_init_dialect): Use it.
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(print_ppc_disassembler_options): Dump options from ppc_opts.
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Internationalize message.
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2009-03-06 20:14:40 +08:00
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2009-03-06 Nick Clifton <nickc@redhat.com>
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* po/es.po: Updated Spanish translation.
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2009-03-04 10:10:34 +08:00
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2009-03-04 Alan Modra <amodra@bigpond.net.au>
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PR 6768
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* configure.in: Test for ld --as-needed support. Link shared
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libopcodes against libm.
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* configure: Regenerate.
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2009-03-04 09:00:53 +08:00
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2009-03-03 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
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instructions from newer processors are listed before older ones.
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2009-03-04 09:16:15 +08:00
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2009-03-03 Alan Modra <amodra@bigpond.net.au>
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* Makefile.am: Run "make dep-am".
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(HFILES): Move lm32-desc.h and lm32-opc.h from..
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(CFILES): ..here.
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* Makefile.in: Regenerate.
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2009-03-02 18:33:08 +08:00
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2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
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* score7-dis.c: New file.
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* Makefile.am: Add dependencies for score7-dis.c.
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* Makefile.in: Regenerate.
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* configure.in: Add score7-dis to score files.
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* configure: Regenerate.
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* score-dis.c: Add support for score7 architecture.
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* score-opc.h: Likewise.
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2009-03-02 02:57:19 +08:00
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2009-03-01 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
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* configure: Regenerate.
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2009-02-28 04:13:04 +08:00
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2009-02-27 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (OP_EX): Call OP_E_memory instead of OP_E.
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gas/
* config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63",
"f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63".
(parse_cpu): Extend -mpower7 to accept power7 and isel instructions.
gas/testsuite/
* gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.
* gas/ppc/e500mc.s: Likewise.
* gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests.
* gas/ppc/power6.s: Likewise.
* gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests.
("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.",
"divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw",
"popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.",
"fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.",
"fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.",
"ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix",
"dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx",
"stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte",
"frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests.
* gas/ppc/power7.s: Likewise.
* gas/ppc/vsx.d: New test.
* gas/ppc/vsx.s: Likewise.
* gas/ppc/ppc.exp: Run it.
include/opcode/
* ppc.h (PPC_OPCODE_POWER7): New.
opcodes/
* ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble
the power7 and the isel instructions.
* ppc-opc.c (insert_xc6, extract_xc6): New static functions.
(insert_dm, extract_dm): Likewise.
(XB6): Update comment to include XX2 form.
(WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK,
XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New.
(RemoveXX3DM): Delete.
(powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr",
"mftgpr">: Deprecate for POWER7.
<"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte",
"frsqrte.">: Deprecate the three operand form and enable the two
operand form for POWER7 and later.
<"wait">: Extend to accept optional parameter. Enable for POWER7.
<"waitsrv", "waitimpl">: Add extended opcodes.
<"ldbrx", "stdbrx">: Enable for POWER7.
<"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes.
<"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde",
"divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo",
"divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.",
"divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.",
"fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.",
"fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx",
"lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes.
<"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx",
"stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp",
"xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds",
"xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp",
"xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp",
"xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp",
"xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic",
"xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp",
"xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp",
"xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp",
"xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.",
"xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp",
"xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp",
"xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp",
"xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp",
"xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp",
"xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp",
"xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp",
"xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp",
"xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp",
"xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi",
"xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp",
"xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp",
"xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp",
"xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor",
"xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd",
"xxspltw", "xxswapd">: Add VSX opcodes.
2009-02-27 06:07:33 +08:00
|
|
|
|
2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble
|
|
|
|
|
|
the power7 and the isel instructions.
|
|
|
|
|
|
* ppc-opc.c (insert_xc6, extract_xc6): New static functions.
|
|
|
|
|
|
(insert_dm, extract_dm): Likewise.
|
|
|
|
|
|
(XB6): Update comment to include XX2 form.
|
|
|
|
|
|
(WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK,
|
|
|
|
|
|
XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New.
|
|
|
|
|
|
(RemoveXX3DM): Delete.
|
|
|
|
|
|
(powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr",
|
|
|
|
|
|
"mftgpr">: Deprecate for POWER7.
|
|
|
|
|
|
<"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte",
|
|
|
|
|
|
"frsqrte.">: Deprecate the three operand form and enable the two
|
|
|
|
|
|
operand form for POWER7 and later.
|
|
|
|
|
|
<"wait">: Extend to accept optional parameter. Enable for POWER7.
|
|
|
|
|
|
<"waitsrv", "waitimpl">: Add extended opcodes.
|
|
|
|
|
|
<"ldbrx", "stdbrx">: Enable for POWER7.
|
|
|
|
|
|
<"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes.
|
|
|
|
|
|
<"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde",
|
|
|
|
|
|
"divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo",
|
|
|
|
|
|
"divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.",
|
|
|
|
|
|
"divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.",
|
|
|
|
|
|
"fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.",
|
|
|
|
|
|
"fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx",
|
|
|
|
|
|
"lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes.
|
|
|
|
|
|
<"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx",
|
|
|
|
|
|
"stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp",
|
|
|
|
|
|
"xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds",
|
|
|
|
|
|
"xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp",
|
|
|
|
|
|
"xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp",
|
|
|
|
|
|
"xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp",
|
|
|
|
|
|
"xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic",
|
|
|
|
|
|
"xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp",
|
|
|
|
|
|
"xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp",
|
|
|
|
|
|
"xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp",
|
|
|
|
|
|
"xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.",
|
|
|
|
|
|
"xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp",
|
|
|
|
|
|
"xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp",
|
|
|
|
|
|
"xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp",
|
|
|
|
|
|
"xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp",
|
|
|
|
|
|
"xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp",
|
|
|
|
|
|
"xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp",
|
|
|
|
|
|
"xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp",
|
|
|
|
|
|
"xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp",
|
|
|
|
|
|
"xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp",
|
|
|
|
|
|
"xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi",
|
|
|
|
|
|
"xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp",
|
|
|
|
|
|
"xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp",
|
|
|
|
|
|
"xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp",
|
|
|
|
|
|
"xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor",
|
|
|
|
|
|
"xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd",
|
|
|
|
|
|
"xxspltw", "xxswapd">: Add VSX opcodes.
|
|
|
|
|
|
|
2009-02-24 04:41:46 +08:00
|
|
|
|
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4.
|
|
|
|
|
|
(operand_types): Remove Vex_Imm4.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (Vex_Imm4): Removed.
|
|
|
|
|
|
(OTMax): Updated.
|
|
|
|
|
|
(i386_operand_type): Remove vex_imm4.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Remove Vex_Imm4 comments.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2009-02-23 22:58:34 +08:00
|
|
|
|
2009-02-23 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (neon_opcodes): Correct bit-mask and patterns for
|
|
|
|
|
|
vq{r}shr{u}n.s64 insnstructions.
|
|
|
|
|
|
|
2009-02-20 05:18:46 +08:00
|
|
|
|
2009-02-19 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first
|
|
|
|
|
|
operand to be a float point register (FRT/FRS).
|
|
|
|
|
|
|
2009-02-19 04:51:59 +08:00
|
|
|
|
2009-02-18 Adam Nemet <anemet@caviumnetworks.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
|
|
|
|
|
|
dmfc2 and dmtc2 before the architecture-level variants.
|
|
|
|
|
|
|
2009-02-19 01:13:04 +08:00
|
|
|
|
2009-02-18 Pierre Muller <muller@ics.u-strasbg.fr>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-opc.c: Regenerate.
|
|
|
|
|
|
* frv-opc.c: Regenerate.
|
|
|
|
|
|
* ip2k-opc.c: Regenerate.
|
|
|
|
|
|
* iq2000-opc.c: Regenerate.
|
|
|
|
|
|
* lm32-opc.c: Regenerate.
|
|
|
|
|
|
* m32c-opc.c: Regenerate.
|
|
|
|
|
|
* m32r-opc.c: Regenerate.
|
|
|
|
|
|
* mep-opc.c: Regenerate.
|
|
|
|
|
|
* mt-opc.c: Regenerate.
|
|
|
|
|
|
* xc16x-opc.c: Regenerate.
|
|
|
|
|
|
* xstormy16-opc.c: Regenerate.
|
|
|
|
|
|
* tic54x-dis.c (print_instruction): Avoid compiler warning on
|
|
|
|
|
|
sprintf call.
|
|
|
|
|
|
|
gas/
* config/tc-m68k.c (mcf51qe_ctrl): Add CPUCR.
(mcf52259_ctrl, mcf52277_ctrl, mcf53017_ctrl): New.
(mcf5307_ctrl): Add VBR.
(no_mac): New variable.
(m68k_extensions): Refer to no_mac mask.
(m68k_cpus): Add 51, 51ac, 51cn, 51em, 51jm, 52274, 52277,
52252..52259, 53011..53017.
(m68k_ip): Process CPUCR.
(init_table): Add cpucr entry.
(m68k_set_extension): Allow negated mask to refer to a variable.
(md_show_usage): Use '%s' to silence fprintf warning.
* config/m68k-parse.h (CPUCR): New control register.
gas/testsuite/
* m68k/br-isac.d, m68k/br-isac.s: Add stldsr test.
opcodes/
* m68k-opc.c (m68k_opcodes): Add stldsr instruction.
2009-02-12 16:31:03 +08:00
|
|
|
|
2009-02-12 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k-opc.c (m68k_opcodes): Add stldsr instruction.
|
|
|
|
|
|
|
2009-02-06 09:50:54 +08:00
|
|
|
|
2009-02-05 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c: Update copyright year.
|
|
|
|
|
|
(powerpc_opcodes) <"dcbt", "dcbtst">: Deprecate the Embedded operand
|
|
|
|
|
|
ordering for POWER4 and later and use the correct Server ordering.
|
|
|
|
|
|
|
2009-02-05 00:03:31 +08:00
|
|
|
|
2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
AVX Programming Reference (January, 2009)
|
|
|
|
|
|
* i386-dis.c (PREFIX_VEX_3A44): New.
|
|
|
|
|
|
(VEX_LEN_3A44_P_2): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A48): Updated.
|
|
|
|
|
|
(VEX_LEN_3A4C_P_2): Likewise.
|
|
|
|
|
|
(prefix_table): Add PREFIX_VEX_3A44.
|
|
|
|
|
|
(vex_table): Likewise.
|
|
|
|
|
|
(vex_len_table): Add VEX_LEN_3A44_P_2.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add PCLMUL + AVX instructions.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
bfd:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
* archures.c (bfd_mach_mips_xlr): Define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_xlr): Define.
(arch_info_struct): Add XLR entry.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
(mips_set_isa_flags): Handle bfd_mach_mips_xlr
(mips_mach_extensions): Add XLR entry.
binutils:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.
gas:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
M_MSGWAIT and M_MSGWAIT_T.
(mips_cpu_info_table): Add XLR entry.
* doc/c-mips.texi (-march): Document xlr.
gas/testsuite:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* gas/mips/mips.exp (xlr): New architecture.
(xlr-ext): Run test.
* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.
include/elf:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (E_MIPS_MACH_XLR): Define.
include/opcode:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
(INSN_CHIP_MASK): Update.
(CPU_XLR): Define.
(OPCODE_IS_MEMBER): Update.
(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
opcodes:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
(mips_arch_choices): Add XLR entry.
* mips-opc.c (XLR): Define.
(mips_builtin_opcodes): Add XLR instructions.
2009-02-04 02:16:04 +08:00
|
|
|
|
2009-02-03 Sandip Matte <sandip@rmicorp.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
|
|
|
|
|
|
(mips_arch_choices): Add XLR entry.
|
|
|
|
|
|
* mips-opc.c (XLR): Define.
|
|
|
|
|
|
(mips_builtin_opcodes): Add XLR instructions.
|
|
|
|
|
|
|
2009-02-03 23:54:05 +08:00
|
|
|
|
2009-02-03 Carlos O'Donell <carlos@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add install-pdf target.
|
|
|
|
|
|
* po/Make-in: Add install-pdf target.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
2009-02-03 10:15:57 +08:00
|
|
|
|
2009-02-02 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mep-asm.c: Regenerate.
|
|
|
|
|
|
* mep-desc.c: Regenerate.
|
|
|
|
|
|
* mep-desc.h: Regenerate.
|
|
|
|
|
|
* mep-dis.c: Regenerate.
|
|
|
|
|
|
* mep-ibld.c: Regenerate.
|
|
|
|
|
|
* mep-opc.c: Regenerate.
|
|
|
|
|
|
* mep-opc.h: Regenerate.
|
|
|
|
|
|
|
2009-01-29 19:48:34 +08:00
|
|
|
|
2009-01-29 Mark Mitchell <mark@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd,
|
|
|
|
|
|
qsub, and qdsub.
|
|
|
|
|
|
|
2009-01-28 16:45:47 +08:00
|
|
|
|
2009-01-28 Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (suxc1): Add the flag of FP_D.
|
|
|
|
|
|
|
2009-01-20 15:22:30 +08:00
|
|
|
|
2009-01-20 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* fr30-asm.c, fr30-dis.c, fr30-ibld.c, frv-asm.c, frv-dis.c,
|
|
|
|
|
|
* frv-ibld.c, ip2k-asm.c, ip2k-dis.c, ip2k-ibld.c,
|
|
|
|
|
|
* iq2000-asm.c, iq2000-dis.c, iq2000-ibld.c, m32c-asm.c,
|
|
|
|
|
|
* m32c-dis.c, m32c-ibld.c, m32r-asm.c, m32r-dis.c,
|
|
|
|
|
|
* m32r-ibld.c, mep-asm.c, mep-dis.c, mep-ibld.c, mt-asm.c,
|
|
|
|
|
|
* mt-dis.c, mt-ibld.c, openrisc-asm.c, openrisc-dis.c,
|
|
|
|
|
|
* openrisc-ibld.c, xc16x-asm.c, xc16x-dis.c, xc16x-ibld.c,
|
|
|
|
|
|
* xstormy16-asm.c, xstormy16-dis.c, xstormy16-ibld.c: Regenerate.
|
|
|
|
|
|
|
2009-01-16 16:02:29 +08:00
|
|
|
|
2009-01-16 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in (commonbfdlib): Delete.
|
|
|
|
|
|
(SHARED_LIBADD): Add pic libiberty if such is available.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2009-01-15 12:27:28 +08:00
|
|
|
|
2009-01-14 Peter Bergner <bergner@vnet.ibm.com>
|
|
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* ppc-dis.c (print_insn_powerpc): Skip insn if it is deprecated.
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* ppc-opc.c (powerpc_opcodes) <mtfsf, mtfsf.>: Deprecate the two
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operand form and enable the four operand form for POWER6 and later.
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<mtfsfi, mtfsfi.>: Deprecate the two operand form and enable the
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three operand form for POWER6 and later.
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2009-01-15 03:35:12 +08:00
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2009-01-14 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (OUTS): Use "%s" as format string.
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2009-01-14 08:42:07 +08:00
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2009-01-13 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Remove a white space.
|
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(operand_type_init): Likewise.
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2009-01-13 08:00:35 +08:00
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2009-01-12 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Add NoAVX to movnti, lfence and mfence.
|
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* i386-tbl.h: Regenerated.
|
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gas/testsuite/
2009-01-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/opts.s: Add tests for add, adc, and, cmp, or, sbb,
sub and xor.
* gas/i386/x86-64-opts.s: Likewise.
* gas/i386/opts.d: Updated.
* gas/i386/opts-intel.d: Likewise.
* gas/i386/x86-64-opts.d: Likewise.
* gas/i386/x86-64-opts-intel.d: Likewise.
opcodes/
2009-01-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386): Use EbS on addB, orB, adcB, sbbB, andB,
subB, xorB and cmpB. Use EvS on addS, orS, adcS, sbbS, andS,
subS, xorS and cmpS.
2009-01-13 00:04:11 +08:00
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2009-01-12 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (dis386): Use EbS on addB, orB, adcB, sbbB, andB,
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subB, xorB and cmpB. Use EvS on addS, orS, adcS, sbbS, andS,
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subS, xorS and cmpS.
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gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
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2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
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CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
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CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
|
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(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
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and CpuSYSCALL.
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(lineno): Removed.
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(set_bitfield): Take an argument, lineno. Don't report lineno
|
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on error if it is -1.
|
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(process_i386_cpu_flag): Take an argument, lineno.
|
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(process_i386_opcode_modifier): Likewise.
|
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(process_i386_operand_type): Likewise.
|
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(output_i386_opcode): Likewise.
|
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(opcode_hash_entry): Add lineno.
|
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(process_i386_opcodes): Updated.
|
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(process_i386_registers): Likewise.
|
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(process_i386_initializers): Likewise.
|
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* i386-opc.h (CpuP4): Removed.
|
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(CpuK6): Likewise.
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(CpuK8): Likewise.
|
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(CpuClflush): New.
|
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(CpuSYSCALL): Likewise.
|
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(CpuMMX): Updated.
|
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(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
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cpuclflush and cpusyscall.
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* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
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syscall and sysret.
|
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* i386-init.h: Regenerated.
|
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* i386-tbl.h: Likewise.
|
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2009-01-10 04:32:32 +08:00
|
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2009-01-09 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
|
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and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS.
|
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(cpu_flags): Add CpuRdtscp.
|
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(set_bitfield): Remove CpuSledgehammer check.
|
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* i386-opc.h (CpuRdtscp): New.
|
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(CpuLM): Updated.
|
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(i386_cpu_flags): Add cpurdtscp.
|
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* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
|
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
|
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2009-01-10 02:50:58 +08:00
|
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|
2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
|
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* ppc-opc.c (PPCNONE): Define.
|
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(NOPOWER4): Delete.
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(powerpc_opcodes): Initialize the new "deprecated" field.
|
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2009-01-07 01:15:28 +08:00
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2009-01-06 H.J. Lu <hongjiu.lu@intel.com>
|
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|
AVX Programming Reference (December, 2008)
|
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|
* i386-dis.c (VEX_LEN_2B_M_0): Removed.
|
|
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(VEX_LEN_E7_P_2_M_0): Likewise.
|
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|
(VEX_LEN_2C_P_1): Updated.
|
|
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|
(VEX_LEN_E8_P_2): Likewise.
|
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(vex_len_table): Remove VEX_LEN_2B_M_0 and VEX_LEN_E7_P_2_M_0.
|
|
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(mod_table): Likewise.
|
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* i386-opc.tbl: Add 256bit vmovntdq, vmovntpd and vmovntps.
|
|
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* i386-tbl.h: Regenerated.
|
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2009-01-06 09:14:45 +08:00
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2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
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* i386-gen.c (process_copyright): Update for 2009.
|
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* i386-init.h: Regenerated.
|
|
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* i386-tbl.h: Likewise.
|
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|
2009-01-06 09:03:27 +08:00
|
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|
2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
|
2008-04-24 00:11:47 +08:00
|
|
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|
|
2009-01-06 09:03:27 +08:00
|
|
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|
AVX Programming Reference (December, 2008)
|
|
|
|
|
|
* i386-dis.c (OP_VEX_FMA): Removed.
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
|
|
(OP_EX_VexW): Likewise.
|
2009-01-06 09:03:27 +08:00
|
|
|
|
(OP_EX_VexImmW): Likewise.
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
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|
(OP_XMM_VexW): Likewise.
|
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|
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(VEXI4_Fixup): Likewise.
|
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|
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(VPERMIL2_Fixup): Likewise.
|
|
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(VexI4): Likewise.
|
2009-01-06 09:03:27 +08:00
|
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(VexFMA): Likewise.
|
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(Vex128FMA): Likewise.
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
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|
(EXVexW): Likewise.
|
|
|
|
|
|
(EXdVexW): Likewise.
|
|
|
|
|
|
(EXqVexW): Likewise.
|
2009-01-06 09:03:27 +08:00
|
|
|
|
(EXVexImmW): Likewise.
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
|
|
(XMVexW): Likewise.
|
|
|
|
|
|
(VPERMIL2): Likewise.
|
2009-01-06 09:03:27 +08:00
|
|
|
|
(PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise.
|
|
|
|
|
|
(VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise.
|
|
|
|
|
|
(VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise.
|
|
|
|
|
|
(get_vex_imm8): Likewise.
|
|
|
|
|
|
(OP_EX_VexReg): Likewise.
|
|
|
|
|
|
vpermil2_op): Likewise.
|
|
|
|
|
|
(EXVexWdq): New.
|
|
|
|
|
|
(vex_w_dq_mode): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise.
|
|
|
|
|
|
(es_reg): Updated.
|
|
|
|
|
|
(PREFIX_VEX_38DB): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A4A): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3A60): Likewise.
|
|
|
|
|
|
(PREFIX_VEX_3ADF): Likewise.
|
|
|
|
|
|
(VEX_LEN_3ADF_P_2): Likewise.
|
|
|
|
|
|
(prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A,
|
|
|
|
|
|
PREFIX_VEX_3A5C...PREFIX_VEX_3A5F,
|
|
|
|
|
|
PREFIX_VEX_3A68...PREFIX_VEX_3A6F and
|
|
|
|
|
|
PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add
|
|
|
|
|
|
PREFIX_VEX_3896...PREFIX_VEX_389F,
|
|
|
|
|
|
PREFIX_VEX_38A6...PREFIX_VEX_38AF and
|
|
|
|
|
|
PREFIX_VEX_38B6...PREFIX_VEX_38BF.
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
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(vex_table): Likewise.
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2009-01-06 09:03:27 +08:00
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(vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2
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and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2.
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(putop): Support "%XW".
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(intel_operand_size): Handle vex_w_dq_mode.
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2008-03-18 06:17:33 +08:00
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2009-01-06 09:03:27 +08:00
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* i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS.
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2008-03-18 06:17:33 +08:00
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2009-01-06 09:03:27 +08:00
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* i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA
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instructions. Add new FMA instructions.
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2008-03-02 07:30:51 +08:00
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* i386-tbl.h: Regenerated.
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2009-01-06 09:03:27 +08:00
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2009-01-02 Matthias Klose <doko@ubuntu.com>
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2008-01-02 08:37:44 +08:00
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2009-01-06 09:03:27 +08:00
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* or32-opc.c (or32_print_register, or32_print_immediate,
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disassemble_insn): Don't rely on undefined sprintf behaviour.
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2008-01-02 08:37:44 +08:00
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2009-01-06 09:03:27 +08:00
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For older changes see ChangeLog-2008
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1999-05-03 15:29:11 +08:00
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Local Variables:
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2001-01-12 03:01:42 +08:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 15:29:11 +08:00
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version-control: never
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End:
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