2012-08-13 22:52:54 +08:00
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/* AArch64 assembler/disassembler support.
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2024-01-04 19:52:08 +08:00
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Copyright (C) 2009-2024 Free Software Foundation, Inc.
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2012-08-13 22:52:54 +08:00
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Contributed by ARM Ltd.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the license, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODE_AARCH64_H
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#define OPCODE_AARCH64_H
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#include "bfd.h"
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2021-03-31 07:37:02 +08:00
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#include <stdint.h>
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2012-08-13 22:52:54 +08:00
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#include <assert.h>
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#include <stdlib.h>
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libopcodes/aarch64: add support for disassembler styling
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
2022-04-28 20:31:07 +08:00
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#include "dis-asm.h"
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2015-10-07 19:35:46 +08:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2012-08-13 22:52:54 +08:00
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/* The offset for pc-relative addressing is currently defined to be 0. */
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#define AARCH64_PCREL_OFFSET 0
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typedef uint32_t aarch64_insn;
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aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
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/* An enum containing all known CPU features. The values act as bit positions
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into aarch64_feature_set. */
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enum aarch64_feature_bit {
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/* All processors. */
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AARCH64_FEATURE_V8,
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/* ARMv8.6 processors. */
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AARCH64_FEATURE_V8_6A,
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/* Bfloat16 insns. */
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AARCH64_FEATURE_BFLOAT16,
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/* Armv8-A processors. */
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AARCH64_FEATURE_V8A,
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/* SVE2 instructions. */
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AARCH64_FEATURE_SVE2,
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/* ARMv8.2 processors. */
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AARCH64_FEATURE_V8_2A,
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/* ARMv8.3 processors. */
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AARCH64_FEATURE_V8_3A,
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AARCH64_FEATURE_SVE2_AES,
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AARCH64_FEATURE_SVE2_BITPERM,
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AARCH64_FEATURE_SVE2_SM4,
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AARCH64_FEATURE_SVE2_SHA3,
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/* ARMv8.4 processors. */
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AARCH64_FEATURE_V8_4A,
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/* Armv8-R processors. */
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AARCH64_FEATURE_V8R,
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/* Armv8.7 processors. */
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AARCH64_FEATURE_V8_7A,
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/* Scalable Matrix Extension. */
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AARCH64_FEATURE_SME,
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/* Atomic 64-byte load/store. */
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AARCH64_FEATURE_LS64,
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/* v8.3 Pointer Authentication. */
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2024-02-23 22:52:58 +08:00
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AARCH64_FEATURE_PAUTH,
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aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
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/* FP instructions. */
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AARCH64_FEATURE_FP,
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/* SIMD instructions. */
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AARCH64_FEATURE_SIMD,
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/* CRC instructions. */
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AARCH64_FEATURE_CRC,
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/* LSE instructions. */
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AARCH64_FEATURE_LSE,
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/* PAN instructions. */
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AARCH64_FEATURE_PAN,
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/* LOR instructions. */
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AARCH64_FEATURE_LOR,
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/* v8.1 SIMD instructions. */
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AARCH64_FEATURE_RDMA,
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/* v8.1 features. */
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AARCH64_FEATURE_V8_1A,
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/* v8.2 FP16 instructions. */
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AARCH64_FEATURE_F16,
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/* RAS Extensions. */
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AARCH64_FEATURE_RAS,
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/* Statistical Profiling. */
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AARCH64_FEATURE_PROFILE,
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/* SVE instructions. */
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AARCH64_FEATURE_SVE,
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/* RCPC instructions. */
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AARCH64_FEATURE_RCPC,
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2024-01-12 09:44:10 +08:00
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/* RCPC2 instructions. */
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AARCH64_FEATURE_RCPC2,
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aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
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/* Complex # instructions. */
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AARCH64_FEATURE_COMPNUM,
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2024-01-12 09:42:36 +08:00
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/* JavaScript conversion instructions. */
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AARCH64_FEATURE_JSCVT,
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aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
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/* Dot Product instructions. */
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AARCH64_FEATURE_DOTPROD,
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/* SM3 & SM4 instructions. */
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AARCH64_FEATURE_SM4,
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/* SHA2 instructions. */
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AARCH64_FEATURE_SHA2,
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/* SHA3 instructions. */
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AARCH64_FEATURE_SHA3,
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/* AES instructions. */
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AARCH64_FEATURE_AES,
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/* v8.2 FP16FML ins. */
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AARCH64_FEATURE_F16_FML,
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/* ARMv8.5 processors. */
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AARCH64_FEATURE_V8_5A,
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/* v8.5 Flag Manipulation version 2. */
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AARCH64_FEATURE_FLAGMANIP,
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/* FRINT[32,64][Z,X] insns. */
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AARCH64_FEATURE_FRINTTS,
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/* SB instruction. */
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AARCH64_FEATURE_SB,
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/* Execution and Data Prediction Restriction instructions. */
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AARCH64_FEATURE_PREDRES,
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/* DC CVADP. */
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AARCH64_FEATURE_CVADP,
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/* Random Number instructions. */
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AARCH64_FEATURE_RNG,
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/* SCXTNUM_ELx. */
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AARCH64_FEATURE_SCXTNUM,
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/* ID_PFR2 instructions. */
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AARCH64_FEATURE_ID_PFR2,
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/* SSBS mechanism enabled. */
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AARCH64_FEATURE_SSBS,
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/* Memory Tagging Extension. */
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AARCH64_FEATURE_MEMTAG,
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/* Transactional Memory Extension. */
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AARCH64_FEATURE_TME,
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2024-01-12 09:45:25 +08:00
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/* XS memory attribute. */
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AARCH64_FEATURE_XS,
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2024-01-12 09:44:46 +08:00
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/* WFx instructions with timeout. */
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AARCH64_FEATURE_WFXT,
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aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
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/* Standardization of memory operations. */
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AARCH64_FEATURE_MOPS,
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/* Hinted conditional branches. */
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AARCH64_FEATURE_HBC,
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/* Matrix Multiply instructions. */
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AARCH64_FEATURE_I8MM,
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AARCH64_FEATURE_F32MM,
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AARCH64_FEATURE_F64MM,
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/* v8.4 Flag Manipulation. */
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AARCH64_FEATURE_FLAGM,
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/* Armv9.0-A processors. */
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AARCH64_FEATURE_V9A,
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/* SME F64F64. */
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AARCH64_FEATURE_SME_F64F64,
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/* SME I16I64. */
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AARCH64_FEATURE_SME_I16I64,
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/* Armv8.8 processors. */
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AARCH64_FEATURE_V8_8A,
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/* Common Short Sequence Compression instructions. */
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AARCH64_FEATURE_CSSC,
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2023-11-02 20:40:29 +08:00
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/* Armv8.9-A processors. */
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AARCH64_FEATURE_V8_9A,
|
2023-11-02 20:44:13 +08:00
|
|
|
|
/* Check Feature Status Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_CHK,
|
2023-11-02 21:04:20 +08:00
|
|
|
|
/* Guarded Control Stack. */
|
|
|
|
|
|
AARCH64_FEATURE_GCS,
|
2023-11-16 20:16:53 +08:00
|
|
|
|
/* SPE Call Return branch records. */
|
|
|
|
|
|
AARCH64_FEATURE_SPE_CRR,
|
|
|
|
|
|
/* SPE Filter by data source. */
|
|
|
|
|
|
AARCH64_FEATURE_SPE_FDS,
|
|
|
|
|
|
/* Additional SPE events. */
|
|
|
|
|
|
AARCH64_FEATURE_SPEv1p4,
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
/* SME2. */
|
2023-09-26 22:01:21 +08:00
|
|
|
|
AARCH64_FEATURE_SME2,
|
2023-11-01 21:44:45 +08:00
|
|
|
|
/* Translation Hardening Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_THE,
|
2023-10-30 20:39:28 +08:00
|
|
|
|
/* LSE128. */
|
|
|
|
|
|
AARCH64_FEATURE_LSE128,
|
2023-11-16 20:18:28 +08:00
|
|
|
|
/* ARMv8.9-A RAS Extensions. */
|
|
|
|
|
|
AARCH64_FEATURE_RASv2,
|
2024-06-20 03:08:17 +08:00
|
|
|
|
/* Delegated SError exceptions for EL3. */
|
|
|
|
|
|
AARCH64_FEATURE_E3DSE,
|
2023-11-16 20:18:28 +08:00
|
|
|
|
/* System Control Register2. */
|
|
|
|
|
|
AARCH64_FEATURE_SCTLR2,
|
|
|
|
|
|
/* Fine Grained Traps. */
|
|
|
|
|
|
AARCH64_FEATURE_FGT2,
|
|
|
|
|
|
/* Physical Fault Address. */
|
|
|
|
|
|
AARCH64_FEATURE_PFAR,
|
2023-11-16 22:24:27 +08:00
|
|
|
|
/* Address Translate Stage 1. */
|
|
|
|
|
|
AARCH64_FEATURE_ATS1A,
|
2023-11-16 22:27:25 +08:00
|
|
|
|
/* Memory Attribute Index Enhancement. */
|
|
|
|
|
|
AARCH64_FEATURE_AIE,
|
|
|
|
|
|
/* Stage 1 Permission Indirection Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_S1PIE,
|
|
|
|
|
|
/* Stage 2 Permission Indirection Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_S2PIE,
|
|
|
|
|
|
/* Stage 1 Permission Overlay Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_S1POE,
|
|
|
|
|
|
/* Stage 2 Permission Overlay Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_S2POE,
|
|
|
|
|
|
/* Extension to Translation Control Registers. */
|
|
|
|
|
|
AARCH64_FEATURE_TCR2,
|
2023-09-06 22:52:45 +08:00
|
|
|
|
/* Speculation Prediction Restriction instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_PREDRES2,
|
2023-10-10 23:37:11 +08:00
|
|
|
|
/* Instrumentation Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_ITE,
|
2023-11-15 20:21:33 +08:00
|
|
|
|
/* 128-bit page table descriptor, system registers
|
|
|
|
|
|
and isntructions. */
|
|
|
|
|
|
AARCH64_FEATURE_D128,
|
2024-01-10 19:10:07 +08:00
|
|
|
|
/* Armv8.9-A/Armv9.4-A architecture Debug extension. */
|
|
|
|
|
|
AARCH64_FEATURE_DEBUGv8p9,
|
|
|
|
|
|
/* Performance Monitors Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_PMUv3p9,
|
|
|
|
|
|
/* Performance Monitors Snapshots Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_PMUv3_SS,
|
|
|
|
|
|
/* Performance Monitors Instruction Counter Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_PMUv3_ICNTR,
|
2024-05-16 19:36:14 +08:00
|
|
|
|
/* System Performance Monitors Extension */
|
|
|
|
|
|
AARCH64_FEATURE_SPMU,
|
2024-06-20 03:10:22 +08:00
|
|
|
|
/* System Performance Monitors Extension version 2 */
|
|
|
|
|
|
AARCH64_FEATURE_SPMU2,
|
2024-01-10 19:10:07 +08:00
|
|
|
|
/* Performance Monitors Synchronous-Exception-Based Event Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_SEBEP,
|
aarch64: Add support for FEAT_B16B16 instructions.
Hi,
This patch add support for SVE2.1 and SME2.1 non-widening BFloat16
(FEAT_B16B16) instructions.
Following instructions predicated, unpredicated and indexed
variants are added in this patch.
bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm,
bfmla,bfmls,bfmul and bfsub.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
2024-01-15 17:28:28 +08:00
|
|
|
|
/* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_B16B16,
|
2024-01-15 17:34:41 +08:00
|
|
|
|
/* SME2.1 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SME2p1,
|
2024-01-15 17:35:55 +08:00
|
|
|
|
/* SVE2.1 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SVE2p1,
|
2024-01-04 21:34:52 +08:00
|
|
|
|
/* RCPC3 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_RCPC3,
|
2024-07-04 01:36:26 +08:00
|
|
|
|
/* Enhanced Software Step Extension. */
|
|
|
|
|
|
AARCH64_FEATURE_STEP2,
|
2024-02-21 20:52:23 +08:00
|
|
|
|
/* Checked Pointer Arithmetic instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_CPA,
|
2024-03-19 23:41:41 +08:00
|
|
|
|
/* FAMINMAX instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_FAMINMAX,
|
2024-02-29 21:35:26 +08:00
|
|
|
|
/* FP8 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_FP8,
|
2024-05-28 22:45:50 +08:00
|
|
|
|
/* LUT instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_LUT,
|
2024-06-07 21:59:02 +08:00
|
|
|
|
/* Branch Record Buffer Extension */
|
|
|
|
|
|
AARCH64_FEATURE_BRBE,
|
2024-06-21 23:30:59 +08:00
|
|
|
|
/* SME LUTv2 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SME_LUTv2,
|
2024-06-22 02:31:34 +08:00
|
|
|
|
/* FP8FMA instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_FP8FMA,
|
|
|
|
|
|
/* FP8DOT4 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_FP8DOT4,
|
|
|
|
|
|
/* FP8DOT2 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_FP8DOT2,
|
|
|
|
|
|
/* SSVE FP8FMA instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SSVE_FP8FMA,
|
|
|
|
|
|
/* SSVE FP8DOT4 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SSVE_FP8DOT4,
|
|
|
|
|
|
/* SSVE FP8DOT2 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SSVE_FP8DOT2,
|
2024-06-22 02:32:31 +08:00
|
|
|
|
/* SME F8F32 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SME_F8F32,
|
|
|
|
|
|
/* SME F8F16 instructions. */
|
|
|
|
|
|
AARCH64_FEATURE_SME_F8F16,
|
2024-06-22 02:31:34 +08:00
|
|
|
|
|
|
|
|
|
|
/* Virtual features. These are used to gate instructions that are enabled
|
|
|
|
|
|
by either of two (or more) sets of command line flags. */
|
|
|
|
|
|
/* +fp8fma+sve or +ssve-fp8fma */
|
|
|
|
|
|
AARCH64_FEATURE_FP8FMA_SVE,
|
|
|
|
|
|
/* +fp8dot4+sve or +ssve-fp8dot4 */
|
|
|
|
|
|
AARCH64_FEATURE_FP8DOT4_SVE,
|
|
|
|
|
|
/* +fp8dot2+sve or +ssve-fp8dot2 */
|
|
|
|
|
|
AARCH64_FEATURE_FP8DOT2_SVE,
|
2024-06-22 02:32:31 +08:00
|
|
|
|
/* +sme-f16f16 or +sme-f8f16 */
|
|
|
|
|
|
AARCH64_FEATURE_SME_F16F16_F8F16,
|
2024-06-10 21:18:52 +08:00
|
|
|
|
/* Armv9.5-A processors. */
|
|
|
|
|
|
AARCH64_FEATURE_V9_5A,
|
2023-09-26 22:01:21 +08:00
|
|
|
|
AARCH64_NUM_FEATURES
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* These macros take an initial argument X that gives the index into
|
|
|
|
|
|
an aarch64_feature_set. The macros then return the bitmask for
|
|
|
|
|
|
that array index. */
|
|
|
|
|
|
|
|
|
|
|
|
/* A mask in which feature bit BIT is set and all other bits are clear. */
|
|
|
|
|
|
#define AARCH64_UINT64_BIT(X, BIT) \
|
|
|
|
|
|
((X) == (BIT) / 64 ? 1ULL << (BIT) % 64 : 0)
|
|
|
|
|
|
|
|
|
|
|
|
/* A mask that includes only AARCH64_FEATURE_<NAME>. */
|
|
|
|
|
|
#define AARCH64_FEATBIT(X, NAME) \
|
|
|
|
|
|
AARCH64_UINT64_BIT (X, AARCH64_FEATURE_##NAME)
|
|
|
|
|
|
|
|
|
|
|
|
/* A mask of the features that are enabled by each architecture version,
|
|
|
|
|
|
excluding those that are inherited from other architecture versions. */
|
|
|
|
|
|
#define AARCH64_ARCH_V8A_FEATURES(X) (AARCH64_FEATBIT (X, V8A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, FP) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, RAS) \
|
2023-11-02 20:44:13 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, SIMD) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, CHK))
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_ARCH_V8_1A_FEATURES(X) (AARCH64_FEATBIT (X, V8_1A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, CRC) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, LSE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, PAN) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, LOR) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, RDMA))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_2A_FEATURES(X) (AARCH64_FEATBIT (X, V8_2A))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_3A_FEATURES(X) (AARCH64_FEATBIT (X, V8_3A) \
|
2024-02-23 22:52:58 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, PAUTH) \
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, RCPC) \
|
2024-01-12 09:42:36 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, COMPNUM) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, JSCVT))
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \
|
2024-01-12 09:44:10 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, RCPC2) \
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, DOTPROD) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, FLAGM) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, F16_FML))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_5A_FEATURES(X) (AARCH64_FEATBIT (X, V8_5A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, FLAGMANIP) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, FRINTTS) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SB) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, PREDRES) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, CVADP) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SCXTNUM) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, ID_PFR2) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SSBS))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_6A_FEATURES(X) (AARCH64_FEATBIT (X, V8_6A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, BFLOAT16) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, I8MM))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_7A_FEATURES(X) (AARCH64_FEATBIT (X, V8_7A) \
|
2024-01-12 09:45:25 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, XS) \
|
2024-01-12 09:44:46 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, WFXT) \
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, LS64))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_8A_FEATURES(X) (AARCH64_FEATBIT (X, V8_8A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, MOPS) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, HBC))
|
2023-11-16 20:16:53 +08:00
|
|
|
|
#define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A) \
|
2024-04-12 20:35:00 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, CSSC) \
|
2023-11-16 20:16:53 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, SPEv1p4) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SPE_CRR) \
|
2023-11-16 20:18:28 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, SPE_FDS) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, RASv2) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SCTLR2) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, FGT2) \
|
2023-11-16 22:24:27 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, PFAR) \
|
2023-11-16 22:27:25 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, ATS1A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, AIE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, S1PIE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, S2PIE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, S1POE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, S2POE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, TCR2) \
|
2024-01-10 19:10:07 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, DEBUGv8p9) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, PMUv3p9) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, PMUv3_SS) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, PMUv3_ICNTR) \
|
2024-05-16 19:36:14 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, SPMU) \
|
2024-01-10 19:10:07 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, SEBEP) \
|
2024-01-17 20:37:15 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, PREDRES2) \
|
2023-11-16 22:27:25 +08:00
|
|
|
|
)
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, F16) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SVE) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SVE2))
|
|
|
|
|
|
#define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X)
|
|
|
|
|
|
#define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X)
|
|
|
|
|
|
#define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X)
|
2024-06-25 18:25:26 +08:00
|
|
|
|
#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, SVE2p1))
|
2024-06-10 21:18:52 +08:00
|
|
|
|
#define AARCH64_ARCH_V9_5A_FEATURES(X) (AARCH64_FEATBIT (X, V9_5A) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, CPA) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, LUT) \
|
2024-06-20 03:08:17 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, FAMINMAX)\
|
|
|
|
|
|
| AARCH64_FEATBIT (X, E3DSE) \
|
2024-06-20 03:10:22 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, SPMU2) \
|
2024-07-04 01:36:26 +08:00
|
|
|
|
| AARCH64_FEATBIT (X, STEP2) \
|
2024-06-20 03:08:17 +08:00
|
|
|
|
)
|
aarch64: Add support for Armv9.1-A to Armv9.3-A
This patch adds AArch64 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags, so we don't need to
eat into the vanishing number of spare AARCH64_FEATURE_* bits.
Hoewver, it was more convenient to separate out the |s of
feature flags so that Armv9.1-A could reuse the set for
Armv8.6-A, and so on.
include/
* opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro,
split out from...
(AARCH64_ARCH_V8): ...here.
(AARCH64_ARCH_V8_1_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_1): ...here.
(AARCH64_ARCH_V8_2_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_2): ...here.
(AARCH64_ARCH_V8_3_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_3): ...here.
(AARCH64_ARCH_V8_4_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_4): ...here.
(AARCH64_ARCH_V8_5_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_5): ...here.
(AARCH64_ARCH_V8_6_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_6): ...here.
(AARCH64_ARCH_V8_7_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_7): ...here.
(AARCH64_ARCH_V8_8_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_8): ...here.
(AARCH64_ARCH_V9_FEATURES): New macro, split out from...
(AARCH64_ARCH_V9): ...here.
(AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros.
(AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros.
(AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros.
gas/
* doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a.
* config/tc-aarch64.c (aarch64_archs): Likewise.
* NEWS: Mention the above.
* testsuite/gas/aarch64/armv9_invalid.d,
testsuite/gas/aarch64/armv9_invalid.s,
testsuite/gas/aarch64/armv9_invalid.l: New test.
* testsuite/gas/aarch64/armv9_1.d,
testsuite/gas/aarch64/armv9_1.s: Likewise.
* testsuite/gas/aarch64/armv9_1_invalid.d,
testsuite/gas/aarch64/armv9_1_invalid.s,
testsuite/gas/aarch64/armv9_1_invalid.l: Likewise.
* testsuite/gas/aarch64/armv9_2.d,
testsuite/gas/aarch64/armv9_2.s: Likewise.
* testsuite/gas/aarch64/armv9_2_invalid.d,
testsuite/gas/aarch64/armv9_2_invalid.s,
testsuite/gas/aarch64/armv9_2_invalid.l: Likewise.
* testsuite/gas/aarch64/armv9_3.d,
testsuite/gas/aarch64/armv9_3.s: Likewise.
2021-12-16 17:32:00 +08:00
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* Architectures are the sum of the base and extensions. */
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \
|
|
|
|
|
|
| AARCH64_ARCH_V8A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_1A(X) (AARCH64_ARCH_V8A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_1A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_2A(X) (AARCH64_ARCH_V8_1A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_2A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_3A(X) (AARCH64_ARCH_V8_2A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_3A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_4A(X) (AARCH64_ARCH_V8_3A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_4A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_5A(X) (AARCH64_ARCH_V8_4A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_5A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_6A(X) (AARCH64_ARCH_V8_5A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_6A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_7A(X) (AARCH64_ARCH_V8_6A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_7A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V8_8A(X) (AARCH64_ARCH_V8_7A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_8A_FEATURES (X))
|
2023-11-02 20:40:29 +08:00
|
|
|
|
#define AARCH64_ARCH_V8_9A(X) (AARCH64_ARCH_V8_8A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V8_9A_FEATURES (X))
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_ARCH_V8R(X) ((AARCH64_ARCH_V8_4A (X) \
|
|
|
|
|
|
| AARCH64_FEATBIT (X, V8R)) \
|
|
|
|
|
|
& ~AARCH64_FEATBIT (X, V8A) \
|
|
|
|
|
|
& ~AARCH64_FEATBIT (X, LOR))
|
|
|
|
|
|
|
|
|
|
|
|
#define AARCH64_ARCH_V9A(X) (AARCH64_ARCH_V8_5A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V9A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V9_1A(X) (AARCH64_ARCH_V9A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V9_1A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V9_2A(X) (AARCH64_ARCH_V9_1A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V9_2A_FEATURES (X))
|
|
|
|
|
|
#define AARCH64_ARCH_V9_3A(X) (AARCH64_ARCH_V9_2A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V9_3A_FEATURES (X))
|
2023-11-02 20:40:29 +08:00
|
|
|
|
#define AARCH64_ARCH_V9_4A(X) (AARCH64_ARCH_V9_3A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V9_4A_FEATURES (X))
|
2024-06-10 21:18:52 +08:00
|
|
|
|
#define AARCH64_ARCH_V9_5A(X) (AARCH64_ARCH_V9_4A (X) \
|
|
|
|
|
|
| AARCH64_ARCH_V9_5A_FEATURES (X))
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
#define AARCH64_ARCH_NONE(X) 0
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
/* CPU-specific features. */
|
2023-09-26 22:01:21 +08:00
|
|
|
|
typedef struct {
|
|
|
|
|
|
uint64_t flags[(AARCH64_NUM_FEATURES + 63) / 64];
|
|
|
|
|
|
} aarch64_feature_set;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
|
2023-09-26 22:01:21 +08:00
|
|
|
|
((~(CPU).flags[0] & AARCH64_FEATBIT (0, FEAT)) == 0 \
|
|
|
|
|
|
&& (~(CPU).flags[1] & AARCH64_FEATBIT (1, FEAT)) == 0)
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
2016-07-01 23:20:50 +08:00
|
|
|
|
#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
|
2023-09-26 22:01:21 +08:00
|
|
|
|
((~(CPU).flags[0] & (FEAT).flags[0]) == 0 \
|
|
|
|
|
|
&& (~(CPU).flags[1] & (FEAT).flags[1]) == 0)
|
2016-07-01 23:20:50 +08:00
|
|
|
|
|
|
|
|
|
|
#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
|
2023-09-26 22:01:21 +08:00
|
|
|
|
(((CPU).flags[0] & (FEAT).flags[0]) != 0 \
|
|
|
|
|
|
|| ((CPU).flags[1] & (FEAT).flags[1]) != 0)
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_SET_FEATURE(DEST, FEAT) \
|
2023-09-26 22:01:21 +08:00
|
|
|
|
((DEST).flags[0] = FEAT (0), \
|
|
|
|
|
|
(DEST).flags[1] = FEAT (1))
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
#define AARCH64_CLEAR_FEATURE(DEST, SRC, FEAT) \
|
2023-09-26 22:01:21 +08:00
|
|
|
|
((DEST).flags[0] = (SRC).flags[0] & ~AARCH64_FEATBIT (0, FEAT), \
|
|
|
|
|
|
(DEST).flags[1] = (SRC).flags[1] & ~AARCH64_FEATBIT (1, FEAT))
|
|
|
|
|
|
|
|
|
|
|
|
#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
|
|
|
|
|
|
do \
|
|
|
|
|
|
{ \
|
|
|
|
|
|
(TARG).flags[0] = (F1).flags[0] | (F2).flags[0]; \
|
|
|
|
|
|
(TARG).flags[1] = (F1).flags[1] | (F2).flags[1]; \
|
|
|
|
|
|
} \
|
2012-08-13 22:52:54 +08:00
|
|
|
|
while (0)
|
|
|
|
|
|
|
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_CLEAR_FEATURES(TARG,F1,F2) \
|
|
|
|
|
|
do \
|
|
|
|
|
|
{ \
|
|
|
|
|
|
(TARG).flags[0] = (F1).flags[0] &~ (F2).flags[0]; \
|
|
|
|
|
|
(TARG).flags[1] = (F1).flags[1] &~ (F2).flags[1]; \
|
|
|
|
|
|
} \
|
2012-08-13 22:52:54 +08:00
|
|
|
|
while (0)
|
|
|
|
|
|
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
/* aarch64_feature_set initializers for no features and all features,
|
|
|
|
|
|
respectively. */
|
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_NO_FEATURES { { 0, 0 } }
|
|
|
|
|
|
#define AARCH64_ALL_FEATURES { { -1, -1 } }
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
/* An aarch64_feature_set initializer for a single feature,
|
|
|
|
|
|
AARCH64_FEATURE_<FEAT>. */
|
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_FEATURE(FEAT) \
|
|
|
|
|
|
{ { AARCH64_FEATBIT (0, FEAT), AARCH64_FEATBIT (1, FEAT) } }
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
/* An aarch64_feature_set initializer for a specific architecture version,
|
|
|
|
|
|
including all the features that are enabled by default for that architecture
|
|
|
|
|
|
version. */
|
2023-09-26 22:01:21 +08:00
|
|
|
|
#define AARCH64_ARCH_FEATURES(ARCH) \
|
|
|
|
|
|
{ { AARCH64_ARCH_##ARCH (0), AARCH64_ARCH_##ARCH (1) } }
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
/* Used by AARCH64_CPU_FEATURES. */
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_1(X, ARCH, F1) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_ARCH_##ARCH (X))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_2(X, ARCH, F1, F2) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_1 (X, ARCH, F2))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_3(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_2 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_4(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_3 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_5(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_4 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_6(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_5 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_7(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_6 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_8(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_7 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
#define AARCH64_OR_FEATURES_9(X, ARCH, F1, ...) \
|
|
|
|
|
|
(AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_8 (X, ARCH, __VA_ARGS__))
|
|
|
|
|
|
|
|
|
|
|
|
/* An aarch64_feature_set initializer for a CPU that implements architecture
|
|
|
|
|
|
version ARCH, and additionally provides the N features listed in "...". */
|
|
|
|
|
|
#define AARCH64_CPU_FEATURES(ARCH, N, ...) \
|
2023-09-26 22:01:21 +08:00
|
|
|
|
{ { AARCH64_OR_FEATURES_##N (0, ARCH, __VA_ARGS__), \
|
|
|
|
|
|
AARCH64_OR_FEATURES_##N (1, ARCH, __VA_ARGS__) } }
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
|
|
|
|
|
|
/* An aarch64_feature_set initializer for the N features listed in "...". */
|
|
|
|
|
|
#define AARCH64_FEATURES(N, ...) \
|
|
|
|
|
|
AARCH64_CPU_FEATURES (NONE, N, __VA_ARGS__)
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
enum aarch64_operand_class
|
|
|
|
|
|
{
|
|
|
|
|
|
AARCH64_OPND_CLASS_NIL,
|
|
|
|
|
|
AARCH64_OPND_CLASS_INT_REG,
|
|
|
|
|
|
AARCH64_OPND_CLASS_MODIFIED_REG,
|
|
|
|
|
|
AARCH64_OPND_CLASS_FP_REG,
|
|
|
|
|
|
AARCH64_OPND_CLASS_SIMD_REG,
|
|
|
|
|
|
AARCH64_OPND_CLASS_SIMD_ELEMENT,
|
|
|
|
|
|
AARCH64_OPND_CLASS_SISD_REG,
|
|
|
|
|
|
AARCH64_OPND_CLASS_SIMD_REGLIST,
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
AARCH64_OPND_CLASS_SVE_REG,
|
2023-03-30 18:09:07 +08:00
|
|
|
|
AARCH64_OPND_CLASS_SVE_REGLIST,
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
AARCH64_OPND_CLASS_PRED_REG,
|
2023-03-30 18:09:05 +08:00
|
|
|
|
AARCH64_OPND_CLASS_ZA_ACCESS,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_CLASS_ADDRESS,
|
|
|
|
|
|
AARCH64_OPND_CLASS_IMMEDIATE,
|
|
|
|
|
|
AARCH64_OPND_CLASS_SYSTEM,
|
2013-11-06 04:50:18 +08:00
|
|
|
|
AARCH64_OPND_CLASS_COND,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* Operand code that helps both parsing and coding.
|
|
|
|
|
|
Keep AARCH64_OPERANDS synced. */
|
|
|
|
|
|
|
|
|
|
|
|
enum aarch64_opnd
|
|
|
|
|
|
{
|
|
|
|
|
|
AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_Rd, /* Integer register as destination. */
|
|
|
|
|
|
AARCH64_OPND_Rn, /* Integer register as source. */
|
|
|
|
|
|
AARCH64_OPND_Rm, /* Integer register as source. */
|
|
|
|
|
|
AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
|
|
|
|
|
|
AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
|
2023-11-02 20:44:13 +08:00
|
|
|
|
AARCH64_OPND_X16, /* Integer register x16 in chkfeat instruction. */
|
2020-11-09 19:09:12 +08:00
|
|
|
|
AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */
|
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2019-04-11 17:19:37 +08:00
|
|
|
|
AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
|
|
|
|
|
|
AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
|
|
|
|
|
|
AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
|
|
|
|
|
|
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
|
2016-11-11 18:39:46 +08:00
|
|
|
|
AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
|
2014-09-03 21:40:41 +08:00
|
|
|
|
AARCH64_OPND_PAIRREG, /* Paired register operand. */
|
2023-12-13 22:09:08 +08:00
|
|
|
|
AARCH64_OPND_PAIRREG_OR_XZR, /* Paired register operand, optionally xzr. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
|
|
|
|
|
|
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
|
2024-02-21 20:52:23 +08:00
|
|
|
|
AARCH64_OPND_Rm_LSL, /* Integer Rm shifted (LSL-only). */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_Fd, /* Floating-point Fd. */
|
|
|
|
|
|
AARCH64_OPND_Fn, /* Floating-point Fn. */
|
|
|
|
|
|
AARCH64_OPND_Fm, /* Floating-point Fm. */
|
|
|
|
|
|
AARCH64_OPND_Fa, /* Floating-point Fa. */
|
|
|
|
|
|
AARCH64_OPND_Ft, /* Floating-point Ft. */
|
|
|
|
|
|
AARCH64_OPND_Ft2, /* Floating-point Ft2. */
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
|
|
|
|
|
|
AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
|
|
|
|
|
|
AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
|
|
|
|
|
|
|
Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
* config/tc-aarch64.c (process_omitted_operand):
Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
and AARCH64_OPND_IMM_2.
(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
and AARCH64_OPND_ADDR_OFFSET.
include/
* opcode/aarch64.h:
(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
and AARCH64_OPND_SM3_IMM2.
(aarch64_insn_class): Add cryptosm3 and cryptosm4.
(arch64_feature_set): Make uint64_t.
opcodes/
* aarch64-asm.h (ins_addr_offset): New.
* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
(aarch64_ins_addr_offset): New.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_addr_offset): New.
* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
(aarch64_ext_addr_offset): New.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
* aarch64-opc.c (fields): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
* aarch64-tbl.h
(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 23:22:30 +08:00
|
|
|
|
AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
|
|
|
|
|
|
AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
|
|
|
|
|
|
AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
|
|
|
|
|
|
AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
|
|
|
|
|
|
AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
|
|
|
|
|
|
AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
|
|
|
|
|
|
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
|
|
|
|
|
|
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
|
Fix AArch64 encodings for by element instructions.
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.
e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.
Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.
This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).
Also the patch updates all instructions that should be affected by this.
opcodes/
PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.
gas/
PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
include/
PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-06-29 19:12:27 +08:00
|
|
|
|
AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
|
2024-06-22 02:31:34 +08:00
|
|
|
|
qualifier is S_H or S_2B. */
|
|
|
|
|
|
AARCH64_OPND_Em8, /* AdvSIMD Vector Element Vm restricted to V0 - V7,
|
|
|
|
|
|
used only with qualifier S_B. */
|
2024-05-28 22:45:50 +08:00
|
|
|
|
AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */
|
|
|
|
|
|
AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */
|
|
|
|
|
|
AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
|
|
|
|
|
|
AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
|
|
|
|
|
|
AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
|
|
|
|
|
|
structure to all lanes. */
|
2024-05-28 22:45:50 +08:00
|
|
|
|
AARCH64_OPND_LVn_LUT, /* AdvSIMD Vector register list used in lut. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
|
|
|
|
|
|
|
2016-12-13 20:37:18 +08:00
|
|
|
|
AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
|
|
|
|
|
|
AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
|
Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
* config/tc-aarch64.c (process_omitted_operand):
Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
and AARCH64_OPND_IMM_2.
(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
and AARCH64_OPND_ADDR_OFFSET.
include/
* opcode/aarch64.h:
(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
and AARCH64_OPND_SM3_IMM2.
(aarch64_insn_class): Add cryptosm3 and cryptosm4.
(arch64_feature_set): Make uint64_t.
opcodes/
* aarch64-asm.h (ins_addr_offset): New.
* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
(aarch64_ins_addr_offset): New.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_addr_offset): New.
* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
(aarch64_ext_addr_offset): New.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
* aarch64-opc.c (fields): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
* aarch64-tbl.h
(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 23:22:30 +08:00
|
|
|
|
AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
|
|
|
|
|
|
AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
|
|
|
|
|
|
AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
|
|
|
|
|
|
AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
|
|
|
|
|
|
AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
|
|
|
|
|
|
AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
|
|
|
|
|
|
(no encoding). */
|
|
|
|
|
|
AARCH64_OPND_IMM0, /* Immediate for #0. */
|
|
|
|
|
|
AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
|
|
|
|
|
|
AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
|
|
|
|
|
|
AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
|
|
|
|
|
|
AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
|
|
|
|
|
|
AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
|
|
|
|
|
|
AARCH64_OPND_IMM, /* Immediate. */
|
Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
* config/tc-aarch64.c (process_omitted_operand):
Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
and AARCH64_OPND_IMM_2.
(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
and AARCH64_OPND_ADDR_OFFSET.
include/
* opcode/aarch64.h:
(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
and AARCH64_OPND_SM3_IMM2.
(aarch64_insn_class): Add cryptosm3 and cryptosm4.
(arch64_feature_set): Make uint64_t.
opcodes/
* aarch64-asm.h (ins_addr_offset): New.
* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
(aarch64_ins_addr_offset): New.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_addr_offset): New.
* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
(aarch64_ext_addr_offset): New.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
* aarch64-opc.c (fields): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
* aarch64-tbl.h
(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 23:22:30 +08:00
|
|
|
|
AARCH64_OPND_IMM_2, /* Immediate. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
|
|
|
|
|
|
AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
|
|
|
|
|
|
AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
|
[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12 20:52:55 +08:00
|
|
|
|
AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
|
[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12 20:52:55 +08:00
|
|
|
|
AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_BIT_NUM, /* Immediate. */
|
|
|
|
|
|
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
|
2020-04-30 22:47:30 +08:00
|
|
|
|
AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
|
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
|
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|
|
AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
|
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|
|
|
each condition flag. */
|
|
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AARCH64_OPND_LIMM, /* Logical Immediate. */
|
|
|
|
|
|
AARCH64_OPND_AIMM, /* Arithmetic immediate. */
|
|
|
|
|
|
AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
|
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|
|
AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
|
|
|
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|
|
AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
|
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 18:02:16 +08:00
|
|
|
|
AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
|
|
|
|
|
|
AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
|
|
|
|
|
|
AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_COND, /* Standard condition as the last operand. */
|
2013-11-06 04:50:18 +08:00
|
|
|
|
AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
|
|
|
|
|
|
AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
|
|
|
|
|
|
AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
|
|
|
|
|
|
negative or unaligned and there is
|
|
|
|
|
|
no writeback allowed. This operand code
|
|
|
|
|
|
is only used to support the programmer-
|
|
|
|
|
|
friendly feature of using LDR/STR as the
|
|
|
|
|
|
the mnemonic name for LDUR/STUR instructions
|
|
|
|
|
|
wherever there is no ambiguity. */
|
2016-11-18 17:49:06 +08:00
|
|
|
|
AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
|
[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 21:09:55 +08:00
|
|
|
|
AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
|
|
|
|
|
|
16) immediate. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
|
[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 21:09:55 +08:00
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AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
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16) immediate. */
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2012-08-13 22:52:54 +08:00
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AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
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Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
* config/tc-aarch64.c (process_omitted_operand):
Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
and AARCH64_OPND_IMM_2.
(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
and AARCH64_OPND_ADDR_OFFSET.
include/
* opcode/aarch64.h:
(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
and AARCH64_OPND_SM3_IMM2.
(aarch64_insn_class): Add cryptosm3 and cryptosm4.
(arch64_feature_set): Make uint64_t.
opcodes/
* aarch64-asm.h (ins_addr_offset): New.
* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
(aarch64_ins_addr_offset): New.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_addr_offset): New.
* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
(aarch64_ext_addr_offset): New.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
* aarch64-opc.c (fields): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
* aarch64-tbl.h
(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 23:22:30 +08:00
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AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
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2012-08-13 22:52:54 +08:00
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AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
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AARCH64_OPND_SYSREG, /* System register operand. */
|
2023-11-21 04:40:10 +08:00
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AARCH64_OPND_SYSREG128, /* 128-bit system register operand. */
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2012-08-13 22:52:54 +08:00
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AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
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AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
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AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
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AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
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AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
|
2023-11-16 01:21:39 +08:00
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AARCH64_OPND_SYSREG_TLBIP, /* System register <tlbip_op> operand. */
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2018-09-26 17:52:51 +08:00
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AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
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2012-08-13 22:52:54 +08:00
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AARCH64_OPND_BARRIER, /* Barrier operand. */
|
2020-10-28 22:01:36 +08:00
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AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
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2012-08-13 22:52:54 +08:00
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AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
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AARCH64_OPND_PRFOP, /* Prefetch operation. */
|
2023-03-30 18:09:18 +08:00
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AARCH64_OPND_RPRFMOP, /* Range prefetch operation. */
|
2015-12-11 18:22:40 +08:00
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AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
|
2023-11-02 21:07:29 +08:00
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AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */
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[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
2018-09-26 18:00:49 +08:00
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AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
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2024-06-07 21:59:02 +08:00
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AARCH64_OPND_BRBOP, /* BRB operation IALL or INJ in bit 5. */
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AARCH64_OPND_Rt_IN_SYS_ALIASES, /* Defaulted and omitted Rt used in SYS aliases such as brb. */
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2023-10-30 19:47:23 +08:00
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AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */
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AARCH64_OPND_LSE128_Rt2, /* LSE128 <Xt2>. */
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[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
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AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
|
[binutils][aarch64] Matrix Multiply extension enablement [8/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the aarch64 backend.
The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
(parse_operands): Add new operand.
* testsuite/gas/aarch64/i8mm.s: New test.
* testsuite/gas/aarch64/i8mm.d: New test.
* testsuite/gas/aarch64/f32mm.s: New test.
* testsuite/gas/aarch64/f32mm.d: New test.
* testsuite/gas/aarch64/f64mm.s: New test.
* testsuite/gas/aarch64/f64mm.d: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
(AARCH64_FEATURE_F32MM): New.
(AARCH64_FEATURE_F64MM): New.
(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
instructions that do not require special handling.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
aarch64_feature_f64mm): New feature sets.
(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
instructions.
(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
macros.
(QL_MMLA64, OP_SVE_SBB): New qualifiers.
(OP_SVE_QQQ): New qualifier.
(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
the movprfx constraint.
(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
(aarch64_opcode_table): Define new instructions smmla,
ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
uzip{1/2}, trn{1/2}.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_ADDR_RI_S4x32.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
Account for new instructions.
* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
S4x32 operand.
* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
Regression tested on arm-none-eabi.
Is it ok for trunk?
Regards,
Mihail
2019-11-08 01:10:01 +08:00
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AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
|
[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:
[<base>, #<offset>, MUL VL]
This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.
For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
2016-09-21 23:56:15 +08:00
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AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
|
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AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
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AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
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AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
|
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AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
|
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AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 23:55:49 +08:00
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AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
|
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AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
|
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|
AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
|
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AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
|
2018-03-28 16:44:45 +08:00
|
|
|
|
AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 23:55:49 +08:00
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AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
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AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
|
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AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
|
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AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
|
2021-11-18 04:02:06 +08:00
|
|
|
|
AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 23:55:49 +08:00
|
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AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
|
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AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
|
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|
AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
|
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AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
|
aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q
as mentioned below, for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html
1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as
predicated instructions and this issue is fixed in this patch by replacing
"SVE2p1_INSNC" with "SVE2p1_INSN" macro.
2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed
by replacing "SVE_Zt" with "SVE_ZtxN".
3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in
this patch.
4) In ld1q/st1q the index in the second argument is optional and if index
is xzr and is skipped in the assembly, the index field is ignored by the
disassembler.
Fixing above mentioned issues helps with following:
1) ld1q and st1q first register operand accepts enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping
sequence of vector registers.
For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
registers are added along with short-form of operands for non-wrapping sequence.
I have added test using following logic:
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes)
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1>
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value)
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value)
ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones)
ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding.
For all the above form of instructions the hyphenated form is preferred for
disassembly if there are more than two registers in the list, and the register
numbers are monotonically increasing in increments of one.
2024-06-25 19:58:27 +08:00
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AARCH64_OPND_SVE_ADDR_RX_LSL4, /* SVE [<Xn|SP>, <Xm>, LSL #4]. */
|
2019-05-09 17:29:18 +08:00
|
|
|
|
AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 23:55:49 +08:00
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AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
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AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
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AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
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AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
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Bit 14 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
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Bit 22 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
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Bit 14 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
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Bit 22 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
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Bit 14 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
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Bit 22 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
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Bit 14 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
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Bit 22 controls S/U choice. */
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AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
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AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
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AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
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AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
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AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
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AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
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AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
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[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
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AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
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AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
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2016-09-21 23:57:22 +08:00
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AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
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AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
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AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
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AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
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[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
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AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
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AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
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2019-05-09 17:29:15 +08:00
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AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
|
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
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AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
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AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
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AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
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2016-09-21 23:54:53 +08:00
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AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
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[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 23:55:22 +08:00
|
|
|
|
AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
|
2016-09-21 23:54:53 +08:00
|
|
|
|
AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
|
2023-03-30 18:09:11 +08:00
|
|
|
|
AARCH64_OPND_SVE_PNd, /* SVE pn0-pn15 in Pd. */
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
|
2023-03-30 18:09:11 +08:00
|
|
|
|
AARCH64_OPND_SVE_PNg4_10, /* SVE pn0-pn15 in Pg, bits [13,10]. */
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
|
2023-03-30 18:09:11 +08:00
|
|
|
|
AARCH64_OPND_SVE_PNn, /* SVE pn0-pn15 in Pn. */
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
|
2023-03-30 18:09:11 +08:00
|
|
|
|
AARCH64_OPND_SVE_PNt, /* SVE pn0-pn15 in Pt. */
|
2016-09-21 23:57:43 +08:00
|
|
|
|
AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
|
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
|
|
|
|
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
|
|
|
|
|
|
AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
|
2019-05-09 17:29:27 +08:00
|
|
|
|
AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
|
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
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AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
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AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
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2019-05-09 17:29:22 +08:00
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AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
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[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
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AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
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AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
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AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
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AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
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AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
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AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
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AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
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AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
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2024-06-25 18:30:24 +08:00
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AARCH64_OPND_SVE_UIMM4, /* SVE unsigned 4-bit immediate. */
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2016-09-21 23:57:43 +08:00
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AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
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AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
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AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
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AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
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2024-01-15 17:34:41 +08:00
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AARCH64_OPND_SME_ZA_array_vrsb_1, /* Tile to vector, two registers (B). */
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AARCH64_OPND_SME_ZA_array_vrsh_1, /* Tile to vector, two registers (H). */
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AARCH64_OPND_SME_ZA_array_vrss_1, /* Tile to vector, two registers (S). */
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AARCH64_OPND_SME_ZA_array_vrsd_1, /* Tile to vector, two registers (D). */
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AARCH64_OPND_SME_ZA_array_vrsb_2, /* Tile to vector, four registers (B). */
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AARCH64_OPND_SME_ZA_array_vrsh_2, /* Tile to vector, four registers (H). */
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AARCH64_OPND_SME_ZA_array_vrss_2, /* Tile to vector, four registers (S). */
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AARCH64_OPND_SME_ZA_array_vrsd_2, /* Tile to vector, four registers (D). */
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2024-07-08 23:36:42 +08:00
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AARCH64_OPND_SME_ZA_ARRAY4, /* Tile to vector, single (BHSDQ). */
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[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
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AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
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AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
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AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
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AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
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AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
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gas, aarch64: Add SVE2 lut extension
Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links:
* luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
* luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
These instructions use new SVE2 vector operands. They are called
SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have
1 bit, 2 bit, and 3 bit indices respectively.
The lsb and width of these new operands are the same as many existing
operands but the convention is to give different names to fields that
serve different purpose so we introduced new fields in aarch64-opc.c
and aarch64-opc.h.
We made a design choice for the second operand of the halfword variant of
luti4 with two register tables. We could have either defined a new operand,
like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With
the new operand, we would need to implement constraints on register
lists based on either operand or opcode flag. With existing operand, we
could just existing constraint checks using opcode flag. We chose
the second approach and went with SVE_ZnxN and added opcode flag to
enforce lengths of vector register list operands. This way, we can reuse
the existing constraint check logic.
2024-05-28 22:45:52 +08:00
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AARCH64_OPND_SVE_Zm1_23_INDEX, /* SVE bit index in Zm, bit 23. */
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AARCH64_OPND_SVE_Zm2_22_INDEX, /* SVE bit index in Zm, bits [23,22]. */
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
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AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
|
2019-05-09 17:29:17 +08:00
|
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AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
|
gas, aarch64: Add SVE2 lut extension
Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links:
* luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en
* luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en
These instructions use new SVE2 vector operands. They are called
SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have
1 bit, 2 bit, and 3 bit indices respectively.
The lsb and width of these new operands are the same as many existing
operands but the convention is to give different names to fields that
serve different purpose so we introduced new fields in aarch64-opc.c
and aarch64-opc.h.
We made a design choice for the second operand of the halfword variant of
luti4 with two register tables. We could have either defined a new operand,
like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With
the new operand, we would need to implement constraints on register
lists based on either operand or opcode flag. With existing operand, we
could just existing constraint checks using opcode flag. We chose
the second approach and went with SVE_ZnxN and added opcode flag to
enforce lengths of vector register list operands. This way, we can reuse
the existing constraint check logic.
2024-05-28 22:45:52 +08:00
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AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */
|
2023-03-30 18:09:17 +08:00
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AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */
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AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
|
2024-06-22 02:31:34 +08:00
|
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AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */
|
2019-05-09 17:29:24 +08:00
|
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AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
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AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
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AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
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AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
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2024-06-25 18:27:23 +08:00
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AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
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AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
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AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
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AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
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AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
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2024-06-21 23:30:59 +08:00
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AARCH64_OPND_SME_Zdnx4_STRIDED, /* SVE vector register list from [4:2]*4. */
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2023-03-30 18:09:13 +08:00
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AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
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AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
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2024-06-21 23:30:59 +08:00
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AARCH64_OPND_SME_Znx2_BIT_INDEX, /* SVE vector register list encoding a bit index from [9:6]*2. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
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AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
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2024-06-22 02:32:31 +08:00
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AARCH64_OPND_SME_ZAda_1b, /* SME <ZAda>.H, 1-bits. */
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2021-11-18 03:21:33 +08:00
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AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
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AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
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2021-11-18 03:31:25 +08:00
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AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */
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2021-11-18 03:31:25 +08:00
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AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Pdx2, /* Predicate register list in [3:1]. */
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AARCH64_OPND_SME_PdxN, /* Predicate register list in [3:0]. */
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2021-11-18 03:21:33 +08:00
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AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_PNd3, /* Predicate-as-counter register, bits [3:0]. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_PNn, /* Predicate-as-counter register, bits [8:5]. */
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AARCH64_OPND_SME_PNn3_INDEX1, /* Indexed pred-as-counter reg, bits [8:5]. */
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AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */
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2021-11-18 03:56:09 +08:00
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AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
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2023-03-30 18:09:11 +08:00
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AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
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2023-03-30 18:09:14 +08:00
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AARCH64_OPND_SME_ZA_array_off1x4, /* SME ZA[<Wv>, #<imm1>*4:<imm1>*4+3]. */
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2023-03-30 18:09:13 +08:00
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AARCH64_OPND_SME_ZA_array_off2x2, /* SME ZA[<Wv>, #<imm2>*2:<imm2>*2+1]. */
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2023-03-30 18:09:14 +08:00
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AARCH64_OPND_SME_ZA_array_off2x4, /* SME ZA[<Wv>, #<imm2>*4:<imm2>*4+3]. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
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AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */
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2023-03-30 18:09:13 +08:00
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AARCH64_OPND_SME_ZA_array_off3x2, /* SME ZA[<Wv>, #<imm3>*2:<imm3>*2+1]. */
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2023-03-30 18:09:11 +08:00
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AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */
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2021-11-18 04:02:06 +08:00
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AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
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2021-11-18 04:15:13 +08:00
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AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
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2023-03-30 18:09:11 +08:00
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AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
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2023-03-30 18:09:16 +08:00
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AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */
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AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
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2023-03-30 18:09:13 +08:00
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AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
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AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
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2024-06-22 02:32:31 +08:00
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AARCH64_OPND_SME_Zm_INDEX2_3, /* Zn.T[index], bits [19:16,10,3]. */
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2023-03-30 18:09:14 +08:00
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AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */
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2023-03-30 18:09:13 +08:00
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AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */
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2024-06-22 02:32:31 +08:00
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AARCH64_OPND_SME_Zm_INDEX3_3, /* Zn.T[index], bits [19:16,11:10,3]. */
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2023-03-30 18:09:13 +08:00
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AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */
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2023-03-30 18:09:14 +08:00
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AARCH64_OPND_SME_Zm_INDEX4_1, /* Zn.T[index], bits [19:16,11:10,2:1]. */
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2024-06-22 02:32:31 +08:00
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AARCH64_OPND_SME_Zm_INDEX4_2, /* Zn.T[index], bits [19:16,11:10,3:2]. */
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AARCH64_OPND_SME_Zm_INDEX4_3, /* Zn.T[index], bits [19:16,15,11,10,3]. */
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2023-03-30 18:09:14 +08:00
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AARCH64_OPND_SME_Zm_INDEX4_10, /* Zn.T[index], bits [19:16,15,12:10]. */
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2023-03-30 18:09:12 +08:00
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AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
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AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
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AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
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AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
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AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
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AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
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aarch64: Add support for sve2p1 pmov instruction.
This patch adds support for followign SVE2p1 instruction, spec is available here [1].
1. PMOV (to vector)
2. PMOV (to predicate)
Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.
AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".
As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
PMOV <Pn>.D, <Zd>{[<imm>]}
Example1:
Assembly: pmov z5[0], p6.d
Disassembly: pmov z5, p6.d
Assembly: pmov z5, p6.d
Disassembly: pmov z5, p6.d
Example2:
Assembly: pmov p4.b, z5[0]
Disassembly: pmov p4.b, z5
Assembly: pmov p4.b, z5
Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-09 00:44:33 +08:00
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AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
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AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
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AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
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AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
|
|
|
|
|
|
AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
|
2023-03-30 18:09:12 +08:00
|
|
|
|
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
|
|
|
|
|
|
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
|
2023-03-30 18:09:12 +08:00
|
|
|
|
AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
|
|
|
|
|
|
AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */
|
2024-06-21 23:30:59 +08:00
|
|
|
|
AARCH64_OPND_SME_ZT0_INDEX2_12, /* ZT0[<imm>], bits [13:12]. */
|
2023-03-30 18:09:12 +08:00
|
|
|
|
AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */
|
2019-05-02 00:14:01 +08:00
|
|
|
|
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
|
Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
* config/tc-aarch64.c (process_omitted_operand):
Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
and AARCH64_OPND_IMM_2.
(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
and AARCH64_OPND_ADDR_OFFSET.
include/
* opcode/aarch64.h:
(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
and AARCH64_OPND_SM3_IMM2.
(aarch64_insn_class): Add cryptosm3 and cryptosm4.
(arch64_feature_set): Make uint64_t.
opcodes/
* aarch64-asm.h (ins_addr_offset): New.
* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
(aarch64_ins_addr_offset): New.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_addr_offset): New.
* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
(aarch64_ext_addr_offset): New.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
* aarch64-opc.c (fields): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
* aarch64-tbl.h
(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 23:22:30 +08:00
|
|
|
|
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
|
aarch64: Add support for +mops
This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.
I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]
include/
* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
(AARCH64_OPND_MOPS_WB_Rn): Likewise.
opcodes/
* aarch64-asm.h (ins_x0_to_x30): New inserter.
* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
* aarch64-dis.h (ext_x0_to_x30): New extractor.
* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
* aarch64-tbl.h (aarch64_feature_mops): New feature set.
(aarch64_feature_mops_memtag): Likewise.
(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
(MOPS_SET_INSN): New macros.
(aarch64_opcode_table): Add MOPS instructions.
(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
* aarch64-opc.c (aarch64_print_operand): Handle
AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
AARCH64_OPND_MOPS_WB_Rn.
(verify_three_different_regs): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
* doc/c-aarch64.texi: Document +mops.
* config/tc-aarch64.c (parse_x0_to_x30): New function.
(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
(aarch64_features): Add "mops".
* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
* testsuite/gas/aarch64/mops_invalid.s,
* testsuite/gas/aarch64/mops_invalid.d,
* testsuite/gas/aarch64/mops_invalid.l: Likewise.
2021-12-02 23:00:57 +08:00
|
|
|
|
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
|
|
|
|
|
|
AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */
|
2022-11-15 00:47:22 +08:00
|
|
|
|
AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */
|
|
|
|
|
|
AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */
|
|
|
|
|
|
AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */
|
aarch64: rcpc3: New RCPC3_ADDR operand types
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
2024-01-06 01:26:09 +08:00
|
|
|
|
AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* [<Xn|SP>]{, #<imm>}. */
|
|
|
|
|
|
AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!. */
|
|
|
|
|
|
AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
|
|
|
|
|
|
AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */
|
2024-06-07 21:59:02 +08:00
|
|
|
|
AARCH64_OPND_RCPC3_ADDR_OFFSET,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* Qualifier constrains an operand. It either specifies a variant of an
|
|
|
|
|
|
operand type or limits values available to an operand type.
|
|
|
|
|
|
|
|
|
|
|
|
N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
|
|
|
|
|
|
|
|
|
|
|
|
enum aarch64_opnd_qualifier
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Indicating no further qualification on an operand. */
|
|
|
|
|
|
AARCH64_OPND_QLF_NIL,
|
|
|
|
|
|
|
|
|
|
|
|
/* Qualifying an operand which is a general purpose (integer) register;
|
|
|
|
|
|
indicating the operand data size or a specific register. */
|
|
|
|
|
|
AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
|
|
|
|
|
|
AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
|
|
|
|
|
|
AARCH64_OPND_QLF_WSP, /* WSP. */
|
|
|
|
|
|
AARCH64_OPND_QLF_SP, /* SP. */
|
|
|
|
|
|
|
|
|
|
|
|
/* Qualifying an operand which is a floating-point register, a SIMD
|
|
|
|
|
|
vector element or a SIMD vector element list; indicating operand data
|
|
|
|
|
|
size or the size of each SIMD vector element in the case of a SIMD
|
|
|
|
|
|
vector element list.
|
|
|
|
|
|
These qualifiers are also used to qualify an address operand to
|
|
|
|
|
|
indicate the size of data element a load/store instruction is
|
|
|
|
|
|
accessing.
|
|
|
|
|
|
They are also used for the immediate shift operand in e.g. SSHR. Such
|
|
|
|
|
|
a use is only for the ease of operand encoding/decoding and qualifier
|
|
|
|
|
|
sequence matching; such a use should not be applied widely; use the value
|
|
|
|
|
|
constraint qualifiers for immediate operands wherever possible. */
|
|
|
|
|
|
AARCH64_OPND_QLF_S_B,
|
|
|
|
|
|
AARCH64_OPND_QLF_S_H,
|
|
|
|
|
|
AARCH64_OPND_QLF_S_S,
|
|
|
|
|
|
AARCH64_OPND_QLF_S_D,
|
|
|
|
|
|
AARCH64_OPND_QLF_S_Q,
|
2024-06-22 02:31:34 +08:00
|
|
|
|
/* These type qualifiers have a special meaning in that they mean 2 x 1 byte,
|
|
|
|
|
|
4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that
|
|
|
|
|
|
they have no difference with AARCH64_OPND_QLF_S_B in encoding. They are
|
|
|
|
|
|
here purely for syntactical reasons and is an exception from normal
|
|
|
|
|
|
AArch64 disassembly scheme. */
|
|
|
|
|
|
AARCH64_OPND_QLF_S_2B,
|
2017-12-19 20:05:20 +08:00
|
|
|
|
AARCH64_OPND_QLF_S_4B,
|
[binutils][aarch64] Bfloat16 enablement [2/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Special case the
S_2H operand qualifier.
* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
* testsuite/gas/aarch64/bfloat16.d: New test.
* testsuite/gas/aarch64/bfloat16.s: New test.
* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
(enum aarch64_opnd_qualifier): Introduce new operand qualifier
AARCH64_OPND_QLF_S_2H.
(enum aarch64_insn_class): Introduce new class "bfloat16".
(BFLOAT16_SVE_INSNC): New feature set for bfloat16
instructions to support the movprfx constraint.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-dis-2.c (aarch64_opcode_lookup_1,
aarch64_find_next_opcode): Account for new instructions.
* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-opc.c (struct operand_qualifier_data): Add data for
new AARCH64_OPND_QLF_S_2H qualifier.
* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
aarch64_feature_bfloat16_bfmmla4): New feature sets.
(BFLOAT_SVE, BFLOAT): New feature set macros.
(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
to define BFloat16 instructions.
(aarch64_opcode_table): Define new instructions bfdot,
bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
bfcvtn2, bfcvt.
Regression tested on aarch64-elf.
Is it ok for trunk?
Regards,
Mihail
2019-11-08 00:38:59 +08:00
|
|
|
|
AARCH64_OPND_QLF_S_2H,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
/* Qualifying an operand which is a SIMD vector register or a SIMD vector
|
|
|
|
|
|
register list; indicating register shape.
|
|
|
|
|
|
They are also used for the immediate shift operand in e.g. SSHR. Such
|
|
|
|
|
|
a use is only for the ease of operand encoding/decoding and qualifier
|
|
|
|
|
|
sequence matching; such a use should not be applied widely; use the value
|
|
|
|
|
|
constraint qualifiers for immediate operands wherever possible. */
|
2017-12-19 20:04:13 +08:00
|
|
|
|
AARCH64_OPND_QLF_V_4B,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_QLF_V_8B,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_16B,
|
2015-12-15 01:27:52 +08:00
|
|
|
|
AARCH64_OPND_QLF_V_2H,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_QLF_V_4H,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_8H,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_2S,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_4S,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_1D,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_2D,
|
|
|
|
|
|
AARCH64_OPND_QLF_V_1Q,
|
|
|
|
|
|
|
2016-09-21 23:54:30 +08:00
|
|
|
|
AARCH64_OPND_QLF_P_Z,
|
|
|
|
|
|
AARCH64_OPND_QLF_P_M,
|
[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12 21:09:55 +08:00
|
|
|
|
|
|
|
|
|
|
/* Used in scaled signed immediate that are scaled by a Tag granule
|
|
|
|
|
|
like in stg, st2g, etc. */
|
|
|
|
|
|
AARCH64_OPND_QLF_imm_tag,
|
2016-09-21 23:54:30 +08:00
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* Constraint on value. */
|
2016-12-13 20:37:18 +08:00
|
|
|
|
AARCH64_OPND_QLF_CR, /* CRn, CRm. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPND_QLF_imm_0_7,
|
|
|
|
|
|
AARCH64_OPND_QLF_imm_0_15,
|
|
|
|
|
|
AARCH64_OPND_QLF_imm_0_31,
|
|
|
|
|
|
AARCH64_OPND_QLF_imm_0_63,
|
|
|
|
|
|
AARCH64_OPND_QLF_imm_1_32,
|
|
|
|
|
|
AARCH64_OPND_QLF_imm_1_64,
|
|
|
|
|
|
|
|
|
|
|
|
/* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
|
|
|
|
|
|
or shift-ones. */
|
|
|
|
|
|
AARCH64_OPND_QLF_LSL,
|
|
|
|
|
|
AARCH64_OPND_QLF_MSL,
|
|
|
|
|
|
|
|
|
|
|
|
/* Special qualifier helping retrieve qualifier information during the
|
|
|
|
|
|
decoding time (currently not in use). */
|
|
|
|
|
|
AARCH64_OPND_QLF_RETRIEVE,
|
aarch64: Remove asserts from operand qualifier decoders [PR31595]
Given that the disassembler should never abort when decoding
(potentially random) data, assertion statements in the
`get_*reg_qualifier_from_value' function family prove problematic.
Consider the random 32-bit word W, encoded in a data segment and
encountered on execution of `objdump -D <obj_name>'.
If:
(W & ~opcode_mask) == valid instruction
Then before `print_insn_aarch64_word' has a chance to report the
instruction as potentially undefined, an attempt will be made to have
the qualifiers for the instruction's register operands (if any)
decoded. If the relevant bits do not map onto a valid qualifier for
the matched instruction-like word, an abort will be triggered and the
execution of objdump aborted.
As this scenario is perfectly feasible and, in light of the fact that
objdump must successfully decode all sections of a given object file,
it is not appropriate to assert in this family of functions.
Therefore, we add a new pseudo-qualifier `AARCH64_OPND_QLF_ERR' for
handling invalid qualifier-associated values and re-purpose the
assertion conditions in qualifier-retrieving functions to be the
predicate guarding the returning of the calculated qualifier type.
If the predicate fails, we return this new qualifier and allow the
caller to handle the error as appropriate.
As these functions are called either from within
`aarch64_extract_operand' or `do_special_decoding', both of which are
expected to return non-zero values, it suffices that callers return
zero upon encountering `AARCH64_OPND_QLF_ERR'.
Ar present the error presented in the hypothetical scenario has been
encountered in `get_sreg_qualifier_from_value', but the change is made
to the whole family to keep the interface consistent.
Bug: https://sourceware.org/PR31595
2024-04-16 18:49:15 +08:00
|
|
|
|
|
|
|
|
|
|
/* Special qualifier used for indicating error in qualifier retrieval. */
|
|
|
|
|
|
AARCH64_OPND_QLF_ERR,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* Instruction class. */
|
|
|
|
|
|
|
|
|
|
|
|
enum aarch64_insn_class
|
|
|
|
|
|
{
|
[binutils][aarch64] Matrix Multiply extension enablement [8/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the aarch64 backend.
The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
(parse_operands): Add new operand.
* testsuite/gas/aarch64/i8mm.s: New test.
* testsuite/gas/aarch64/i8mm.d: New test.
* testsuite/gas/aarch64/f32mm.s: New test.
* testsuite/gas/aarch64/f32mm.d: New test.
* testsuite/gas/aarch64/f64mm.s: New test.
* testsuite/gas/aarch64/f64mm.d: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
(AARCH64_FEATURE_F32MM): New.
(AARCH64_FEATURE_F64MM): New.
(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
instructions that do not require special handling.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
aarch64_feature_f64mm): New feature sets.
(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
instructions.
(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
macros.
(QL_MMLA64, OP_SVE_SBB): New qualifiers.
(OP_SVE_QQQ): New qualifier.
(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
the movprfx constraint.
(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
(aarch64_opcode_table): Define new instructions smmla,
ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
uzip{1/2}, trn{1/2}.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_ADDR_RI_S4x32.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
Account for new instructions.
* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
S4x32 operand.
* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
Regression tested on arm-none-eabi.
Is it ok for trunk?
Regards,
Mihail
2019-11-08 01:10:01 +08:00
|
|
|
|
aarch64_misc,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
addsub_carry,
|
|
|
|
|
|
addsub_ext,
|
|
|
|
|
|
addsub_imm,
|
|
|
|
|
|
addsub_shift,
|
|
|
|
|
|
asimdall,
|
|
|
|
|
|
asimddiff,
|
|
|
|
|
|
asimdelem,
|
|
|
|
|
|
asimdext,
|
|
|
|
|
|
asimdimm,
|
|
|
|
|
|
asimdins,
|
|
|
|
|
|
asimdmisc,
|
|
|
|
|
|
asimdperm,
|
|
|
|
|
|
asimdsame,
|
|
|
|
|
|
asimdshf,
|
|
|
|
|
|
asimdtbl,
|
|
|
|
|
|
asisddiff,
|
|
|
|
|
|
asisdelem,
|
|
|
|
|
|
asisdlse,
|
|
|
|
|
|
asisdlsep,
|
|
|
|
|
|
asisdlso,
|
|
|
|
|
|
asisdlsop,
|
|
|
|
|
|
asisdmisc,
|
|
|
|
|
|
asisdone,
|
|
|
|
|
|
asisdpair,
|
|
|
|
|
|
asisdsame,
|
|
|
|
|
|
asisdshf,
|
|
|
|
|
|
bitfield,
|
|
|
|
|
|
branch_imm,
|
|
|
|
|
|
branch_reg,
|
|
|
|
|
|
compbranch,
|
|
|
|
|
|
condbranch,
|
|
|
|
|
|
condcmp_imm,
|
|
|
|
|
|
condcmp_reg,
|
|
|
|
|
|
condsel,
|
|
|
|
|
|
cryptoaes,
|
|
|
|
|
|
cryptosha2,
|
|
|
|
|
|
cryptosha3,
|
|
|
|
|
|
dp_1src,
|
|
|
|
|
|
dp_2src,
|
|
|
|
|
|
dp_3src,
|
|
|
|
|
|
exception,
|
|
|
|
|
|
extract,
|
|
|
|
|
|
float2fix,
|
|
|
|
|
|
float2int,
|
|
|
|
|
|
floatccmp,
|
|
|
|
|
|
floatcmp,
|
|
|
|
|
|
floatdp1,
|
|
|
|
|
|
floatdp2,
|
|
|
|
|
|
floatdp3,
|
|
|
|
|
|
floatimm,
|
|
|
|
|
|
floatsel,
|
|
|
|
|
|
ldst_immpost,
|
|
|
|
|
|
ldst_immpre,
|
|
|
|
|
|
ldst_imm9, /* immpost or immpre */
|
2016-11-18 17:49:06 +08:00
|
|
|
|
ldst_imm10, /* LDRAA/LDRAB */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
ldst_pos,
|
|
|
|
|
|
ldst_regoff,
|
|
|
|
|
|
ldst_unpriv,
|
|
|
|
|
|
ldst_unscaled,
|
|
|
|
|
|
ldstexcl,
|
|
|
|
|
|
ldstnapair_offs,
|
|
|
|
|
|
ldstpair_off,
|
|
|
|
|
|
ldstpair_indexed,
|
|
|
|
|
|
loadlit,
|
|
|
|
|
|
log_imm,
|
|
|
|
|
|
log_shift,
|
2014-09-03 21:40:41 +08:00
|
|
|
|
lse_atomic,
|
2023-10-30 20:39:28 +08:00
|
|
|
|
lse128_atomic,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
movewide,
|
|
|
|
|
|
pcreladdr,
|
|
|
|
|
|
ic_system,
|
2023-03-30 18:09:13 +08:00
|
|
|
|
sme_fp_sd,
|
|
|
|
|
|
sme_int_sd,
|
2021-11-18 03:21:33 +08:00
|
|
|
|
sme_misc,
|
2023-03-30 18:09:02 +08:00
|
|
|
|
sme_mov,
|
2021-11-18 04:02:06 +08:00
|
|
|
|
sme_ldr,
|
2023-03-30 18:09:02 +08:00
|
|
|
|
sme_psel,
|
2023-03-30 18:09:16 +08:00
|
|
|
|
sme_shift,
|
2024-07-08 23:36:40 +08:00
|
|
|
|
sme_size_12_bh,
|
2023-03-30 18:09:12 +08:00
|
|
|
|
sme_size_12_bhs,
|
|
|
|
|
|
sme_size_12_hs,
|
2024-06-21 23:30:59 +08:00
|
|
|
|
sme_size_12_b,
|
2023-03-30 18:09:12 +08:00
|
|
|
|
sme_size_22,
|
2023-03-30 18:09:13 +08:00
|
|
|
|
sme_size_22_hsd,
|
2023-03-30 18:09:16 +08:00
|
|
|
|
sme_sz_23,
|
2021-11-18 04:02:06 +08:00
|
|
|
|
sme_str,
|
2021-11-18 04:15:13 +08:00
|
|
|
|
sme_start,
|
|
|
|
|
|
sme_stop,
|
2023-03-30 18:09:12 +08:00
|
|
|
|
sme2_mov,
|
2024-01-15 17:34:41 +08:00
|
|
|
|
sme2_movaz,
|
[AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding. Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.
include/
* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
(sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
(sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
aarch64_insn_classes.
opcodes/
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
* aarch64-asm.c (aarch64_get_variant): New function.
(aarch64_encode_variant_using_iclass): Likewise.
(aarch64_opcode_encode): Call it.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
(aarch64_opcode_decode): Call it.
2016-09-21 23:58:22 +08:00
|
|
|
|
sve_cpy,
|
|
|
|
|
|
sve_index,
|
|
|
|
|
|
sve_limm,
|
|
|
|
|
|
sve_misc,
|
|
|
|
|
|
sve_movprfx,
|
|
|
|
|
|
sve_pred_zm,
|
|
|
|
|
|
sve_shift_pred,
|
|
|
|
|
|
sve_shift_unpred,
|
|
|
|
|
|
sve_size_bhs,
|
|
|
|
|
|
sve_size_bhsd,
|
|
|
|
|
|
sve_size_hsd,
|
2019-05-09 17:29:16 +08:00
|
|
|
|
sve_size_hsd2,
|
[AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding. Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.
include/
* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
(sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
(sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
aarch64_insn_classes.
opcodes/
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
* aarch64-asm.c (aarch64_get_variant): New function.
(aarch64_encode_variant_using_iclass): Likewise.
(aarch64_opcode_encode): Call it.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
(aarch64_opcode_decode): Call it.
2016-09-21 23:58:22 +08:00
|
|
|
|
sve_size_sd,
|
2019-05-09 17:29:20 +08:00
|
|
|
|
sve_size_bh,
|
2019-05-09 17:29:19 +08:00
|
|
|
|
sve_size_sd2,
|
[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.
Only the variant specifying .Q -> .D sizes should have that
restriction.
This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).
We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size. This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.
Regtested targeting aarch64-linux.
gas/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
* doc/c-aarch64.texi: Add special note of pmull{t,b}
instructions under the sve2-aes architecture extension.
* testsuite/gas/aarch64/illegal-sve2.s: Add small size
pmull{t,b} instructions.
* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
disassembly.
* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
instructions.
include/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
renamed to sve_size_13.
opcodes/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
(OP_SVE_VVV_Q_D): Add new qualifier.
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
(struct aarch64_opcode): Split pmull{t,b} into those requiring
AES and those not.
2019-07-01 22:17:22 +08:00
|
|
|
|
sve_size_13,
|
2019-05-09 17:29:22 +08:00
|
|
|
|
sve_shift_tsz_hsd,
|
2019-05-09 17:29:23 +08:00
|
|
|
|
sve_shift_tsz_bhsd,
|
2019-05-09 17:29:26 +08:00
|
|
|
|
sve_size_tsz_bhs,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
testbranch,
|
Adds the new Fields and Operand types for the new instructions in Armv8.4-a.
gas/
* config/tc-aarch64.c (process_omitted_operand):
Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
and AARCH64_OPND_IMM_2.
(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
and AARCH64_OPND_ADDR_OFFSET.
include/
* opcode/aarch64.h:
(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
and AARCH64_OPND_SM3_IMM2.
(aarch64_insn_class): Add cryptosm3 and cryptosm4.
(arch64_feature_set): Make uint64_t.
opcodes/
* aarch64-asm.h (ins_addr_offset): New.
* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
(aarch64_ins_addr_offset): New.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_addr_offset): New.
* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
(aarch64_ext_addr_offset): New.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
* aarch64-opc.c (fields): Add FLD_imm6_2,
FLD_imm4_2 and FLD_SM3_imm2.
(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
* aarch64-tbl.h
(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09 23:22:30 +08:00
|
|
|
|
cryptosm3,
|
|
|
|
|
|
cryptosm4,
|
2017-06-28 18:09:01 +08:00
|
|
|
|
dotproduct,
|
[binutils][aarch64] Bfloat16 enablement [2/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Special case the
S_2H operand qualifier.
* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
* testsuite/gas/aarch64/bfloat16.d: New test.
* testsuite/gas/aarch64/bfloat16.s: New test.
* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
(enum aarch64_opnd_qualifier): Introduce new operand qualifier
AARCH64_OPND_QLF_S_2H.
(enum aarch64_insn_class): Introduce new class "bfloat16".
(BFLOAT16_SVE_INSNC): New feature set for bfloat16
instructions to support the movprfx constraint.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-dis-2.c (aarch64_opcode_lookup_1,
aarch64_find_next_opcode): Account for new instructions.
* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-opc.c (struct operand_qualifier_data): Add data for
new AARCH64_OPND_QLF_S_2H qualifier.
* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
aarch64_feature_bfloat16_bfmmla4): New feature sets.
(BFLOAT_SVE, BFLOAT): New feature set macros.
(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
to define BFloat16 instructions.
(aarch64_opcode_table): Define new instructions bfdot,
bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
bfcvtn2, bfcvt.
Regression tested on aarch64-elf.
Is it ok for trunk?
Regards,
Mihail
2019-11-08 00:38:59 +08:00
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bfloat16,
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2022-11-15 00:47:22 +08:00
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cssc,
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2023-11-02 21:04:20 +08:00
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gcs,
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aarch64: ADD FEAT_THE RCWCAS instructions.
This patch adds support for FEAT_THE doubleword and quadword instructions.
doubleword insturctions are enabled by "+the" flag whereas quadword
instructions are enabled on passing both "+the and +d128" flags.
Support for following sets of instructions is added in this patch.
Read check write compare and swap doubleword:
(rcwcas, rcwcasa, rcwcasal, rcwcasl)
Read check write compare and swap quadword:
(rcwcasp,rcwcaspa, rcwcaspal, rcwcaspl)
Read check write software compare and swap doubleword:
(rcwscas, rcwscasa, rcwscasal, rcwscasl)
Read check write software compare and swap quadword:
(rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl)
Read check write atomic bit clear on doubleword:
(rcwclr, rcwclra, rcwclral, rcwclrl)
Read check write atomic bit clear on quadword:
(rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl)
Read check write software atomic bit clear on doubleword:
(rcwsclr, rcwsclra, rcwsclral, rcwsclrl)
Read check write software atomic bit clear on quadword:
(rcwsclrp,rcwsclrpa, rcwsclrpal,rcwsclrpl)
Read check write atomic bit set on doubleword:
(rcwset,rcwseta, rcwsetal,rcwsetl)
Read check write atomic bit set on quadword:
(rcwsetp,rcwsetpa,rcwsetpal,rcwsetpl)
Read check write software atomic bit set on doubleword:
(rcwsset,rcwsseta,rcwssetal,rcwssetl)
Read check write software atomic bit set on quadword:
(rcwssetp,rcwssetpa,rcwssetpal,rcwssetpl)
Read check write swap doubleword:
(rcwswp,rcwswpa,rcwswpal,rcwswpl)
Read check write swap quadword:
(rcwswpp,rcwswppa, rcwswppal,rcwswppl)
Read check write software swap doubleword:
(rcwsswp,rcwsswpa,rcwsswpal,rcwsswpl)
Read check write software swap quadword:
(rcwsswpp,rcwsswppa,rcwsswppal,rcwsswppl)
2024-01-09 18:30:20 +08:00
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the,
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2024-01-15 17:37:32 +08:00
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sve2_urqvs,
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sve_index1,
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2024-05-28 22:45:50 +08:00
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rcpc3,
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2024-07-19 11:24:35 +08:00
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lut,
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last_iclass = lut
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2012-08-13 22:52:54 +08:00
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};
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/* Opcode enumerators. */
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enum aarch64_op
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{
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OP_NIL,
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OP_STRB_POS,
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OP_LDRB_POS,
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OP_LDRSB_POS,
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OP_STRH_POS,
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OP_LDRH_POS,
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OP_LDRSH_POS,
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OP_STR_POS,
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OP_LDR_POS,
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OP_STRF_POS,
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OP_LDRF_POS,
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OP_LDRSW_POS,
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OP_PRFM_POS,
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OP_STURB,
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OP_LDURB,
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OP_LDURSB,
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OP_STURH,
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OP_LDURH,
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OP_LDURSH,
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OP_STUR,
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OP_LDUR,
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OP_STURV,
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OP_LDURV,
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OP_LDURSW,
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OP_PRFUM,
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OP_LDR_LIT,
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OP_LDRV_LIT,
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OP_LDRSW_LIT,
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OP_PRFM_LIT,
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OP_ADD,
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OP_B,
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OP_BL,
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OP_MOVN,
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OP_MOVZ,
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OP_MOVK,
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OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
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OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
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OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
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OP_MOV_V, /* MOV alias for moving vector register. */
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OP_ASR_IMM,
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OP_LSR_IMM,
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OP_LSL_IMM,
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OP_BIC,
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OP_UBFX,
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OP_BFXIL,
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OP_SBFX,
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OP_SBFIZ,
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OP_BFI,
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2015-11-27 23:25:08 +08:00
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OP_BFC, /* ARMv8.2. */
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2012-08-13 22:52:54 +08:00
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OP_UBFIZ,
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OP_UXTB,
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OP_UXTH,
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OP_UXTW,
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OP_CINC,
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OP_CINV,
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OP_CNEG,
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OP_CSET,
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OP_CSETM,
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OP_FCVT,
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OP_FCVTN,
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OP_FCVTN2,
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OP_FCVTL,
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OP_FCVTL2,
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OP_FCVTXN_S, /* Scalar version. */
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OP_ROR_IMM,
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include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
opcodes/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
gas/testsuite/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
2013-01-30 23:43:32 +08:00
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OP_SXTL,
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OP_SXTL2,
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OP_UXTL,
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OP_UXTL2,
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[AArch64][SVE 31/32] Add SVE instructions
This patch adds the SVE instruction definitions and associated OP_*
enum values.
include/
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
opcodes/
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
(OP_SVE_XWU, OP_SVE_XXU): New macros.
(aarch64_feature_sve): New variable.
(SVE): New macro.
(_SVE_INSN): Likewise.
(aarch64_opcode_table): Add SVE instructions.
* aarch64-opc.h (extract_fields): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.c (extract_fields): Make global.
(do_misc_decoding): Handle the new SVE aarch64_ops.
* aarch64-dis-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.
2016-09-21 23:58:48 +08:00
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OP_MOV_P_P,
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2023-03-30 18:09:11 +08:00
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OP_MOV_PN_PN,
|
[AArch64][SVE 31/32] Add SVE instructions
This patch adds the SVE instruction definitions and associated OP_*
enum values.
include/
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
opcodes/
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
(OP_SVE_XWU, OP_SVE_XXU): New macros.
(aarch64_feature_sve): New variable.
(SVE): New macro.
(_SVE_INSN): Likewise.
(aarch64_opcode_table): Add SVE instructions.
* aarch64-opc.h (extract_fields): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.c (extract_fields): Make global.
(do_misc_decoding): Handle the new SVE aarch64_ops.
* aarch64-dis-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.
2016-09-21 23:58:48 +08:00
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OP_MOV_Z_P_Z,
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OP_MOV_Z_V,
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OP_MOV_Z_Z,
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OP_MOV_Z_Zi,
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OP_MOVM_P_P_P,
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OP_MOVS_P_P,
|
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OP_MOVZS_P_P_P,
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OP_MOVZ_P_P_P,
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OP_NOTS_P_P_P_Z,
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OP_NOT_P_P_P_Z,
|
|
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|
|
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 18:02:16 +08:00
|
|
|
|
OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
|
|
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
OP_TOTAL_NUM, /* Pseudo. */
|
|
|
|
|
|
};
|
|
|
|
|
|
|
2018-10-04 01:35:15 +08:00
|
|
|
|
/* Error types. */
|
|
|
|
|
|
enum err_type
|
|
|
|
|
|
{
|
|
|
|
|
|
ERR_OK,
|
|
|
|
|
|
ERR_UND,
|
|
|
|
|
|
ERR_UNP,
|
|
|
|
|
|
ERR_NYI,
|
2018-10-04 01:38:42 +08:00
|
|
|
|
ERR_VFI,
|
2018-10-04 01:35:15 +08:00
|
|
|
|
ERR_NR_ENTRIES
|
|
|
|
|
|
};
|
|
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* Maximum number of operands an instruction can have. */
|
2023-11-15 21:48:59 +08:00
|
|
|
|
#define AARCH64_MAX_OPND_NUM 7
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* Maximum number of qualifier sequences an instruction can have. */
|
|
|
|
|
|
#define AARCH64_MAX_QLF_SEQ_NUM 10
|
|
|
|
|
|
/* Operand qualifier typedef; optimized for the size. */
|
|
|
|
|
|
typedef unsigned char aarch64_opnd_qualifier_t;
|
|
|
|
|
|
/* Operand qualifier sequence typedef. */
|
|
|
|
|
|
typedef aarch64_opnd_qualifier_t \
|
|
|
|
|
|
aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
|
|
|
|
|
|
|
|
|
|
|
|
/* FIXME: improve the efficiency. */
|
2021-03-31 07:50:10 +08:00
|
|
|
|
static inline bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
|
|
|
|
|
|
{
|
|
|
|
|
|
int i;
|
|
|
|
|
|
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
|
|
|
|
|
|
if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
|
2021-03-31 07:50:10 +08:00
|
|
|
|
return false;
|
|
|
|
|
|
return true;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
2018-10-04 01:27:52 +08:00
|
|
|
|
/* Forward declare error reporting type. */
|
|
|
|
|
|
typedef struct aarch64_operand_error aarch64_operand_error;
|
|
|
|
|
|
/* Forward declare instruction sequence type. */
|
|
|
|
|
|
typedef struct aarch64_instr_sequence aarch64_instr_sequence;
|
|
|
|
|
|
/* Forward declare instruction definition. */
|
|
|
|
|
|
typedef struct aarch64_inst aarch64_inst;
|
|
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* This structure holds information for a particular opcode. */
|
|
|
|
|
|
|
|
|
|
|
|
struct aarch64_opcode
|
|
|
|
|
|
{
|
|
|
|
|
|
/* The name of the mnemonic. */
|
|
|
|
|
|
const char *name;
|
|
|
|
|
|
|
|
|
|
|
|
/* The opcode itself. Those bits which will be filled in with
|
|
|
|
|
|
operands are zeroes. */
|
|
|
|
|
|
aarch64_insn opcode;
|
|
|
|
|
|
|
|
|
|
|
|
/* The opcode mask. This is used by the disassembler. This is a
|
|
|
|
|
|
mask containing ones indicating those bits which must match the
|
|
|
|
|
|
opcode field, and zeroes indicating those bits which need not
|
|
|
|
|
|
match (and are presumably filled in by operands). */
|
|
|
|
|
|
aarch64_insn mask;
|
|
|
|
|
|
|
|
|
|
|
|
/* Instruction class. */
|
|
|
|
|
|
enum aarch64_insn_class iclass;
|
|
|
|
|
|
|
|
|
|
|
|
/* Enumerator identifier. */
|
|
|
|
|
|
enum aarch64_op op;
|
|
|
|
|
|
|
|
|
|
|
|
/* Which architecture variant provides this instruction. */
|
|
|
|
|
|
const aarch64_feature_set *avariant;
|
|
|
|
|
|
|
|
|
|
|
|
/* An array of operand codes. Each code is an index into the
|
|
|
|
|
|
operand table. They appear in the order which the operands must
|
|
|
|
|
|
appear in assembly code, and are terminated by a zero. */
|
|
|
|
|
|
enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
|
|
|
|
|
|
|
|
|
|
|
|
/* A list of operand qualifier code sequence. Each operand qualifier
|
|
|
|
|
|
code qualifies the corresponding operand code. Each operand
|
|
|
|
|
|
qualifier sequence specifies a valid opcode variant and related
|
|
|
|
|
|
constraint on operands. */
|
|
|
|
|
|
aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
|
|
|
|
|
|
|
|
|
|
|
|
/* Flags providing information about this instruction */
|
AArch64: Mark sve instructions that require MOVPRFX constraints
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
2018-10-04 01:22:15 +08:00
|
|
|
|
uint64_t flags;
|
|
|
|
|
|
|
|
|
|
|
|
/* Extra constraints on the instruction that the verifier checks. */
|
|
|
|
|
|
uint32_t constraints;
|
2016-04-28 16:11:03 +08:00
|
|
|
|
|
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 23:52:30 +08:00
|
|
|
|
/* If nonzero, this operand and operand 0 are both registers and
|
|
|
|
|
|
are required to have the same register number. */
|
|
|
|
|
|
unsigned char tied_operand;
|
|
|
|
|
|
|
2016-04-28 16:11:03 +08:00
|
|
|
|
/* If non-NULL, a function to verify that a given instruction is valid. */
|
2018-10-04 01:37:07 +08:00
|
|
|
|
enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
|
2021-03-31 07:50:10 +08:00
|
|
|
|
bfd_vma, bool, aarch64_operand_error *,
|
2018-10-04 01:37:07 +08:00
|
|
|
|
struct aarch64_instr_sequence *);
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
typedef struct aarch64_opcode aarch64_opcode;
|
|
|
|
|
|
|
|
|
|
|
|
/* Table describing all the AArch64 opcodes. */
|
2021-06-27 13:37:24 +08:00
|
|
|
|
extern const aarch64_opcode aarch64_opcode_table[];
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
/* Opcode flags. */
|
|
|
|
|
|
#define F_ALIAS (1 << 0)
|
|
|
|
|
|
#define F_HAS_ALIAS (1 << 1)
|
|
|
|
|
|
/* Disassembly preference priority 1-3 (the larger the higher). If nothing
|
|
|
|
|
|
is specified, it is the priority 0 by default, i.e. the lowest priority. */
|
|
|
|
|
|
#define F_P1 (1 << 2)
|
|
|
|
|
|
#define F_P2 (2 << 2)
|
|
|
|
|
|
#define F_P3 (3 << 2)
|
|
|
|
|
|
/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
|
|
|
|
|
|
#define F_COND (1 << 4)
|
|
|
|
|
|
/* Instruction has the field of 'sf'. */
|
|
|
|
|
|
#define F_SF (1 << 5)
|
|
|
|
|
|
/* Instruction has the field of 'size:Q'. */
|
|
|
|
|
|
#define F_SIZEQ (1 << 6)
|
|
|
|
|
|
/* Floating-point instruction has the field of 'type'. */
|
|
|
|
|
|
#define F_FPTYPE (1 << 7)
|
|
|
|
|
|
/* AdvSIMD scalar instruction has the field of 'size'. */
|
|
|
|
|
|
#define F_SSIZE (1 << 8)
|
|
|
|
|
|
/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
|
|
|
|
|
|
#define F_T (1 << 9)
|
|
|
|
|
|
/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
|
|
|
|
|
|
#define F_GPRSIZE_IN_Q (1 << 10)
|
|
|
|
|
|
/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
|
|
|
|
|
|
#define F_LDS_SIZE (1 << 11)
|
|
|
|
|
|
/* Optional operand; assume maximum of 1 operand can be optional. */
|
|
|
|
|
|
#define F_OPD0_OPT (1 << 12)
|
|
|
|
|
|
#define F_OPD1_OPT (2 << 12)
|
|
|
|
|
|
#define F_OPD2_OPT (3 << 12)
|
|
|
|
|
|
#define F_OPD3_OPT (4 << 12)
|
|
|
|
|
|
#define F_OPD4_OPT (5 << 12)
|
|
|
|
|
|
/* Default value for the optional operand when omitted from the assembly. */
|
|
|
|
|
|
#define F_DEFAULT(X) (((X) & 0x1f) << 15)
|
|
|
|
|
|
/* Instruction that is an alias of another instruction needs to be
|
|
|
|
|
|
encoded/decoded by converting it to/from the real form, followed by
|
|
|
|
|
|
the encoding/decoding according to the rules of the real opcode.
|
|
|
|
|
|
This compares to the direct coding using the alias's information.
|
|
|
|
|
|
N.B. this flag requires F_ALIAS to be used together. */
|
|
|
|
|
|
#define F_CONV (1 << 20)
|
|
|
|
|
|
/* Use together with F_ALIAS to indicate an alias opcode is a programmer
|
|
|
|
|
|
friendly pseudo instruction available only in the assembly code (thus will
|
|
|
|
|
|
not show up in the disassembly). */
|
|
|
|
|
|
#define F_PSEUDO (1 << 21)
|
|
|
|
|
|
/* Instruction has miscellaneous encoding/decoding rules. */
|
|
|
|
|
|
#define F_MISC (1 << 22)
|
|
|
|
|
|
/* Instruction has the field of 'N'; used in conjunction with F_SF. */
|
|
|
|
|
|
#define F_N (1 << 23)
|
|
|
|
|
|
/* Opcode dependent field. */
|
|
|
|
|
|
#define F_OD(X) (((X) & 0x7) << 24)
|
2014-09-03 21:40:41 +08:00
|
|
|
|
/* Instruction has the field of 'sz'. */
|
|
|
|
|
|
#define F_LSE_SZ (1 << 27)
|
2016-09-21 23:51:00 +08:00
|
|
|
|
/* Require an exact qualifier match, even for NIL qualifiers. */
|
|
|
|
|
|
#define F_STRICT (1ULL << 28)
|
Implement Read/Write constraints on system registers on AArch64
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15 23:37:20 +08:00
|
|
|
|
/* This system instruction is used to read system registers. */
|
|
|
|
|
|
#define F_SYS_READ (1ULL << 29)
|
|
|
|
|
|
/* This system instruction is used to write system registers. */
|
|
|
|
|
|
#define F_SYS_WRITE (1ULL << 30)
|
AArch64: Mark sve instructions that require MOVPRFX constraints
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
2018-10-04 01:22:15 +08:00
|
|
|
|
/* This instruction has an extra constraint on it that imposes a requirement on
|
|
|
|
|
|
subsequent instructions. */
|
|
|
|
|
|
#define F_SCAN (1ULL << 31)
|
aarch64: Add support for optional operand pairs
Two of the instructions added by the `+d128' architectural extension
add the flexibility to have two optional operands. Prior to the
addition of the `tlbip' and `sysp' instructions, no mnemonic allowed
more than one such optional operand.
With `tlbip' as an example, some TLBIP instruction names do not allow
for any optional operands, while others allow for both to be optional.
In the latter case, it is possible that either the second operand
alone is omitted or both operands are omitted.
Therefore, a considerable degree of flexibility needed to be added to
the way operands were parsed. It was, however, possible to achieve
this with relatively few changes to existing code.
it is noteworthy that opcode flags specifying the optional operand
number are non-orthogonal. For example, we have:
#define F_OPD1_OPT (2 << 12) : 0b10 << 12
#define F_OPD2_OPT (3 << 12) : 0b11 << 12
such that by virtue of the observation that
(F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT
it is impossible to mark both operands 1 and 2 as optional for an
instruction and it is assumed that a maximum of 1 operand can ever be
optional. This is not overly-problematic given that, for optional
pairs, the second optional operand is always found immediately after
the first. Thus, it suffices for us to flag that there is a second
optional operand. With this fact, we can infer its position in the
mnemonic from the position of the first (e.g. if the second operand in
the mnemonic is optional, we know the third is too). We therefore
define the `F_OPD_PAIR_OPT' flag and calculate its position in the
mnemonic from the value encoded by the `F_OPD<n>_OPT' flag.
Another observation is that there is a tight coupling between default
values assigned to the two registers when one (or both) are omitted
from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero
register is specified), Xt2 defaults to the same value, otherwise Xt2
will be assigned Xt + 1. This meant that where you have default value
validation, in checking the second optional operand's value, it is
also necessary to look at the value assigned to the
previously-processed operand value before deciding its validity. Thus
`process_omitted_operand' needs not only access to its `operand'
argument, but also to the global `inst' struct.
2023-12-13 22:27:31 +08:00
|
|
|
|
/* Instruction takes a pair of optional operands. If we specify the Nth operand
|
|
|
|
|
|
to be optional, then we also implicitly specify (N+1)th operand to also be
|
|
|
|
|
|
optional. */
|
|
|
|
|
|
#define F_OPD_PAIR_OPT (1ULL << 32)
|
2023-11-20 23:32:15 +08:00
|
|
|
|
/* This instruction does not allow the full range of values that the
|
|
|
|
|
|
width of fields in the assembler instruction would theoretically
|
|
|
|
|
|
allow. This impacts the constraintts on assembly but yelds no
|
|
|
|
|
|
impact on disassembly. */
|
|
|
|
|
|
#define F_OPD_NARROW (1ULL << 33)
|
2024-01-15 17:35:55 +08:00
|
|
|
|
/* For the instruction with size[22:23] field. */
|
|
|
|
|
|
#define F_OPD_SIZE (1ULL << 34)
|
2024-01-06 01:27:04 +08:00
|
|
|
|
/* RCPC3 instruction has the field of 'size'. */
|
|
|
|
|
|
#define F_RCPC3_SIZE (1ULL << 35)
|
2024-07-08 23:36:44 +08:00
|
|
|
|
/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
|
|
|
|
|
|
assembler. */
|
|
|
|
|
|
#define F_VG_REQ (1ULL << 36)
|
2024-07-19 11:24:10 +08:00
|
|
|
|
|
|
|
|
|
|
/* 4-bit flag field to indicate subclass of instructions.
|
|
|
|
|
|
Note the overlap between the set of subclass flags in each logical category
|
|
|
|
|
|
(F_LDST_*, F_ARITH_*, F_BRANCH_* etc.); The usage of flags as
|
|
|
|
|
|
iclass-specific enums is intentional. */
|
|
|
|
|
|
#define F_SUBCLASS (15ULL << 37)
|
|
|
|
|
|
|
|
|
|
|
|
#define F_LDST_LOAD (1ULL << 37)
|
|
|
|
|
|
#define F_LDST_STORE (2ULL << 37)
|
|
|
|
|
|
/* Subclasses to denote add, sub and mov insns. */
|
|
|
|
|
|
#define F_ARITH_ADD (1ULL << 37)
|
|
|
|
|
|
#define F_ARITH_SUB (2ULL << 37)
|
|
|
|
|
|
#define F_ARITH_MOV (3ULL << 37)
|
|
|
|
|
|
/* Subclasses to denote call and ret insns. */
|
|
|
|
|
|
#define F_BRANCH_CALL (1ULL << 37)
|
|
|
|
|
|
#define F_BRANCH_RET (2ULL << 37)
|
|
|
|
|
|
/* Subclass to denote that only tag update is involved. */
|
|
|
|
|
|
#define F_DP_TAG_ONLY (1ULL << 37)
|
|
|
|
|
|
|
|
|
|
|
|
#define F_SUBCLASS_OTHER (F_SUBCLASS)
|
|
|
|
|
|
/* Next bit is 41. */
|
AArch64: Mark sve instructions that require MOVPRFX constraints
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
2018-10-04 01:22:15 +08:00
|
|
|
|
|
|
|
|
|
|
/* Instruction constraints. */
|
|
|
|
|
|
/* This instruction has a predication constraint on the instruction at PC+4. */
|
|
|
|
|
|
#define C_SCAN_MOVPRFX (1U << 0)
|
|
|
|
|
|
/* This instruction's operation width is determined by the operand with the
|
|
|
|
|
|
largest element size. */
|
|
|
|
|
|
#define C_MAX_ELEM (1U << 1)
|
aarch64: Enforce P/M/E order for MOPS instructions
The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02 23:00:57 +08:00
|
|
|
|
#define C_SCAN_MOPS_P (1U << 2)
|
|
|
|
|
|
#define C_SCAN_MOPS_M (2U << 2)
|
|
|
|
|
|
#define C_SCAN_MOPS_E (3U << 2)
|
|
|
|
|
|
#define C_SCAN_MOPS_PME (3U << 2)
|
|
|
|
|
|
/* Next bit is 4. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
static inline bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
alias_opcode_p (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
TRUE/FALSE simplification
There is really no need to write code like "foo != 0 ? TRUE : FALSE"
unless we had stupidly defined FALSE as something other than 0 or TRUE
as something other than 1. The simpler "foo != 0" does just as well.
Similarly "(condition == TRUE)" or "(condition == FALSE) can be
simplified to "(condition)" and "(!condition)" respectively.
I'll note that there is reason to use "integer_expression != 0" when
assigning a bfd_boolean rather than the simpler "integer_expression",
if you expect the variable to have 0 or 1 value. It's probably even a
good idea to not rely on implicit conversion if bfd_boolean were _Bool.
bfd/
* aoutx.h (aout_link_write_symbols): Don't cast boolean expression
to bfd_boolean.
* elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans
against FALSE.
* elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE.
(is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE".
(is_reloc_SDA_relative, is_reloc_for_GOT): Likewise.
(is_reloc_for_PLT, is_reloc_for_TLS): Likewise.
* elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise.
* elf32-nds32.c (insert_nds32_elf_blank): Likewise.
* elf32-rx.c (rx_set_section_contents): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise.
* elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise.
* mach-o.c (bfd_mach_o_read_command): Likewise.
* targets.c (bfd_get_target_info): Likewise.
binutils/
* dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE".
* dwarf.c (read_and_display_attr_value): Likewise.
(display_debug_str_offsets): Likewise.
* objdump.c (dump_bfd): Likewise.
* readelf.c (dump_section_as_strings): Likewise.
(dump_section_as_bytes): Likewise.
gas/
* atof-generic.c (FALSE, TRUE): Don't define.
* config/obj-elf.h (FALSE, TRUE): Don't define.
* config/obj-som.h (FALSE, TRUE): Don't define.
* config/tc-hppa.h (FALSE, TRUE): Don't define.
* config/tc-pdp11.c (FALSE, TRUE): Don't define.
* config/tc-iq2000.h (obj_fix_adjustable): Delete.
* config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-mt.h (obj_fix_adjustable): Delete.
* config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-arc.c (parse_opcode_flags): Simplify boolean expression.
(relaxable_flag, relaxable_operand, assemble_insn): Likewise.
(tokenize_extregister): Likewise.
* config/tc-csky.c (parse_opcode, get_operand_value): Likewise.
(parse_operands_op, parse_operands, md_assemble): Likewise.
* config/tc-d10v.c (build_insn): Likewise.
* config/tc-score.c (s3_gen_insn_frag): Likewise.
* config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise.
* config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise.
* config/tc-z80.c (emit_byte): Likewise.
include/
* opcode/aarch64.h (alias_opcode_p): Simplify boolean expression.
(opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise.
(opcode_has_special_coder): Likewise.
ld/
* emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify
boolean expression.
* lexsup.c (parse_args): Likewise.
* pe-dll.c (pe_dll_id_target): Likewise.
opcodes/
* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
(fp_qualifier_p, get_data_pattern): Likewise.
(aarch64_get_operand_modifier_from_value): Likewise.
(aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
(operand_variant_qualifier_p): Likewise.
(qualifier_value_in_range_constraint_p): Likewise.
(aarch64_get_qualifier_esize): Likewise.
(aarch64_get_qualifier_nelem): Likewise.
(aarch64_get_qualifier_standard_value): Likewise.
(get_lower_bound, get_upper_bound): Likewise.
(aarch64_find_best_match, match_operands_qualifier): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
(operand_need_sign_extension, operand_need_shift_by_two): Likewise.
(operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
* arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
* tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
(print_insn_tic6x): Likewise.
2021-03-29 07:22:56 +08:00
|
|
|
|
return (opcode->flags & F_ALIAS) != 0;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
static inline bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
opcode_has_alias (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
TRUE/FALSE simplification
There is really no need to write code like "foo != 0 ? TRUE : FALSE"
unless we had stupidly defined FALSE as something other than 0 or TRUE
as something other than 1. The simpler "foo != 0" does just as well.
Similarly "(condition == TRUE)" or "(condition == FALSE) can be
simplified to "(condition)" and "(!condition)" respectively.
I'll note that there is reason to use "integer_expression != 0" when
assigning a bfd_boolean rather than the simpler "integer_expression",
if you expect the variable to have 0 or 1 value. It's probably even a
good idea to not rely on implicit conversion if bfd_boolean were _Bool.
bfd/
* aoutx.h (aout_link_write_symbols): Don't cast boolean expression
to bfd_boolean.
* elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans
against FALSE.
* elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE.
(is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE".
(is_reloc_SDA_relative, is_reloc_for_GOT): Likewise.
(is_reloc_for_PLT, is_reloc_for_TLS): Likewise.
* elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise.
* elf32-nds32.c (insert_nds32_elf_blank): Likewise.
* elf32-rx.c (rx_set_section_contents): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise.
* elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise.
* mach-o.c (bfd_mach_o_read_command): Likewise.
* targets.c (bfd_get_target_info): Likewise.
binutils/
* dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE".
* dwarf.c (read_and_display_attr_value): Likewise.
(display_debug_str_offsets): Likewise.
* objdump.c (dump_bfd): Likewise.
* readelf.c (dump_section_as_strings): Likewise.
(dump_section_as_bytes): Likewise.
gas/
* atof-generic.c (FALSE, TRUE): Don't define.
* config/obj-elf.h (FALSE, TRUE): Don't define.
* config/obj-som.h (FALSE, TRUE): Don't define.
* config/tc-hppa.h (FALSE, TRUE): Don't define.
* config/tc-pdp11.c (FALSE, TRUE): Don't define.
* config/tc-iq2000.h (obj_fix_adjustable): Delete.
* config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-mt.h (obj_fix_adjustable): Delete.
* config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-arc.c (parse_opcode_flags): Simplify boolean expression.
(relaxable_flag, relaxable_operand, assemble_insn): Likewise.
(tokenize_extregister): Likewise.
* config/tc-csky.c (parse_opcode, get_operand_value): Likewise.
(parse_operands_op, parse_operands, md_assemble): Likewise.
* config/tc-d10v.c (build_insn): Likewise.
* config/tc-score.c (s3_gen_insn_frag): Likewise.
* config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise.
* config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise.
* config/tc-z80.c (emit_byte): Likewise.
include/
* opcode/aarch64.h (alias_opcode_p): Simplify boolean expression.
(opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise.
(opcode_has_special_coder): Likewise.
ld/
* emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify
boolean expression.
* lexsup.c (parse_args): Likewise.
* pe-dll.c (pe_dll_id_target): Likewise.
opcodes/
* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
(fp_qualifier_p, get_data_pattern): Likewise.
(aarch64_get_operand_modifier_from_value): Likewise.
(aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
(operand_variant_qualifier_p): Likewise.
(qualifier_value_in_range_constraint_p): Likewise.
(aarch64_get_qualifier_esize): Likewise.
(aarch64_get_qualifier_nelem): Likewise.
(aarch64_get_qualifier_standard_value): Likewise.
(get_lower_bound, get_upper_bound): Likewise.
(aarch64_find_best_match, match_operands_qualifier): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
(operand_need_sign_extension, operand_need_shift_by_two): Likewise.
(operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
* arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
* tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
(print_insn_tic6x): Likewise.
2021-03-29 07:22:56 +08:00
|
|
|
|
return (opcode->flags & F_HAS_ALIAS) != 0;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Priority for disassembling preference. */
|
|
|
|
|
|
static inline int
|
|
|
|
|
|
opcode_priority (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
|
|
|
|
|
return (opcode->flags >> 2) & 0x3;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
static inline bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
pseudo_opcode_p (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
TRUE/FALSE simplification
There is really no need to write code like "foo != 0 ? TRUE : FALSE"
unless we had stupidly defined FALSE as something other than 0 or TRUE
as something other than 1. The simpler "foo != 0" does just as well.
Similarly "(condition == TRUE)" or "(condition == FALSE) can be
simplified to "(condition)" and "(!condition)" respectively.
I'll note that there is reason to use "integer_expression != 0" when
assigning a bfd_boolean rather than the simpler "integer_expression",
if you expect the variable to have 0 or 1 value. It's probably even a
good idea to not rely on implicit conversion if bfd_boolean were _Bool.
bfd/
* aoutx.h (aout_link_write_symbols): Don't cast boolean expression
to bfd_boolean.
* elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans
against FALSE.
* elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE.
(is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE".
(is_reloc_SDA_relative, is_reloc_for_GOT): Likewise.
(is_reloc_for_PLT, is_reloc_for_TLS): Likewise.
* elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise.
* elf32-nds32.c (insert_nds32_elf_blank): Likewise.
* elf32-rx.c (rx_set_section_contents): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise.
* elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise.
* mach-o.c (bfd_mach_o_read_command): Likewise.
* targets.c (bfd_get_target_info): Likewise.
binutils/
* dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE".
* dwarf.c (read_and_display_attr_value): Likewise.
(display_debug_str_offsets): Likewise.
* objdump.c (dump_bfd): Likewise.
* readelf.c (dump_section_as_strings): Likewise.
(dump_section_as_bytes): Likewise.
gas/
* atof-generic.c (FALSE, TRUE): Don't define.
* config/obj-elf.h (FALSE, TRUE): Don't define.
* config/obj-som.h (FALSE, TRUE): Don't define.
* config/tc-hppa.h (FALSE, TRUE): Don't define.
* config/tc-pdp11.c (FALSE, TRUE): Don't define.
* config/tc-iq2000.h (obj_fix_adjustable): Delete.
* config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-mt.h (obj_fix_adjustable): Delete.
* config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-arc.c (parse_opcode_flags): Simplify boolean expression.
(relaxable_flag, relaxable_operand, assemble_insn): Likewise.
(tokenize_extregister): Likewise.
* config/tc-csky.c (parse_opcode, get_operand_value): Likewise.
(parse_operands_op, parse_operands, md_assemble): Likewise.
* config/tc-d10v.c (build_insn): Likewise.
* config/tc-score.c (s3_gen_insn_frag): Likewise.
* config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise.
* config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise.
* config/tc-z80.c (emit_byte): Likewise.
include/
* opcode/aarch64.h (alias_opcode_p): Simplify boolean expression.
(opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise.
(opcode_has_special_coder): Likewise.
ld/
* emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify
boolean expression.
* lexsup.c (parse_args): Likewise.
* pe-dll.c (pe_dll_id_target): Likewise.
opcodes/
* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
(fp_qualifier_p, get_data_pattern): Likewise.
(aarch64_get_operand_modifier_from_value): Likewise.
(aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
(operand_variant_qualifier_p): Likewise.
(qualifier_value_in_range_constraint_p): Likewise.
(aarch64_get_qualifier_esize): Likewise.
(aarch64_get_qualifier_nelem): Likewise.
(aarch64_get_qualifier_standard_value): Likewise.
(get_lower_bound, get_upper_bound): Likewise.
(aarch64_find_best_match, match_operands_qualifier): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
(operand_need_sign_extension, operand_need_shift_by_two): Likewise.
(operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
* arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
* tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
(print_insn_tic6x): Likewise.
2021-03-29 07:22:56 +08:00
|
|
|
|
return (opcode->flags & F_PSEUDO) != 0lu;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
2024-07-19 11:24:10 +08:00
|
|
|
|
/* Whether the opcode has the specific subclass flag.
|
|
|
|
|
|
N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* etc. subclass
|
|
|
|
|
|
flags means that the callers of this function have the responsibility of
|
|
|
|
|
|
checking for the flags appropriate for the specific iclass. */
|
|
|
|
|
|
static inline bool
|
|
|
|
|
|
aarch64_opcode_subclass_p (const aarch64_opcode *opcode, uint64_t flag)
|
|
|
|
|
|
{
|
|
|
|
|
|
return ((opcode->flags & F_SUBCLASS) == flag);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
aarch64: Add support for optional operand pairs
Two of the instructions added by the `+d128' architectural extension
add the flexibility to have two optional operands. Prior to the
addition of the `tlbip' and `sysp' instructions, no mnemonic allowed
more than one such optional operand.
With `tlbip' as an example, some TLBIP instruction names do not allow
for any optional operands, while others allow for both to be optional.
In the latter case, it is possible that either the second operand
alone is omitted or both operands are omitted.
Therefore, a considerable degree of flexibility needed to be added to
the way operands were parsed. It was, however, possible to achieve
this with relatively few changes to existing code.
it is noteworthy that opcode flags specifying the optional operand
number are non-orthogonal. For example, we have:
#define F_OPD1_OPT (2 << 12) : 0b10 << 12
#define F_OPD2_OPT (3 << 12) : 0b11 << 12
such that by virtue of the observation that
(F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT
it is impossible to mark both operands 1 and 2 as optional for an
instruction and it is assumed that a maximum of 1 operand can ever be
optional. This is not overly-problematic given that, for optional
pairs, the second optional operand is always found immediately after
the first. Thus, it suffices for us to flag that there is a second
optional operand. With this fact, we can infer its position in the
mnemonic from the position of the first (e.g. if the second operand in
the mnemonic is optional, we know the third is too). We therefore
define the `F_OPD_PAIR_OPT' flag and calculate its position in the
mnemonic from the value encoded by the `F_OPD<n>_OPT' flag.
Another observation is that there is a tight coupling between default
values assigned to the two registers when one (or both) are omitted
from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero
register is specified), Xt2 defaults to the same value, otherwise Xt2
will be assigned Xt + 1. This meant that where you have default value
validation, in checking the second optional operand's value, it is
also necessary to look at the value assigned to the
previously-processed operand value before deciding its validity. Thus
`process_omitted_operand' needs not only access to its `operand'
argument, but also to the global `inst' struct.
2023-12-13 22:27:31 +08:00
|
|
|
|
/* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
|
|
|
|
|
|
by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
|
|
|
|
|
|
[IDX, IDX + 1]. */
|
2021-03-31 07:50:10 +08:00
|
|
|
|
static inline bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
|
|
|
|
|
|
{
|
aarch64: Add support for optional operand pairs
Two of the instructions added by the `+d128' architectural extension
add the flexibility to have two optional operands. Prior to the
addition of the `tlbip' and `sysp' instructions, no mnemonic allowed
more than one such optional operand.
With `tlbip' as an example, some TLBIP instruction names do not allow
for any optional operands, while others allow for both to be optional.
In the latter case, it is possible that either the second operand
alone is omitted or both operands are omitted.
Therefore, a considerable degree of flexibility needed to be added to
the way operands were parsed. It was, however, possible to achieve
this with relatively few changes to existing code.
it is noteworthy that opcode flags specifying the optional operand
number are non-orthogonal. For example, we have:
#define F_OPD1_OPT (2 << 12) : 0b10 << 12
#define F_OPD2_OPT (3 << 12) : 0b11 << 12
such that by virtue of the observation that
(F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT
it is impossible to mark both operands 1 and 2 as optional for an
instruction and it is assumed that a maximum of 1 operand can ever be
optional. This is not overly-problematic given that, for optional
pairs, the second optional operand is always found immediately after
the first. Thus, it suffices for us to flag that there is a second
optional operand. With this fact, we can infer its position in the
mnemonic from the position of the first (e.g. if the second operand in
the mnemonic is optional, we know the third is too). We therefore
define the `F_OPD_PAIR_OPT' flag and calculate its position in the
mnemonic from the value encoded by the `F_OPD<n>_OPT' flag.
Another observation is that there is a tight coupling between default
values assigned to the two registers when one (or both) are omitted
from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero
register is specified), Xt2 defaults to the same value, otherwise Xt2
will be assigned Xt + 1. This meant that where you have default value
validation, in checking the second optional operand's value, it is
also necessary to look at the value assigned to the
previously-processed operand value before deciding its validity. Thus
`process_omitted_operand' needs not only access to its `operand'
argument, but also to the global `inst' struct.
2023-12-13 22:27:31 +08:00
|
|
|
|
if (opcode->flags & F_OPD_PAIR_OPT)
|
|
|
|
|
|
return (((opcode->flags >> 12) & 0x7) == idx
|
|
|
|
|
|
|| ((opcode->flags >> 12) & 0x7) == idx + 1);
|
TRUE/FALSE simplification
There is really no need to write code like "foo != 0 ? TRUE : FALSE"
unless we had stupidly defined FALSE as something other than 0 or TRUE
as something other than 1. The simpler "foo != 0" does just as well.
Similarly "(condition == TRUE)" or "(condition == FALSE) can be
simplified to "(condition)" and "(!condition)" respectively.
I'll note that there is reason to use "integer_expression != 0" when
assigning a bfd_boolean rather than the simpler "integer_expression",
if you expect the variable to have 0 or 1 value. It's probably even a
good idea to not rely on implicit conversion if bfd_boolean were _Bool.
bfd/
* aoutx.h (aout_link_write_symbols): Don't cast boolean expression
to bfd_boolean.
* elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans
against FALSE.
* elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE.
(is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE".
(is_reloc_SDA_relative, is_reloc_for_GOT): Likewise.
(is_reloc_for_PLT, is_reloc_for_TLS): Likewise.
* elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise.
* elf32-nds32.c (insert_nds32_elf_blank): Likewise.
* elf32-rx.c (rx_set_section_contents): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise.
* elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise.
* mach-o.c (bfd_mach_o_read_command): Likewise.
* targets.c (bfd_get_target_info): Likewise.
binutils/
* dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE".
* dwarf.c (read_and_display_attr_value): Likewise.
(display_debug_str_offsets): Likewise.
* objdump.c (dump_bfd): Likewise.
* readelf.c (dump_section_as_strings): Likewise.
(dump_section_as_bytes): Likewise.
gas/
* atof-generic.c (FALSE, TRUE): Don't define.
* config/obj-elf.h (FALSE, TRUE): Don't define.
* config/obj-som.h (FALSE, TRUE): Don't define.
* config/tc-hppa.h (FALSE, TRUE): Don't define.
* config/tc-pdp11.c (FALSE, TRUE): Don't define.
* config/tc-iq2000.h (obj_fix_adjustable): Delete.
* config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-mt.h (obj_fix_adjustable): Delete.
* config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-arc.c (parse_opcode_flags): Simplify boolean expression.
(relaxable_flag, relaxable_operand, assemble_insn): Likewise.
(tokenize_extregister): Likewise.
* config/tc-csky.c (parse_opcode, get_operand_value): Likewise.
(parse_operands_op, parse_operands, md_assemble): Likewise.
* config/tc-d10v.c (build_insn): Likewise.
* config/tc-score.c (s3_gen_insn_frag): Likewise.
* config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise.
* config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise.
* config/tc-z80.c (emit_byte): Likewise.
include/
* opcode/aarch64.h (alias_opcode_p): Simplify boolean expression.
(opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise.
(opcode_has_special_coder): Likewise.
ld/
* emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify
boolean expression.
* lexsup.c (parse_args): Likewise.
* pe-dll.c (pe_dll_id_target): Likewise.
opcodes/
* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
(fp_qualifier_p, get_data_pattern): Likewise.
(aarch64_get_operand_modifier_from_value): Likewise.
(aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
(operand_variant_qualifier_p): Likewise.
(qualifier_value_in_range_constraint_p): Likewise.
(aarch64_get_qualifier_esize): Likewise.
(aarch64_get_qualifier_nelem): Likewise.
(aarch64_get_qualifier_standard_value): Likewise.
(get_lower_bound, get_upper_bound): Likewise.
(aarch64_find_best_match, match_operands_qualifier): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
(operand_need_sign_extension, operand_need_shift_by_two): Likewise.
(operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
* arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
* tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
(print_insn_tic6x): Likewise.
2021-03-29 07:22:56 +08:00
|
|
|
|
return ((opcode->flags >> 12) & 0x7) == idx + 1;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static inline aarch64_insn
|
|
|
|
|
|
get_optional_operand_default_value (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
|
|
|
|
|
return (opcode->flags >> 15) & 0x1f;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static inline unsigned int
|
|
|
|
|
|
get_opcode_dependent_value (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
|
|
|
|
|
return (opcode->flags >> 24) & 0x7;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2024-07-08 23:36:44 +08:00
|
|
|
|
static inline bool
|
|
|
|
|
|
get_opcode_dependent_vg_status (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
|
|
|
|
|
return (opcode->flags >> 36) & 0x1;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
static inline bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
opcode_has_special_coder (const aarch64_opcode *opcode)
|
|
|
|
|
|
{
|
2014-09-03 21:40:41 +08:00
|
|
|
|
return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
|
2024-01-15 17:35:55 +08:00
|
|
|
|
| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND
|
2024-01-06 01:27:04 +08:00
|
|
|
|
| F_OPD_SIZE | F_RCPC3_SIZE)) != 0;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
struct aarch64_name_value_pair
|
|
|
|
|
|
{
|
|
|
|
|
|
const char * name;
|
|
|
|
|
|
aarch64_insn value;
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
|
|
|
|
|
|
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
|
2020-10-28 22:01:36 +08:00
|
|
|
|
extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
|
2012-08-13 22:52:54 +08:00
|
|
|
|
extern const struct aarch64_name_value_pair aarch64_prfops [32];
|
2015-12-11 18:11:27 +08:00
|
|
|
|
extern const struct aarch64_name_value_pair aarch64_hint_options [];
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
2020-08-11 00:44:02 +08:00
|
|
|
|
#define AARCH64_MAX_SYSREG_NAME_LEN 32
|
|
|
|
|
|
|
2013-11-06 04:54:22 +08:00
|
|
|
|
typedef struct
|
|
|
|
|
|
{
|
|
|
|
|
|
const char * name;
|
|
|
|
|
|
aarch64_insn value;
|
|
|
|
|
|
uint32_t flags;
|
2020-06-11 19:34:37 +08:00
|
|
|
|
|
|
|
|
|
|
/* A set of features, all of which are required for this system register to be
|
|
|
|
|
|
available. */
|
|
|
|
|
|
aarch64_feature_set features;
|
2013-11-06 04:54:22 +08:00
|
|
|
|
} aarch64_sys_reg;
|
|
|
|
|
|
|
|
|
|
|
|
extern const aarch64_sys_reg aarch64_sys_regs [];
|
2013-11-20 19:22:40 +08:00
|
|
|
|
extern const aarch64_sys_reg aarch64_pstatefields [];
|
2021-03-31 07:50:10 +08:00
|
|
|
|
extern bool aarch64_sys_reg_deprecated_p (const uint32_t);
|
2023-11-21 04:40:10 +08:00
|
|
|
|
extern bool aarch64_sys_reg_128bit_p (const uint32_t);
|
2023-10-02 16:51:27 +08:00
|
|
|
|
extern bool aarch64_sys_reg_alias_p (const uint32_t);
|
2021-03-31 07:50:10 +08:00
|
|
|
|
extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set,
|
|
|
|
|
|
const aarch64_sys_reg *);
|
2013-11-06 04:54:22 +08:00
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
typedef struct
|
|
|
|
|
|
{
|
2015-10-07 19:23:15 +08:00
|
|
|
|
const char *name;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
uint32_t value;
|
2015-12-11 00:31:35 +08:00
|
|
|
|
uint32_t flags ;
|
2024-01-15 19:19:48 +08:00
|
|
|
|
|
|
|
|
|
|
/* A set of features, all of which are required for this system instruction to be
|
|
|
|
|
|
available. */
|
|
|
|
|
|
aarch64_feature_set features;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
} aarch64_sys_ins_reg;
|
|
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
|
|
|
|
|
|
extern bool
|
2020-09-08 21:21:44 +08:00
|
|
|
|
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
|
2024-01-15 19:19:48 +08:00
|
|
|
|
const char *reg_name,
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
uint32_t, const aarch64_feature_set *);
|
2015-12-11 00:31:35 +08:00
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
|
|
|
|
|
|
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
|
|
|
|
|
|
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
|
|
|
|
|
|
extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
|
2018-09-26 17:52:51 +08:00
|
|
|
|
extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
/* Shift/extending operator kinds.
|
|
|
|
|
|
N.B. order is important; keep aarch64_operand_modifiers synced. */
|
|
|
|
|
|
enum aarch64_modifier_kind
|
|
|
|
|
|
{
|
|
|
|
|
|
AARCH64_MOD_NONE,
|
|
|
|
|
|
AARCH64_MOD_MSL,
|
|
|
|
|
|
AARCH64_MOD_ROR,
|
|
|
|
|
|
AARCH64_MOD_ASR,
|
|
|
|
|
|
AARCH64_MOD_LSR,
|
|
|
|
|
|
AARCH64_MOD_LSL,
|
|
|
|
|
|
AARCH64_MOD_UXTB,
|
|
|
|
|
|
AARCH64_MOD_UXTH,
|
|
|
|
|
|
AARCH64_MOD_UXTW,
|
|
|
|
|
|
AARCH64_MOD_UXTX,
|
|
|
|
|
|
AARCH64_MOD_SXTB,
|
|
|
|
|
|
AARCH64_MOD_SXTH,
|
|
|
|
|
|
AARCH64_MOD_SXTW,
|
|
|
|
|
|
AARCH64_MOD_SXTX,
|
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 23:55:22 +08:00
|
|
|
|
AARCH64_MOD_MUL,
|
[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:
[<base>, #<offset>, MUL VL]
This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.
For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
2016-09-21 23:56:15 +08:00
|
|
|
|
AARCH64_MOD_MUL_VL,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
aarch64_extend_operator_p (enum aarch64_modifier_kind);
|
|
|
|
|
|
|
|
|
|
|
|
enum aarch64_modifier_kind
|
|
|
|
|
|
aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
|
|
|
|
|
|
/* Condition. */
|
|
|
|
|
|
|
|
|
|
|
|
typedef struct
|
|
|
|
|
|
{
|
|
|
|
|
|
/* A list of names with the first one as the disassembly preference;
|
|
|
|
|
|
terminated by NULL if fewer than 3. */
|
[AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-22 00:09:59 +08:00
|
|
|
|
const char *names[4];
|
2012-08-13 22:52:54 +08:00
|
|
|
|
aarch64_insn value;
|
|
|
|
|
|
} aarch64_cond;
|
|
|
|
|
|
|
|
|
|
|
|
extern const aarch64_cond aarch64_conds[16];
|
|
|
|
|
|
|
|
|
|
|
|
const aarch64_cond* get_cond_from_value (aarch64_insn value);
|
|
|
|
|
|
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
|
|
|
|
|
|
|
2023-03-30 18:09:04 +08:00
|
|
|
|
/* Information about a reference to part of ZA. */
|
|
|
|
|
|
struct aarch64_indexed_za
|
|
|
|
|
|
{
|
2023-03-30 18:09:11 +08:00
|
|
|
|
/* Which tile is being accessed. Unused (and 0) for an index into ZA. */
|
|
|
|
|
|
int regno;
|
|
|
|
|
|
|
2023-03-30 18:09:04 +08:00
|
|
|
|
struct
|
|
|
|
|
|
{
|
2023-03-30 18:09:11 +08:00
|
|
|
|
/* The 32-bit index register. */
|
|
|
|
|
|
int regno;
|
|
|
|
|
|
|
|
|
|
|
|
/* The first (or only) immediate offset. */
|
|
|
|
|
|
int64_t imm;
|
|
|
|
|
|
|
|
|
|
|
|
/* The last immediate offset minus the first immediate offset.
|
|
|
|
|
|
Unlike the range size, this is guaranteed not to overflow
|
|
|
|
|
|
when the end offset > the start offset. */
|
|
|
|
|
|
uint64_t countm1;
|
2023-03-30 18:09:04 +08:00
|
|
|
|
} index;
|
2023-03-30 18:09:11 +08:00
|
|
|
|
|
|
|
|
|
|
/* The vector group size, or 0 if none. */
|
2023-03-30 18:09:11 +08:00
|
|
|
|
unsigned group_size : 8;
|
2023-03-30 18:09:11 +08:00
|
|
|
|
|
|
|
|
|
|
/* True if a tile access is vertical, false if it is horizontal.
|
|
|
|
|
|
Unused (and 0) for an index into ZA. */
|
|
|
|
|
|
unsigned v : 1;
|
2023-03-30 18:09:04 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
2023-03-30 18:09:10 +08:00
|
|
|
|
/* Information about a list of registers. */
|
|
|
|
|
|
struct aarch64_reglist
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned first_regno : 8;
|
|
|
|
|
|
unsigned num_regs : 8;
|
|
|
|
|
|
/* The difference between the nth and the n+1th register. */
|
|
|
|
|
|
unsigned stride : 8;
|
|
|
|
|
|
/* 1 if it is a list of reg element. */
|
|
|
|
|
|
unsigned has_index : 1;
|
|
|
|
|
|
/* Lane index; valid only when has_index is 1. */
|
|
|
|
|
|
int64_t index;
|
2023-03-31 00:01:30 +08:00
|
|
|
|
};
|
2023-03-30 18:09:10 +08:00
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* Structure representing an operand. */
|
|
|
|
|
|
|
|
|
|
|
|
struct aarch64_opnd_info
|
|
|
|
|
|
{
|
|
|
|
|
|
enum aarch64_opnd type;
|
|
|
|
|
|
aarch64_opnd_qualifier_t qualifier;
|
|
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
|
|
|
|
union
|
|
|
|
|
|
{
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned regno;
|
|
|
|
|
|
} reg;
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
2016-06-28 16:21:04 +08:00
|
|
|
|
unsigned int regno;
|
|
|
|
|
|
int64_t index;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
} reglane;
|
|
|
|
|
|
/* e.g. LVn. */
|
2023-03-30 18:09:10 +08:00
|
|
|
|
struct aarch64_reglist reglist;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* e.g. immediate or pc relative address offset. */
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
unsigned is_fp : 1;
|
|
|
|
|
|
} imm;
|
|
|
|
|
|
/* e.g. address in STR (register offset). */
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned base_regno;
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
|
|
|
|
|
union
|
|
|
|
|
|
{
|
|
|
|
|
|
int imm;
|
|
|
|
|
|
unsigned regno;
|
|
|
|
|
|
};
|
|
|
|
|
|
unsigned is_reg;
|
|
|
|
|
|
} offset;
|
|
|
|
|
|
unsigned pcrel : 1; /* PC-relative. */
|
|
|
|
|
|
unsigned writeback : 1;
|
|
|
|
|
|
unsigned preind : 1; /* Pre-indexed. */
|
|
|
|
|
|
unsigned postind : 1; /* Post-indexed. */
|
|
|
|
|
|
} addr;
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 23:11:42 +08:00
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struct
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{
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/* The encoding of the system register. */
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aarch64_insn value;
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/* The system register flags. */
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uint32_t flags;
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} sysreg;
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2021-11-18 03:31:25 +08:00
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/* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */
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2023-03-30 18:09:04 +08:00
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struct aarch64_indexed_za indexed_za;
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2021-11-18 03:31:25 +08:00
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2012-08-13 22:52:54 +08:00
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const aarch64_cond *cond;
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/* The encoding of the PSTATE field. */
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aarch64_insn pstatefield;
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const aarch64_sys_ins_reg *sysins_op;
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const struct aarch64_name_value_pair *barrier;
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2015-12-11 18:11:27 +08:00
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const struct aarch64_name_value_pair *hint_option;
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2012-08-13 22:52:54 +08:00
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const struct aarch64_name_value_pair *prfop;
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};
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/* Operand shifter; in use when the operand is a register offset address,
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add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
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struct
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{
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enum aarch64_modifier_kind kind;
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unsigned operator_present: 1; /* Only valid during encoding. */
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/* Value of the 'S' field in ld/st reg offset; used only in decoding. */
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unsigned amount_present: 1;
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[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 23:55:22 +08:00
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int64_t amount;
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2012-08-13 22:52:54 +08:00
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} shifter;
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unsigned skip:1; /* Operand is not completed if there is a fixup needed
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to be done on it. In some (but not all) of these
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cases, we need to tell libopcodes to skip the
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constraint checking and the encoding for this
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operand, so that the libopcodes can pick up the
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right opcode before the operand is fixed-up. This
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flag should only be used during the
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assembling/encoding. */
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unsigned present:1; /* Whether this operand is present in the assembly
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line; not used during the disassembly. */
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};
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typedef struct aarch64_opnd_info aarch64_opnd_info;
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/* Structure representing an instruction.
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It is used during both the assembling and disassembling. The assembler
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fills an aarch64_inst after a successful parsing and then passes it to the
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encoding routine to do the encoding. During the disassembling, the
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disassembler calls the decoding routine to decode a binary instruction; on a
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successful return, such a structure will be filled with information of the
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instruction; then the disassembler uses the information to print out the
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instruction. */
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struct aarch64_inst
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{
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/* The value of the binary instruction. */
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aarch64_insn value;
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/* Corresponding opcode entry. */
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const aarch64_opcode *opcode;
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/* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
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const aarch64_cond *cond;
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/* Operands information. */
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aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
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};
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[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
2018-09-26 18:00:49 +08:00
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/* Defining the HINT #imm values for the aarch64_hint_options. */
|
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#define HINT_OPD_CSYNC 0x11
|
2023-11-02 21:07:29 +08:00
|
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|
#define HINT_OPD_DSYNC 0x13
|
[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
2018-09-26 18:00:49 +08:00
|
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#define HINT_OPD_C 0x22
|
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#define HINT_OPD_J 0x24
|
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#define HINT_OPD_JC 0x26
|
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#define HINT_OPD_NULL 0x00
|
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2012-08-13 22:52:54 +08:00
|
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/* Diagnosis related declaration and interface. */
|
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/* Operand error kind enumerators.
|
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AARCH64_OPDE_RECOVERABLE
|
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|
Less severe error found during the parsing, very possibly because that
|
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|
GAS has picked up a wrong instruction template for the parsing.
|
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|
aarch64: Enforce P/M/E order for MOPS instructions
The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02 23:00:57 +08:00
|
|
|
|
AARCH64_OPDE_A_SHOULD_FOLLOW_B
|
|
|
|
|
|
The instruction forms (or is expected to form) part of a sequence,
|
|
|
|
|
|
but the preceding instruction in the sequence wasn't the expected one.
|
|
|
|
|
|
The message refers to two strings: the name of the current instruction,
|
|
|
|
|
|
followed by the name of the expected preceding instruction.
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPDE_EXPECTED_A_AFTER_B
|
|
|
|
|
|
Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus
|
|
|
|
|
|
so that the current instruction is assumed to be the incorrect one:
|
|
|
|
|
|
"since the previous instruction was B, the current one should be A".
|
|
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPDE_SYNTAX_ERROR
|
|
|
|
|
|
General syntax error; it can be either a user error, or simply because
|
|
|
|
|
|
that GAS is trying a wrong instruction template.
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPDE_FATAL_SYNTAX_ERROR
|
|
|
|
|
|
Definitely a user syntax error.
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPDE_INVALID_VARIANT
|
|
|
|
|
|
No syntax error, but the operands are not a valid combination, e.g.
|
|
|
|
|
|
FMOV D0,S0
|
|
|
|
|
|
|
2023-03-30 18:09:07 +08:00
|
|
|
|
The following errors are only reported against an asm string that is
|
|
|
|
|
|
syntactically valid and that has valid operand qualifiers.
|
|
|
|
|
|
|
2023-03-30 18:09:11 +08:00
|
|
|
|
AARCH64_OPDE_INVALID_VG_SIZE
|
|
|
|
|
|
Error about a "VGx<n>" modifier in a ZA index not having the
|
|
|
|
|
|
correct <n>. This error effectively forms a pair with
|
|
|
|
|
|
AARCH64_OPDE_REG_LIST_LENGTH, since both errors relate to the number
|
|
|
|
|
|
of vectors that an instruction operates on. However, the "VGx<n>"
|
|
|
|
|
|
modifier is optional, whereas a register list always has a known
|
|
|
|
|
|
and explicit length. It therefore seems better to place more
|
|
|
|
|
|
importance on the register list length when selecting an opcode table
|
|
|
|
|
|
entry. This in turn means that having an incorrect register length
|
|
|
|
|
|
should be more severe than having an incorrect "VGx<n>".
|
|
|
|
|
|
|
2023-03-30 18:09:10 +08:00
|
|
|
|
AARCH64_OPDE_REG_LIST_LENGTH
|
|
|
|
|
|
Error about a register list operand having an unexpected number of
|
2023-03-30 18:09:07 +08:00
|
|
|
|
registers. This error is low severity because there might be another
|
|
|
|
|
|
opcode entry that supports the given number of registers.
|
|
|
|
|
|
|
2023-03-30 18:09:10 +08:00
|
|
|
|
AARCH64_OPDE_REG_LIST_STRIDE
|
|
|
|
|
|
Error about a register list operand having the correct number
|
|
|
|
|
|
(and type) of registers, but an unexpected stride. This error is
|
|
|
|
|
|
more severe than AARCH64_OPDE_REG_LIST_LENGTH because it implies
|
|
|
|
|
|
that the length is known to be correct. However, it is lower than
|
|
|
|
|
|
many other errors, since some instructions have forms that share
|
|
|
|
|
|
the same number of registers but have different strides.
|
|
|
|
|
|
|
2021-11-18 04:02:06 +08:00
|
|
|
|
AARCH64_OPDE_UNTIED_IMMS
|
|
|
|
|
|
The asm failed to use the same immediate for a destination operand
|
|
|
|
|
|
and a tied source operand.
|
|
|
|
|
|
|
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 23:52:30 +08:00
|
|
|
|
AARCH64_OPDE_UNTIED_OPERAND
|
|
|
|
|
|
The asm failed to use the same register for a destination operand
|
|
|
|
|
|
and a tied source operand.
|
|
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPDE_OUT_OF_RANGE
|
|
|
|
|
|
Error about some immediate value out of a valid range.
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPDE_UNALIGNED
|
|
|
|
|
|
Error about some immediate value not properly aligned (i.e. not being a
|
|
|
|
|
|
multiple times of a certain value).
|
|
|
|
|
|
|
|
|
|
|
|
AARCH64_OPDE_OTHER_ERROR
|
|
|
|
|
|
Error of the highest severity and used for any severe issue that does not
|
|
|
|
|
|
fall into any of the above categories.
|
|
|
|
|
|
|
2023-03-30 18:09:07 +08:00
|
|
|
|
AARCH64_OPDE_INVALID_REGNO
|
|
|
|
|
|
A register was syntactically valid and had the right type, but it was
|
|
|
|
|
|
outside the range supported by the associated operand field. This is
|
|
|
|
|
|
a high severity error because there are currently no instructions that
|
|
|
|
|
|
would accept the operands that precede the erroneous one (if any) and
|
|
|
|
|
|
yet still accept a wider range of registers.
|
|
|
|
|
|
|
aarch64: Enforce P/M/E order for MOPS instructions
The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02 23:00:57 +08:00
|
|
|
|
AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and
|
|
|
|
|
|
AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
|
|
|
|
|
|
only libopcodes has the information about the valid variants of each
|
|
|
|
|
|
instruction.
|
|
|
|
|
|
|
|
|
|
|
|
The enumerators have an increasing severity. This is helpful when there are
|
|
|
|
|
|
multiple instruction templates available for a given mnemonic name (e.g.
|
|
|
|
|
|
FMOV); this mechanism will help choose the most suitable template from which
|
2023-03-30 18:09:07 +08:00
|
|
|
|
the generated diagnostics can most closely describe the issues, if any.
|
|
|
|
|
|
|
|
|
|
|
|
This enum needs to be kept up-to-date with operand_mismatch_kind_names
|
|
|
|
|
|
in tc-aarch64.c. */
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
enum aarch64_operand_error_kind
|
|
|
|
|
|
{
|
|
|
|
|
|
AARCH64_OPDE_NIL,
|
|
|
|
|
|
AARCH64_OPDE_RECOVERABLE,
|
aarch64: Enforce P/M/E order for MOPS instructions
The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02 23:00:57 +08:00
|
|
|
|
AARCH64_OPDE_A_SHOULD_FOLLOW_B,
|
|
|
|
|
|
AARCH64_OPDE_EXPECTED_A_AFTER_B,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPDE_SYNTAX_ERROR,
|
|
|
|
|
|
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
|
|
|
|
|
|
AARCH64_OPDE_INVALID_VARIANT,
|
2023-03-30 18:09:11 +08:00
|
|
|
|
AARCH64_OPDE_INVALID_VG_SIZE,
|
2023-03-30 18:09:10 +08:00
|
|
|
|
AARCH64_OPDE_REG_LIST_LENGTH,
|
|
|
|
|
|
AARCH64_OPDE_REG_LIST_STRIDE,
|
2021-11-18 04:02:06 +08:00
|
|
|
|
AARCH64_OPDE_UNTIED_IMMS,
|
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 23:52:30 +08:00
|
|
|
|
AARCH64_OPDE_UNTIED_OPERAND,
|
2012-08-13 22:52:54 +08:00
|
|
|
|
AARCH64_OPDE_OUT_OF_RANGE,
|
|
|
|
|
|
AARCH64_OPDE_UNALIGNED,
|
2023-03-30 18:09:07 +08:00
|
|
|
|
AARCH64_OPDE_OTHER_ERROR,
|
|
|
|
|
|
AARCH64_OPDE_INVALID_REGNO
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* N.B. GAS assumes that this structure work well with shallow copy. */
|
|
|
|
|
|
struct aarch64_operand_error
|
|
|
|
|
|
{
|
|
|
|
|
|
enum aarch64_operand_error_kind kind;
|
|
|
|
|
|
int index;
|
|
|
|
|
|
const char *error;
|
aarch64: Enforce P/M/E order for MOPS instructions
The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02 23:00:57 +08:00
|
|
|
|
/* Some data for extra information. */
|
|
|
|
|
|
union {
|
|
|
|
|
|
int i;
|
|
|
|
|
|
const char *s;
|
|
|
|
|
|
} data[3];
|
2021-03-31 07:50:10 +08:00
|
|
|
|
bool non_fatal;
|
2012-08-13 22:52:54 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
2018-10-04 01:27:52 +08:00
|
|
|
|
/* AArch64 sequence structure used to track instructions with F_SCAN
|
|
|
|
|
|
dependencies for both assembler and disassembler. */
|
|
|
|
|
|
struct aarch64_instr_sequence
|
|
|
|
|
|
{
|
2021-12-02 23:00:56 +08:00
|
|
|
|
/* The instructions in the sequence, starting with the one that
|
|
|
|
|
|
caused it to be opened. */
|
2018-10-04 01:27:52 +08:00
|
|
|
|
aarch64_inst *instr;
|
|
|
|
|
|
/* The number of instructions already in the sequence. */
|
2021-12-02 23:00:56 +08:00
|
|
|
|
int num_added_insns;
|
|
|
|
|
|
/* The number of instructions allocated to the sequence. */
|
|
|
|
|
|
int num_allocated_insns;
|
2018-10-04 01:27:52 +08:00
|
|
|
|
};
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
/* Encoding entrypoint. */
|
|
|
|
|
|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
extern bool
|
2012-08-13 22:52:54 +08:00
|
|
|
|
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
|
|
|
|
|
|
aarch64_insn *, aarch64_opnd_qualifier_t *,
|
2018-10-04 01:27:52 +08:00
|
|
|
|
aarch64_operand_error *, aarch64_instr_sequence *);
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
|
|
|
extern const aarch64_opcode *
|
|
|
|
|
|
aarch64_replace_opcode (struct aarch64_inst *,
|
|
|
|
|
|
const aarch64_opcode *);
|
|
|
|
|
|
|
|
|
|
|
|
/* Given the opcode enumerator OP, return the pointer to the corresponding
|
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opcode entry. */
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extern const aarch64_opcode *
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aarch64_get_opcode (enum aarch64_op);
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libopcodes/aarch64: add support for disassembler styling
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
2022-04-28 20:31:07 +08:00
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/* An instance of this structure is passed to aarch64_print_operand, and
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the callback within this structure is used to apply styling to the
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disassembler output. This structure encapsulates the callback and a
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state pointer. */
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struct aarch64_styler
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{
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/* The callback used to apply styling. Returns a string created from FMT
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and ARGS with STYLE applied to the string. STYLER is a pointer back
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to this object so that the callback can access the state member.
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The string returned from this callback must remain valid until the
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call to aarch64_print_operand has completed. */
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const char *(*apply_style) (struct aarch64_styler *styler,
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enum disassembler_style style,
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const char *fmt,
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va_list args);
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/* A pointer to a state object which can be used by the apply_style
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callback function. */
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void *state;
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};
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2012-08-13 22:52:54 +08:00
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/* Generate the string representation of an operand. */
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extern void
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aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
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2018-05-15 23:34:54 +08:00
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const aarch64_opnd_info *, int, int *, bfd_vma *,
|
opcodes/aarch64: split off creation of comment text in disassembler
The function aarch64_print_operand (aarch64-opc.c) is responsible for
converting an instruction operand into the textual representation of
that operand.
In some cases, a comment is included in the operand representation,
though this (currently) only happens for the last operand of the
instruction.
In a future commit I would like to enable the new libopcodes styling
for AArch64, this will allow objdump and GDB[1] to syntax highlight
the disassembler output, however, having operands and comments
combined in a single string like this makes such styling harder.
In this commit, I propose to extend aarch64_print_operand to take a
second buffer. Any comments for the instruction are written into this
extra buffer. The two callers of aarch64_print_operand are then
updated to pass an extra buffer, and print any resulting comment.
In this commit no styling is added, that will come later. However, I
have adjusted the output slightly. Before this commit some comments
would be separated from the instruction operands with a tab character,
while in other cases the comment was separated with two single spaces.
After this commit I use a single tab character in all cases. This
means a few test cases needed updated. If people would prefer me to
move everyone to use the two spaces, then just let me know. Or maybe
there was a good reason why we used a mix of styles, I could probably
figure out a way to maintain the old output exactly if that is
critical.
Other than that, there should be no user visible changes after this
commit.
[1] GDB patches have not been merged yet, but have been posted to the
GDB mailing list:
https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-16 20:46:41 +08:00
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char **, char *, size_t,
|
libopcodes/aarch64: add support for disassembler styling
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
2022-04-28 20:31:07 +08:00
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aarch64_feature_set features,
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struct aarch64_styler *styler);
|
2012-08-13 22:52:54 +08:00
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/* Miscellaneous interface. */
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extern int
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aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
|
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|
extern aarch64_opnd_qualifier_t
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aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
|
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|
|
|
|
const aarch64_opnd_qualifier_t, int);
|
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|
2021-03-31 07:50:10 +08:00
|
|
|
|
extern bool
|
2018-10-04 01:38:42 +08:00
|
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|
|
aarch64_is_destructive_by_operands (const aarch64_opcode *);
|
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|
2012-08-13 22:52:54 +08:00
|
|
|
|
extern int
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aarch64_num_of_operands (const aarch64_opcode *);
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|
extern int
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aarch64_stack_pointer_p (const aarch64_opnd_info *);
|
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|
2015-10-02 22:39:26 +08:00
|
|
|
|
extern int
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|
|
aarch64_zero_register_p (const aarch64_opnd_info *);
|
2012-08-13 22:52:54 +08:00
|
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|
|
2018-10-04 01:35:15 +08:00
|
|
|
|
extern enum err_type
|
2021-03-31 07:50:10 +08:00
|
|
|
|
aarch64_decode_insn (aarch64_insn, aarch64_inst *, bool,
|
2018-10-04 01:38:42 +08:00
|
|
|
|
aarch64_operand_error *);
|
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|
|
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|
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|
|
extern void
|
|
|
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|
|
init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
|
2015-10-02 18:36:00 +08:00
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
/* Given an operand qualifier, return the expected data element size
|
|
|
|
|
|
of a qualified operand. */
|
|
|
|
|
|
extern unsigned char
|
|
|
|
|
|
aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
|
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|
|
|
|
|
|
|
|
|
extern enum aarch64_operand_class
|
|
|
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|
|
aarch64_get_operand_class (enum aarch64_opnd);
|
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|
|
extern const char *
|
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|
aarch64_get_operand_name (enum aarch64_opnd);
|
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|
|
extern const char *
|
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|
|
aarch64_get_operand_desc (enum aarch64_opnd);
|
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|
|
2021-03-31 07:50:10 +08:00
|
|
|
|
extern bool
|
[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
|
|
|
|
aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
|
|
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|
|
2023-03-30 18:09:09 +08:00
|
|
|
|
extern bool
|
aarch64: Restructure feature flag handling
The AArch64 feature-flag code is currently limited to a maximum
of 64 features. This patch reworks it so that the limit can be
increased more easily. The basic idea is:
(1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum
counting bit positions.
(2) Make the feature-list macros take an array index argument
(currently always 0). The macros then return the
aarch64_feature_set contents for that array index.
An N-element array would then be initialised as:
{ MACRO (0), ..., MACRO (N - 1) }
(3) Provide convenience macros for initialising an
aarch64_feature_set for:
- a single feature
- a list of individual features
- an architecture version
- an architecture version + a list of additional features
(2) and (3) use the preprocessor to generate static initialisers.
The main restriction was that uses of the same preprocessor macro
cannot be nested. So if a macro wants to do something for N individual
arguments, it needs to use a chain of N macros to do it. There then
needs to be a way of deriving N, as a preprocessor token suitable for
pasting.
The easiest way of doing that was to precede each list of features
by the number of features in the list. So an aarch64_feature_set
initialiser for three features A, B and C would be written:
AARCH64_FEATURES (3, A, B, C)
This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a
synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-26 22:01:21 +08:00
|
|
|
|
aarch64_cpu_supports_inst_p (aarch64_feature_set, aarch64_inst *);
|
2023-03-30 18:09:09 +08:00
|
|
|
|
|
2024-01-10 00:22:07 +08:00
|
|
|
|
extern int
|
|
|
|
|
|
calc_ldst_datasize (const aarch64_opnd_info *opnds);
|
|
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
#ifdef DEBUG_AARCH64
|
|
|
|
|
|
extern int debug_dump;
|
|
|
|
|
|
|
|
|
|
|
|
extern void
|
|
|
|
|
|
aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
|
|
|
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|
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|
|
#define DEBUG_TRACE(M, ...) \
|
|
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|
|
|
{ \
|
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|
|
|
|
if (debug_dump) \
|
|
|
|
|
|
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
|
|
|
|
|
|
}
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|
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|
|
#define DEBUG_TRACE_IF(C, M, ...) \
|
|
|
|
|
|
{ \
|
|
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|
|
|
if (debug_dump && (C)) \
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|
|
|
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
|
|
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|
|
|
}
|
|
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|
|
|
#else /* !DEBUG_AARCH64 */
|
|
|
|
|
|
#define DEBUG_TRACE(M, ...) ;
|
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|
|
#define DEBUG_TRACE_IF(C, M, ...) ;
|
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|
|
#endif /* DEBUG_AARCH64 */
|
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|
2016-09-21 23:54:53 +08:00
|
|
|
|
extern const char *const aarch64_sve_pattern_array[32];
|
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|
|
extern const char *const aarch64_sve_prfop_array[16];
|
2023-03-30 18:09:18 +08:00
|
|
|
|
extern const char *const aarch64_rprfmop_array[64];
|
2023-03-30 18:09:12 +08:00
|
|
|
|
extern const char *const aarch64_sme_vlxn_array[2];
|
2024-06-07 21:59:02 +08:00
|
|
|
|
extern const char *const aarch64_brbop_array[2];
|
2016-09-21 23:54:53 +08:00
|
|
|
|
|
2015-10-07 19:35:46 +08:00
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
|
}
|
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|
|
#endif
|
|
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|
|
2012-08-13 22:52:54 +08:00
|
|
|
|
#endif /* OPCODE_AARCH64_H */
|
