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binutils-gdb/gdb/riscv-tdep.h

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Minor formatting fixes in riscv-tdep.h This fixes some minor formatting issues in riscv-tdep.h, including one pointed out by ARI. ChangeLog 2018-08-09 Tom Tromey <tom@tromey.com> * riscv-tdep.h: Minor formatting fixes.
2018-08-10 00:46:01 +08:00
/* Target-dependent header for the RISC-V architecture, for GDB, the
GNU Debugger.
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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Copyright (C) 2018 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef RISCV_TDEP_H
#define RISCV_TDEP_H
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
#include "arch/riscv.h"
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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/* RiscV register numbers. */
enum
{
RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
RISCV_RA_REGNUM = 1, /* Return Address. */
RISCV_SP_REGNUM = 2, /* Stack Pointer. */
RISCV_GP_REGNUM = 3, /* Global Pointer. */
RISCV_TP_REGNUM = 4, /* Thread Pointer. */
RISCV_FP_REGNUM = 8, /* Frame Pointer. */
RISCV_A0_REGNUM = 10, /* First argument. */
RISCV_A1_REGNUM = 11, /* Second argument. */
RISCV_PC_REGNUM = 32, /* Program Counter. */
gdb/riscv: Provide non-DWARF stack unwinder Collects information during the prologue scan and uses this to unwind registers when no DWARF information is available. This patch has been tested by disabling the DWARF stack unwinders, and running the complete GDB testsuite against a range of RISC-V targets. The results are comparable to running with the DWARF unwinders in place. gdb/ChangeLog: * riscv-tdep.c: Add 'prologue-value.h' include. (struct riscv_unwind_cache): New struct. (riscv_debug_unwinder): New global. (riscv_scan_prologue): Update arguments, capture register details from prologue scan. (riscv_skip_prologue): Reformat arguments line, move end of prologue calculation into riscv_scan_prologue. (riscv_frame_cache): Update return type, create riscv_unwind_cache, scan the prologue, and fill in remaining cache details. (riscv_frame_this_id): Use frame id computed in riscv_frame_cache. (riscv_frame_prev_register): Use the trad_frame within the riscv_unwind_cache. (_initialize_riscv_tdep): Add 'set/show debug riscv unwinder' flag.
2018-07-17 22:22:39 +08:00
RISCV_NUM_INTEGER_REGS = 32,
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
RISCV_FA0_REGNUM = 43,
RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
Minor formatting fixes in riscv-tdep.h This fixes some minor formatting issues in riscv-tdep.h, including one pointed out by ARI. ChangeLog 2018-08-09 Tom Tromey <tom@tromey.com> * riscv-tdep.h: Minor formatting fixes.
2018-08-10 00:46:01 +08:00
#define DECLARE_CSR(name, num) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
RISCV_LAST_CSR_REGNUM = 4160,
RISC-V: Correct legacy misa register number. gdb/ * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of RISCV_LAST_FP_REGNUM + 1. (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.
2018-07-18 00:42:23 +08:00
RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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RISCV_PRIV_REGNUM = 4161,
RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
};
/* RISC-V specific per-architecture information. */
struct gdbarch_tdep
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
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/* Features about the target that impact how the gdbarch is configured.
Two gdbarch instances are compatible only if this field matches. */
struct riscv_gdbarch_features features;
RISC-V: Print FP regs as union of float types. A 64-bit FP register can hold either a single or double float value, so print it as both types by using a union type for FP registers. Likewise for 128-bit regs which can also hold long double. gdb/ * riscv-tdep.c (riscv_fpreg_d_type, riscv_fpreg_q_type): New. (riscv_register_type): Use them. (riscv_print_one_register_info): Handle union of floats same as float. * riscv-tdep.h (struct gdbarch_tdep): Add riscv_fpreg_d_type and riscv_fpreg_q_type fields.
2018-10-23 05:10:13 +08:00
/* ISA-specific data types. */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
struct type *riscv_fpreg_d_type = nullptr;
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
2017-11-10 04:59:13 +08:00
};
RISC-V: Linux signal frame support. Make riscv_isa_flen available to the linux native code, and clean up duplicate comments. gdb/ * riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment. (riscv_isa_flen): Likewise. Drop static. * riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here. (riscv_isa_flen): Likewise.
2018-10-27 01:29:46 +08:00
/* Return the width in bytes of the general purpose registers for GDBARCH.
Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
RV128. */
RISC-V: Make riscv_isa_xlen a global function. This allows the function to be used from riscv OS files, which also need to depend on XLEN size. gdb/ * riscv-tdep.c (riscv_isa_xlen): Drop static. * riscv-tdep.h (riscv_isa_xlen): Add extern declaration.
2018-08-09 01:48:09 +08:00
extern int riscv_isa_xlen (struct gdbarch *gdbarch);
RISC-V: Linux signal frame support. Make riscv_isa_flen available to the linux native code, and clean up duplicate comments. gdb/ * riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment. (riscv_isa_flen): Likewise. Drop static. * riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here. (riscv_isa_flen): Likewise.
2018-10-27 01:29:46 +08:00
/* Return the width in bytes of the floating point registers for GDBARCH.
If this architecture has no floating point registers, then return 0.
Possible values are 4, 8, or 16 for depending on which of single, double
or quad floating point support is available. */
extern int riscv_isa_flen (struct gdbarch *gdbarch);
RISC-V: Add software single step support. This adds software single step support that is needed by the linux native port. This is modeled after equivalent code in the MIPS port. This also fixes a few bugs in the compressed instruction decode support. Some instructions are RV32/RV64 specific, and this wasn't being checked. Also, a few instructions were accidentally using the non-compressed is_* function. This has been tested on a HiFive Unleashed running Fedora, by putting a breakpoint on start, typing stepi, and then holding down the return key until it finishes, and observing that I see everything I expect to see along the way. There is a problem in _dl_addr where I get into an infinite loop, but it seems to be some synchronization code that doesn't agree with single step, so I have to find the end of the loop, put a breakpoint there, continue, and then single step again until the end. gdb/ * riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes. (decode_register_index_short): New. (decode_j_type_insn, decode_cj_type_insn): New. (decode_b_type_insn, decode_cb_type_insn): New. (riscv_insn::decode): Add support for jumps, branches, lr, and sc. New local xlen. Check xlen when decoding ambiguous compressed insns. In compressed decode, use is_c_lui_insn instead of is_lui_insn, and is_c_sw_insn instead of is_sw_insn. (riscv_next_pc, riscv_next_pc_atomic_sequence): New. (riscv_software_single_step): New. * riscv-tdep.h (riscv_software_single_step): Declare.
2018-08-09 01:53:12 +08:00
/* Single step based on where the current instruction will take us. */
Minor formatting fixes in riscv-tdep.h This fixes some minor formatting issues in riscv-tdep.h, including one pointed out by ARI. ChangeLog 2018-08-09 Tom Tromey <tom@tromey.com> * riscv-tdep.h: Minor formatting fixes.
2018-08-10 00:46:01 +08:00
extern std::vector<CORE_ADDR> riscv_software_single_step
(struct regcache *regcache);
RISC-V: Add software single step support. This adds software single step support that is needed by the linux native port. This is modeled after equivalent code in the MIPS port. This also fixes a few bugs in the compressed instruction decode support. Some instructions are RV32/RV64 specific, and this wasn't being checked. Also, a few instructions were accidentally using the non-compressed is_* function. This has been tested on a HiFive Unleashed running Fedora, by putting a breakpoint on start, typing stepi, and then holding down the return key until it finishes, and observing that I see everything I expect to see along the way. There is a problem in _dl_addr where I get into an infinite loop, but it seems to be some synchronization code that doesn't agree with single step, so I have to find the end of the loop, put a breakpoint there, continue, and then single step again until the end. gdb/ * riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes. (decode_register_index_short): New. (decode_j_type_insn, decode_cj_type_insn): New. (decode_b_type_insn, decode_cb_type_insn): New. (riscv_insn::decode): Add support for jumps, branches, lr, and sc. New local xlen. Check xlen when decoding ambiguous compressed insns. In compressed decode, use is_c_lui_insn instead of is_lui_insn, and is_c_sw_insn instead of is_sw_insn. (riscv_next_pc, riscv_next_pc_atomic_sequence): New. (riscv_software_single_step): New. * riscv-tdep.h (riscv_software_single_step): Declare.
2018-08-09 01:53:12 +08:00
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
2017-11-10 04:59:13 +08:00
#endif /* RISCV_TDEP_H */
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