binutils-gdb/sim/testsuite/v850/divq.cgs

# v850 bins
# mach: v850e3v5
# as: -mv850e3v5

	.include "testutils.inc"
	seti	0xfffffffb r11
	seti	0x32 r10
	divq	r11, r10, r11
	reg	r10, 0xfffffff6
	reg	r11, 0x0
	pass
Fix for v850e divq instruction This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch. 2022-04-06 23:10:40 +08:00			`# v850 bins`
			`# mach: v850e3v5`
			`# as: -mv850e3v5`

			`.include "testutils.inc"`
			`seti 0xfffffffb r11`
			`seti 0x32 r10`
			`divq r11, r10, r11`
			`reg r10, 0xfffffff6`
			`reg r11, 0x0`
			`pass`