2003-01-16 12:08:47 +08:00
|
|
|
/* PPC64 ELF support for BFD.
|
2022-01-02 06:30:17 +08:00
|
|
|
Copyright (C) 2003-2022 Free Software Foundation, Inc.
|
2003-01-16 12:08:47 +08:00
|
|
|
|
2010-04-15 18:26:09 +08:00
|
|
|
This file is part of BFD, the Binary File Descriptor library.
|
2003-01-16 12:08:47 +08:00
|
|
|
|
2010-04-15 18:26:09 +08:00
|
|
|
This program is free software; you can redistribute it and/or modify
|
|
|
|
|
it under the terms of the GNU General Public License as published by
|
|
|
|
|
the Free Software Foundation; either version 3 of the License, or
|
|
|
|
|
(at your option) any later version.
|
2003-01-16 12:08:47 +08:00
|
|
|
|
2010-04-15 18:26:09 +08:00
|
|
|
This program is distributed in the hope that it will be useful,
|
|
|
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
GNU General Public License for more details.
|
2003-01-16 12:08:47 +08:00
|
|
|
|
2010-04-15 18:26:09 +08:00
|
|
|
You should have received a copy of the GNU General Public License
|
|
|
|
|
along with this program; if not, write to the Free Software
|
|
|
|
|
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
|
|
|
|
MA 02110-1301, USA. */
|
2003-01-16 12:08:47 +08:00
|
|
|
|
|
|
|
|
#ifndef _ELF_PPC64_H
|
|
|
|
|
#define _ELF_PPC64_H
|
|
|
|
|
|
|
|
|
|
#include "elf/reloc-macros.h"
|
|
|
|
|
|
|
|
|
|
/* Relocations. */
|
|
|
|
|
START_RELOC_NUMBERS (elf_ppc64_reloc_type)
|
2003-02-04 22:48:36 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_NONE, 0)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR32, 1)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR24, 2)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16, 3)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_LO, 4)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HI, 5)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HA, 6)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR14, 7)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR14_BRTAKEN, 8)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR14_BRNTAKEN, 9)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL24, 10)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL14, 11)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL14_BRTAKEN, 12)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL14_BRNTAKEN, 13)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT16, 14)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT16_LO, 15)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT16_HI, 16)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT16_HA, 17)
|
2003-01-16 12:08:47 +08:00
|
|
|
/* 18 unused. 32-bit reloc is R_PPC_PLTREL24. */
|
2003-02-04 22:48:36 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_COPY, 19)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GLOB_DAT, 20)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_JMP_SLOT, 21)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_RELATIVE, 22)
|
2003-01-16 12:08:47 +08:00
|
|
|
/* 23 unused. 32-bit reloc is R_PPC_LOCAL24PC. */
|
2003-02-04 22:48:36 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_UADDR32, 24)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_UADDR16, 25)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL32, 26)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT32, 27)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTREL32, 28)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT16_LO, 29)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT16_HI, 30)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT16_HA, 31)
|
2003-01-16 12:08:47 +08:00
|
|
|
/* 32 unused. 32-bit reloc is R_PPC_SDAREL16. */
|
2003-02-04 22:48:36 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_SECTOFF, 33)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_SECTOFF_LO, 34)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_SECTOFF_HI, 35)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_SECTOFF_HA, 36)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL30, 37)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR64, 38)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHER, 39)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHERA, 40)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHEST, 41)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHESTA, 42)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_UADDR64, 43)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL64, 44)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT64, 45)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTREL64, 46)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC16, 47)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC16_LO, 48)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC16_HI, 49)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC16_HA, 50)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC, 51)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTGOT16, 52)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTGOT16_LO, 53)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTGOT16_HI, 54)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTGOT16_HA, 55)
|
2003-01-16 12:08:47 +08:00
|
|
|
|
2003-02-04 22:48:36 +08:00
|
|
|
/* The following relocs were added in the 64-bit PowerPC ELF ABI
|
|
|
|
|
revision 1.2. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_DS, 56)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_LO_DS, 57)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT16_DS, 58)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT16_LO_DS, 59)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT16_LO_DS, 60)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_SECTOFF_DS, 61)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_SECTOFF_LO_DS, 62)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC16_DS, 63)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TOC16_LO_DS, 64)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTGOT16_DS, 65)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTGOT16_LO_DS, 66)
|
|
|
|
|
|
|
|
|
|
/* Relocs added to support TLS. PowerPC64 ELF ABI revision 1.5. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TLS, 67)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPMOD64, 68)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16, 69)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_LO, 70)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HI, 71)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HA, 72)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL64, 73)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16, 74)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_LO, 75)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HI, 76)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HA, 77)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL64, 78)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSGD16, 79)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSGD16_LO, 80)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HI, 81)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HA, 82)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSLD16, 83)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSLD16_LO, 84)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HI, 85)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HA, 86)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TPREL16_DS, 87)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TPREL16_LO_DS, 88)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TPREL16_HI, 89)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TPREL16_HA, 90)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_DTPREL16_DS, 91)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_DTPREL16_LO_DS, 92)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HI, 93)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HA, 94)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_DS, 95)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_LO_DS, 96)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HIGHER, 97)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HIGHERA, 98)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HIGHEST, 99)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HIGHESTA, 100)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_DS, 101)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_LO_DS, 102)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HIGHER, 103)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HIGHERA, 104)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HIGHEST, 105)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HIGHESTA, 106)
|
2009-03-04 13:50:50 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_TLSGD, 107)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TLSLD, 108)
|
2011-10-10 21:21:07 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_TOCSAVE, 109)
|
2003-01-16 12:08:47 +08:00
|
|
|
|
Report overflow on PowerPC64 @h and @ha relocations.
This changes the behaviour of @h and @ha on PowerPC64 to report errors
on 32-bit overflow. The motivation for this change is that on
PowerPC64, most uses of @h and @ha modifiers and their corresponding
relocations are to build up 32-bit offsets. We'd like to know when
such offsets overflow. Only rarely do people use @h or @ha with the
high 32-bit modifiers to build a 64-bit constant. Those uses will now
need to use two new modifiers, @high and @higha, if the constant isn't
known at assembly time. For now, we won't report overflow at assembly
time..
This also fixes an error when applying some of the HIGHER and HIGHEST
relocations.
include/elf/
* ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
(IS_PPC64_TLS_RELOC): Match new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
Make all _HA and _HI relocs report signed overflow.
(ppc64_elf_reloc_type_lookup): Handle new relocs.
(must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
(dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
(ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (SEX16): Don't mask.
(REPORT_OVERFLOW_HI): Define as zero.
(ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha,
@tprel@high, and @tprel@higha modifiers.
(md_assemble): Ignore X_unsigned when applying 16-bit insn fields.
Add (disabled) code to check @h and @ha reloc overflow for powerpc64.
Handle new relocs.
(md_apply_fix): Similarly.
elfcpp/
* powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs.
(Target_powerpc::Scan::global, local): Likewise.
(Target_powerpc::Relocate::relocate): Likewise. Check for overflow
on all ppc64 @h and @ha relocs.
2013-10-29 14:23:25 +08:00
|
|
|
/* Added when HA and HI relocs were changed to report overflows. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGH, 110)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHA, 111)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HIGH, 112)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_TPREL16_HIGHA, 113)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HIGH, 114)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL16_HIGHA, 115)
|
|
|
|
|
|
2014-03-05 17:27:39 +08:00
|
|
|
/* Added for ELFv2. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL24_NOTOC, 116)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR64_LOCAL, 117)
|
2015-12-07 10:44:53 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_ENTRY, 118)
|
2014-03-05 17:27:39 +08:00
|
|
|
|
PowerPC inline PLT call support
In addition to the existing relocs we need two more to mark all
instructions in the call sequence, PLTCALL on the call itself (plus
the toc restore insn for ppc64), and PLTSEQ on others. All
relocations in a particular sequence have the same symbol.
Example ppc64 ELFv2 assembly:
.reloc .,R_PPC64_PLTSEQ,puts
std 2,24(1)
addis 12,2,puts@plt@ha # .reloc .,R_PPC64_PLT16_HA,puts
ld 12,puts@plt@l(12) # .reloc .,R_PPC64_PLT16_LO_DS,puts
.reloc .,R_PPC64_PLTSEQ,puts
mtctr 12
.reloc .,R_PPC64_PLTCALL,puts
bctrl
ld 2,24(1)
Example ppc32 -fPIC assembly:
addis 12,30,puts+32768@plt@ha # .reloc .,R_PPC_PLT16_HA,puts+0x8000
lwz 12,12,puts+32768@plt@l # .reloc .,R_PPC_PLT16_LO,puts+0x8000
.reloc .,R_PPC_PLTSEQ,puts+32768
mtctr 12
.reloc .,R_PPC_PLTCALL,puts+32768
bctrl
Marking sequences like this allows the linker to convert them to nops
and a direct call if the target symbol turns out to be local.
When the call is __tls_get_addr, each relocation shown above is paired
with an R_PPC*_TLSLD or R_PPC*_TLSGD reloc to additionally mark the
sequence for possible TLS optimization. The TLSLD or TLSGD relocs are
emitted first.
include/
* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add PLTSEQ and PLTCALL howtos.
(is_plt_seq_reloc): New function.
(ppc_elf_check_relocs): Handle PLTSEQ and PLTCALL relocs.
(ppc_elf_tls_optimize): Handle inline plt call sequence.
(ppc_elf_relax_section): Handle PLTCALL reloc.
(ppc_elf_relocate_section): Nop out inline plt call sequence when
resolving locally.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_PLTSEQ and
R_PPC64_PLTCALL entries. Comment R_PPC64_TOCSAVE.
(has_tls_get_addr_call): Correct comment.
(is_branch_reloc): Add PLTCALL.
(is_plt_seq_reloc): New function.
(ppc64_elf_check_relocs): Handle PLT16_LO_DS reloc. Set
has_tls_reloc for R_PPC64_TLSGD and R_PPC64_TLSLD. Create plt
entry for R_PPC64_PLTCALL.
(ppc64_elf_tls_optimize): Handle inline plt call sequence.
(ppc_type_of_stub): Handle PLTCALL reloc.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_relocate_section): Set "can_plt_call" for PLTCALL
reloc insn. Nop out inline plt call sequence when resolving
locally. Handle __tls_get_addr inline plt call optimization.
elfcpp/
* powerpc.h (R_POWERPC_PLTSEQ, R_POWERPC_PLTCALL): Define.
gold/
* powerpc.cc (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call):
Handle inline plt sequence relocs.
(Stub_table::Plt_stub_key::Plt_stub_key): Likewise.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
2018-04-09 07:55:10 +08:00
|
|
|
/* Marker reloc for inline plt call insns. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTSEQ, 119)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTCALL, 120)
|
|
|
|
|
|
2020-05-11 07:54:14 +08:00
|
|
|
/* Power10 support. */
|
PowerPC relocations for prefix insns
include/
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
(BFD_RELOC_PPC64_PLT_PCREL34),
(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
* elf64-ppc.c (PNOP): Define.
(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
relocs.
(ppc64_elf_prefix_reloc): New function.
(struct ppc_link_hash_table): Add notoc_plt.
(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set
has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle
possible need for dynamic relocs on non-pcrel powerxx relocs.
(dec_dynrel_count): Handle non-pcrel powerxx relocs.
(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_relocate_section): Handle new powerxx relocs.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2018-08-29 12:52:34 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_PLTSEQ_NOTOC, 121)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLTCALL_NOTOC, 122)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PCREL_OPT, 123)
|
PowerPC64 @notoc in non-power10 code
R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on
@notoc cals from non-power10 code in the rare case that using such a
construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas
rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch
instruction if power10 instructions are not enabled at that point.
The new relocation tells the linker to not use power10 instructions on
any stub emitted for that branch, unless overridden by
--power10-stubs=yes.
The current linker heuristic of only generating power10 instructions
for stubs if power10-only relocations are detected, continues to be
used.
include/
* elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc.
(ppc64_elf_reloc_type_lookup): Handle it.
(enum ppc_stub_type): Delete.
(enum ppc_stub_main_type, ppc_stub_sub_type): New.
(struct ppc_stub_type): New.
(struct ppc_stub_hash_entry): Use the above new type.
(struct ppc_link_hash_table): Update stub_count.
(is_branch_reloc, ppc64_elf_check_relocs),
(toc_adjusting_stub_needed): Handle new reloc.
(stub_hash_newfunc, select_alt_stub, ppc_merge_stub),
(ppc_type_of_stub, plt_stub_size, build_plt_stub),
(build_tls_get_addr_head, build_tls_get_addr_tail),
(ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs),
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new
reloc. Modify stub handling to suit new scheme.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled
return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc.
(fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle
BFD_RELOC_PPC64_REL24_P9NOTOC.
ld/
* testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
2021-11-10 06:19:05 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_REL24_P9NOTOC, 124)
|
PowerPC relocations for prefix insns
include/
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
(BFD_RELOC_PPC64_PLT_PCREL34),
(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
* elf64-ppc.c (PNOP): Define.
(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
relocs.
(ppc64_elf_prefix_reloc): New function.
(struct ppc_link_hash_table): Add notoc_plt.
(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set
has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle
possible need for dynamic relocs on non-pcrel powerxx relocs.
(dec_dynrel_count): Handle non-pcrel powerxx relocs.
(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_relocate_section): Handle new powerxx relocs.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2018-08-29 12:52:34 +08:00
|
|
|
|
|
|
|
|
RELOC_NUMBER (R_PPC64_D34, 128)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_D34_LO, 129)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_D34_HI30, 130)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_D34_HA30, 131)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PCREL34, 132)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_PCREL34, 133)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT_PCREL34, 134)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PLT_PCREL34_NOTOC, 135)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHER34, 136)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHERA34, 137)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHEST34, 138)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_ADDR16_HIGHESTA34, 139)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHER34, 140)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHERA34, 141)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHEST34, 142)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHESTA34, 143)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_D28, 144)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_PCREL28, 145)
|
[PowerPC64] pc-relative TLS relocations
This patch supports using pcrel instructions in TLS code sequences. A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation. For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence. The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.
GD:
pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34
bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
edited to IE
pld 3,z@got@tprel@pcrel
add 3,3,13
edited to LE
paddi 3,13,z@tprel
nop
LD:
pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34
bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
..
paddi 9,3,z2@dtprel
pld 10,z3@got@dtprel@pcrel
add 10,10,3
edited to LE
paddi 3,13,0x1000
nop
IE:
pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34
add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1
ldx 4,9,z@tls@pcrel
lwax 5,9,z@tls@pcrel
stdx 5,9,z@tls@pcrel
edited to LE
paddi 9,13,z@tprel
nop
ld 4,0(9)
lwa 5,0(9)
std 5,0(9)
LE:
paddi 10,13,z@tprel
include/
* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
(ppc64_elf_check_relocs): Support pcrel tls relocs.
(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
ld/
* testsuite/ld-powerpc/tlsgd.d,
* testsuite/ld-powerpc/tlsgd.s,
* testsuite/ld-powerpc/tlsie.d,
* testsuite/ld-powerpc/tlsie.s,
* testsuite/ld-powerpc/tlsld.d,
* testsuite/ld-powerpc/tlsld.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-19 14:06:58 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_TPREL34, 146)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_DTPREL34, 147)
|
Rename PowerPC64 pcrel GOT TLS relocations
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
2020-06-06 10:26:20 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSGD_PCREL34, 148)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TLSLD_PCREL34, 149)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_TPREL_PCREL34, 150)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GOT_DTPREL_PCREL34, 151)
|
PowerPC relocations for prefix insns
include/
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
(BFD_RELOC_PPC64_PLT_PCREL34),
(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
* elf64-ppc.c (PNOP): Define.
(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
relocs.
(ppc64_elf_prefix_reloc): New function.
(struct ppc_link_hash_table): Add notoc_plt.
(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set
has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle
possible need for dynamic relocs on non-pcrel powerxx relocs.
(dec_dynrel_count): Handle non-pcrel powerxx relocs.
(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_relocate_section): Handle new powerxx relocs.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2018-08-29 12:52:34 +08:00
|
|
|
|
2010-06-25 13:20:57 +08:00
|
|
|
#ifndef RELOC_MACROS_GEN_FUNC
|
PowerPC64 higher REL16 relocations
There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
2018-08-29 11:58:21 +08:00
|
|
|
/* Relocation only used internally by gas or ld. If you need to use
|
|
|
|
|
these reloc numbers, you can change them to some other unused value
|
2017-02-28 06:02:36 +08:00
|
|
|
without affecting the ABI. They will never appear in object files. */
|
PowerPC64 higher REL16 relocations
There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
2018-08-29 11:58:21 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_LO_DS_OPT, 200)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_16DX_HA, 201)
|
2010-06-25 13:20:57 +08:00
|
|
|
#endif
|
Add assembler, disassembler and linker support for power9.
include/opcode/
* ppc.h (PPC_OPCODE_POWER9): New define.
(PPC_OPCODE_VSX3): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
Add PPC_OPCODE_VSX3 to the vsx entry.
(powerpc_init_dialect): Set default dialect to power9.
* ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
extract_l1 insert_xtq6, extract_xtq6): New static functions.
(insert_esync): Test for illegal L operand value.
(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
PPCVSX3): New defines.
(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
<mcrxr>: Use XBFRARB_MASK.
<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
include/elf/
* ppc.h (R_PPC_REL16DX_HA): New reloction.
* ppc64.h (R_PPC64_REL16DX_HA): Likewise.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
(ppc_elf_addr16_ha_reloc): Likewise.
(ppc_elf_check_relocs): Likewise.
(ppc_elf_relocate_section): Likewise.
(is_insn_dq_form): Handle lxv and stxv instructions.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
(ppc64_elf_ha_reloc): Likewise.
(ppc64_elf_check_relocs): Likewise.
(ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.
elfcpp/
* powerpc.h (R_POWERPC_REL16DX_HA): Define.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
(md_apply_fix): Likewise.
(ppc_handle_align): Handle power9's group ending nop.
gas/testsuite/
* gas/ppc/altivec3.s: New test.
* gas/ppc/altivec3.d: Likewise.
* gas/ppc/vsx3.s: Likewise.
* gas/ppc/vsx3.d: Likewise.
* gas/ppc/power9.s: Likewise.
* gas/ppc/power9.d: Likewise.
* gas/ppc/ppc.exp: Run them.
* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
* gas/ppc/power8.d: Likewise.
* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
<lxvd2x, stxvd2x>: ...to this.
* gas/ppc/vsx.d: Likewise.
gold/
* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
(Powerpc_relocate_functions::addr16dx_ha): Likewise.
(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
ld/testsuite/
* ld-powerpc/addpcis.d: New test.
* ld-powerpc/addpcis.s: New test.
* ld-powerpc/powerpc.exp: Run it.
2015-11-12 09:52:52 +08:00
|
|
|
|
PowerPC64 higher REL16 relocations
There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
2018-08-29 11:58:21 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGH, 240)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHA, 241)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHER, 242)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHERA, 243)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHEST, 244)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HIGHESTA, 245)
|
|
|
|
|
|
Add assembler, disassembler and linker support for power9.
include/opcode/
* ppc.h (PPC_OPCODE_POWER9): New define.
(PPC_OPCODE_VSX3): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
Add PPC_OPCODE_VSX3 to the vsx entry.
(powerpc_init_dialect): Set default dialect to power9.
* ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
extract_l1 insert_xtq6, extract_xtq6): New static functions.
(insert_esync): Test for illegal L operand value.
(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
PPCVSX3): New defines.
(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
<mcrxr>: Use XBFRARB_MASK.
<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
include/elf/
* ppc.h (R_PPC_REL16DX_HA): New reloction.
* ppc64.h (R_PPC64_REL16DX_HA): Likewise.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
(ppc_elf_addr16_ha_reloc): Likewise.
(ppc_elf_check_relocs): Likewise.
(ppc_elf_relocate_section): Likewise.
(is_insn_dq_form): Handle lxv and stxv instructions.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
(ppc64_elf_ha_reloc): Likewise.
(ppc64_elf_check_relocs): Likewise.
(ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.
elfcpp/
* powerpc.h (R_POWERPC_REL16DX_HA): Define.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
(md_apply_fix): Likewise.
(ppc_handle_align): Handle power9's group ending nop.
gas/testsuite/
* gas/ppc/altivec3.s: New test.
* gas/ppc/altivec3.d: Likewise.
* gas/ppc/vsx3.s: Likewise.
* gas/ppc/vsx3.d: Likewise.
* gas/ppc/power9.s: Likewise.
* gas/ppc/power9.d: Likewise.
* gas/ppc/ppc.exp: Run them.
* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
* gas/ppc/power8.d: Likewise.
* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
<lxvd2x, stxvd2x>: ...to this.
* gas/ppc/vsx.d: Likewise.
gold/
* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
(Powerpc_relocate_functions::addr16dx_ha): Likewise.
(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
ld/testsuite/
* ld-powerpc/addpcis.d: New test.
* ld-powerpc/addpcis.s: New test.
* ld-powerpc/powerpc.exp: Run it.
2015-11-12 09:52:52 +08:00
|
|
|
/* Power9 split rel16 for addpcis. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16DX_HA, 246)
|
|
|
|
|
|
2009-07-10 20:19:58 +08:00
|
|
|
/* Support STT_GNU_IFUNC plt calls. */
|
2009-07-29 22:55:20 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_JMP_IREL, 247)
|
2009-07-10 20:19:58 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_IRELATIVE, 248)
|
|
|
|
|
|
2009-07-29 22:55:20 +08:00
|
|
|
/* These are GNU extensions used in PIC code sequences. */
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16, 249)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_LO, 250)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HI, 251)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_REL16_HA, 252)
|
|
|
|
|
|
2003-01-16 12:08:47 +08:00
|
|
|
/* These are GNU extensions to enable C++ vtable garbage collection. */
|
2003-02-04 22:48:36 +08:00
|
|
|
RELOC_NUMBER (R_PPC64_GNU_VTINHERIT, 253)
|
|
|
|
|
RELOC_NUMBER (R_PPC64_GNU_VTENTRY, 254)
|
2003-01-16 12:08:47 +08:00
|
|
|
|
|
|
|
|
END_RELOC_NUMBERS (R_PPC64_max)
|
|
|
|
|
|
Report overflow on PowerPC64 @h and @ha relocations.
This changes the behaviour of @h and @ha on PowerPC64 to report errors
on 32-bit overflow. The motivation for this change is that on
PowerPC64, most uses of @h and @ha modifiers and their corresponding
relocations are to build up 32-bit offsets. We'd like to know when
such offsets overflow. Only rarely do people use @h or @ha with the
high 32-bit modifiers to build a 64-bit constant. Those uses will now
need to use two new modifiers, @high and @higha, if the constant isn't
known at assembly time. For now, we won't report overflow at assembly
time..
This also fixes an error when applying some of the HIGHER and HIGHEST
relocations.
include/elf/
* ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
(IS_PPC64_TLS_RELOC): Match new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
Make all _HA and _HI relocs report signed overflow.
(ppc64_elf_reloc_type_lookup): Handle new relocs.
(must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
(dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
(ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (SEX16): Don't mask.
(REPORT_OVERFLOW_HI): Define as zero.
(ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha,
@tprel@high, and @tprel@higha modifiers.
(md_assemble): Ignore X_unsigned when applying 16-bit insn fields.
Add (disabled) code to check @h and @ha reloc overflow for powerpc64.
Handle new relocs.
(md_apply_fix): Similarly.
elfcpp/
* powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs.
(Target_powerpc::Scan::global, local): Likewise.
(Target_powerpc::Relocate::relocate): Likewise. Check for overflow
on all ppc64 @h and @ha relocs.
2013-10-29 14:23:25 +08:00
|
|
|
#define IS_PPC64_TLS_RELOC(R) \
|
|
|
|
|
(((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA) \
|
[PowerPC64] pc-relative TLS relocations
This patch supports using pcrel instructions in TLS code sequences. A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation. For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence. The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.
GD:
pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34
bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
edited to IE
pld 3,z@got@tprel@pcrel
add 3,3,13
edited to LE
paddi 3,13,z@tprel
nop
LD:
pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34
bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
..
paddi 9,3,z2@dtprel
pld 10,z3@got@dtprel@pcrel
add 10,10,3
edited to LE
paddi 3,13,0x1000
nop
IE:
pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34
add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1
ldx 4,9,z@tls@pcrel
lwax 5,9,z@tls@pcrel
stdx 5,9,z@tls@pcrel
edited to LE
paddi 9,13,z@tprel
nop
ld 4,0(9)
lwa 5,0(9)
std 5,0(9)
LE:
paddi 10,13,z@tprel
include/
* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
(ppc64_elf_check_relocs): Support pcrel tls relocs.
(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
ld/
* testsuite/ld-powerpc/tlsgd.d,
* testsuite/ld-powerpc/tlsgd.s,
* testsuite/ld-powerpc/tlsie.d,
* testsuite/ld-powerpc/tlsie.s,
* testsuite/ld-powerpc/tlsld.d,
* testsuite/ld-powerpc/tlsld.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-19 14:06:58 +08:00
|
|
|
|| ((R) >= R_PPC64_TPREL16_HIGH && (R) <= R_PPC64_DTPREL16_HIGHA) \
|
Rename PowerPC64 pcrel GOT TLS relocations
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
2020-06-06 10:26:20 +08:00
|
|
|
|| ((R) >= R_PPC64_TPREL34 && (R) <= R_PPC64_GOT_DTPREL_PCREL34))
|
2013-10-29 12:36:09 +08:00
|
|
|
|
|
|
|
|
/* e_flags bits specifying ABI.
|
|
|
|
|
1 for original function descriptor using ABI,
|
|
|
|
|
2 for revised ABI without function descriptors,
|
|
|
|
|
0 for unspecified or not using any features affected by the differences. */
|
|
|
|
|
#define EF_PPC64_ABI 3
|
|
|
|
|
|
2013-10-29 13:07:43 +08:00
|
|
|
/* The ELFv2 ABI uses three bits in the symbol st_other field of a
|
2018-07-26 10:41:11 +08:00
|
|
|
function definition to specify the number of bytes between a
|
2013-10-29 13:07:43 +08:00
|
|
|
function's global entry point and local entry point.
|
2018-07-26 10:41:11 +08:00
|
|
|
Values of two to six specify powers of two from four to sixty four
|
|
|
|
|
bytes. For such functions:
|
2013-10-29 13:07:43 +08:00
|
|
|
The global entry point is used when it is necessary to set up the
|
|
|
|
|
toc pointer (r2) for the function. Callers must enter the global
|
|
|
|
|
entry point with r12 set to the global entry point address. On
|
2018-07-26 10:41:11 +08:00
|
|
|
return from the function r2 will contain the toc pointer for the
|
|
|
|
|
function.
|
2013-10-29 13:07:43 +08:00
|
|
|
The local entry point is used when r2 is known to already be valid
|
|
|
|
|
for the function. There is no requirement on r12 when using the
|
|
|
|
|
local entry point, and on return r2 will contain the same value as
|
|
|
|
|
at entry.
|
|
|
|
|
A value of zero in these bits means that the function has a single
|
|
|
|
|
entry point with no requirement on r12 or r2, and that on return r2
|
|
|
|
|
will contain the same value as at entry.
|
2018-07-26 10:41:11 +08:00
|
|
|
A value of one means that the function has a single entry point
|
|
|
|
|
with no requirement on r12 or r2, and that r2 is *not* preserved.
|
|
|
|
|
A value of seven is reserved. */
|
2013-10-29 13:07:43 +08:00
|
|
|
#define STO_PPC64_LOCAL_BIT 5
|
|
|
|
|
#define STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT)
|
|
|
|
|
|
2020-06-29 08:37:56 +08:00
|
|
|
/* 3 bit other field to bytes. */
|
2013-10-29 13:07:43 +08:00
|
|
|
static inline unsigned int
|
|
|
|
|
ppc64_decode_local_entry(unsigned int other)
|
|
|
|
|
{
|
|
|
|
|
return ((1 << other) >> 2) << 2;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-29 08:37:56 +08:00
|
|
|
/* bytes to field value. */
|
2013-10-29 13:07:43 +08:00
|
|
|
static inline unsigned int
|
|
|
|
|
ppc64_encode_local_entry(unsigned int val)
|
|
|
|
|
{
|
|
|
|
|
return (val >= 4 * 4
|
|
|
|
|
? (val >= 8 * 4
|
|
|
|
|
? (val >= 16 * 4 ? 6 : 5)
|
|
|
|
|
: 4)
|
|
|
|
|
: (val >= 2 * 4
|
|
|
|
|
? 3
|
|
|
|
|
: (val >= 1 * 4 ? 2 : 0)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* st_other to number of bytes. */
|
|
|
|
|
#define PPC64_LOCAL_ENTRY_OFFSET(other) \
|
|
|
|
|
ppc64_decode_local_entry (((other) & STO_PPC64_LOCAL_MASK) \
|
|
|
|
|
>> STO_PPC64_LOCAL_BIT)
|
|
|
|
|
/* number of bytes to st_other. */
|
|
|
|
|
#define PPC64_SET_LOCAL_ENTRY_OFFSET(val) \
|
|
|
|
|
ppc64_encode_local_entry (val) << STO_PPC64_LOCAL_BIT
|
|
|
|
|
|
2003-01-16 12:08:47 +08:00
|
|
|
/* Specify the start of the .glink section. */
|
|
|
|
|
#define DT_PPC64_GLINK DT_LOPROC
|
|
|
|
|
|
|
|
|
|
/* Specify the start and size of the .opd section. */
|
|
|
|
|
#define DT_PPC64_OPD (DT_LOPROC + 1)
|
|
|
|
|
#define DT_PPC64_OPDSZ (DT_LOPROC + 2)
|
|
|
|
|
|
2013-10-29 14:04:35 +08:00
|
|
|
/* Specify whether various optimisations are possible. */
|
|
|
|
|
#define DT_PPC64_OPT (DT_LOPROC + 3)
|
|
|
|
|
#define PPC64_OPT_TLS 1
|
|
|
|
|
#define PPC64_OPT_MULTI_TOC 2
|
PPC64_OPT_LOCALENTRY
ELFv2 functions with localentry:0 are those with a single entry point,
ie. global entry == local entry, and that have no requirement on r2 or
r12, and guarantee r2 is unchanged on return. Such an external
function can be called via the PLT without saving r2 or restoring it
on return, avoiding a common load-hit-store for small functions. The
optimization is attractive. The TOC pointer load-hit-store is a major
reason why calls to small functions that need no register saves, or
with shrink-wrap, no register saves on a fast path, are slow on
powerpc64le.
To be safe, this optimization needs ld.so support to check that the
run-time matches link-time function implementation. If a function
in a shared library with st_other localentry non-zero is called
without saving and restoring r2, r2 will be trashed on return, leading
to segfaults. For that reason the optimization does not happen for
weak functions since a weak definition is a fairly solid hint that the
function will likely be overridden. I'm also not enabling the
optimization by default unless glibc-2.26 is detected, which should
have the ld.so checks implemented.
bfd/
* elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0.
(ppc64_elf_merge_symbol_attribute): Merge localentry bits from
dynamic objects.
(is_elfv2_localentry0): New function.
(ppc64_elf_tls_setup): Default params->plt_localentry0.
(plt_stub_size): Adjust size for tls_get_addr_opt stub.
(build_tls_get_addr_stub): Use a simpler stub when r2 is not saved.
(ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for
optimized localentry:0 stubs.
(ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve.
(ppc64_elf_relocate_section): Leave nop unchanged for optimized
localentry:0 stubs.
(ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in
DT_PPC64_OPT.
* elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0.
include/
* elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
ld/
* emultempl/ppc64elf.em (params): Init plt_localentry0 field.
(enum ppc64_opt): New, replacing OPTION_* defines. Add
OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY.
(PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry.
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry.
* testsuite/ld-powerpc/tlsopt5.d: Update.
2017-05-26 08:32:29 +08:00
|
|
|
#define PPC64_OPT_LOCALENTRY 4
|
include/elf/
* ppc.h (DT_PPC_TLSOPT): Define.
* ppc64.h (DT_PPC64_TLSOPT): Define.
bfd/
* elf32-ppc.c (TLS_GET_ADDR_GLINK_SIZE): Define.
(ADD_3_12_2, BEQLR, CMPWI_11_0, LWZ_11_3, LWZ_12_3): Define.
(MR_0_3, MR_3_0): Define.
(struct ppc_elf_link_hash_table): Add no_tls_get_addr_opt.
(ppc_elf_select_plt_layout): Save emit_stub_syms param earlier.
(ppc_elf_tls_setup): Add no_tls_get_addr_opt param and save to hash
table. Check for presense of __tls_get_addr_opt
(allocate_dynrelocs): Increase glink entry size for __tls_get_addr.
(ppc_elf_size_dynamic_sections): Add DT_PPC_TLS_OPT tag.
(write_glink_stub): Add param p.
(ppc_elf_relocate_section): Adjust write_glink_stub call.
(ppc_elf_finish_dynamic_symbol): Emit special glink call stub for
__tls_get_addr.
* elf32-ppc.h (ppc_elf_tls_setup): Update prototype.
* elf64-ppc.c (struct ppc_link_hash_table): Add no_tls_get_addr_opt.
(ppc64_elf_tls_setup): Add no_tls_get_addr_opt param and save to hash
table. Check for presense of __tls_get_addr_opt.
(ppc64_elf_size_dynamic_sections): Add DT_PPC64_TLS_OPT tag.
(LD_R11_0R3, LD_R12_0R3, MR_R0_R3, CMPDI_R11_0, ADD_R3_R12_R13,
BEQLR, MR_R3_R0, MFLR_R11, STD_R11_0R1, BCTRL, LD_R11_0R1,
LD_R2_0R1, MTLR_R11): Define.
(build_tls_get_addr_stub): New function.
(ppc_build_one_stub): Call it.
(ppc_size_one_stub): Add extra size for __tls_get_addr stub.
(ppc64_elf_relocate_section): Don't change nop to ld 2,40(1) for
__tls_get_addr plt call.
* elf64-ppc.h (ppc64_elf_tls_setup): Update prototype.
binutils/
* readelf.c (get_ppc_dynamic_type): Add TLSOPT.
(get_ppc64_dynamic_type): Likewise.
ld/
* emultempl/ppc32elf.em (no_tls_get_addr_opt): New var.
(ppc_before_allocation): Pass to ppc_elf_tls_setup.
(OPTION_NO_TLS_GET_ADDR_OPT): Define. Redefine other options in
terms of previous option.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add
--no-tls-get-addr-optimize.
(PARSE_AND_LIST_ARGS_CASES): Handle it.
* emultempl/ppc64elf.em (no_tls_get_addr_opt): New var.
(ppc_before_allocation): Pass to ppc64_elf_tls_setup.
(OPTION_NO_TLS_GET_ADDR_OPT): Define.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add
--no-tls-get-addr-optimize.
(PARSE_AND_LIST_ARGS_CASES): Handle it.
ld/testsuite/
* ld-powerpc/tlslib.s: Delete dot-symbol entry syms. Add
__tls_get_addr_opt.
* ld-powerpc/tlslib32.s: Add __tls_get_addr_opt.
* ld-powerpc/oldtlslib.s: New file, old-abi version of tlslib.s.
* ld-powerpc/powerpc.exp: Build old-abi library and use it in
two new link tests.
* ld-powerpc/tlsexe.d: Update for new __tls_get_addr stub.
* ld-powerpc/tlsexe.g, * ld-powerpc/tlsexe.r, *ld-powerpc/tlsexe32.d,
* ld-powerpc/tlsexe32.g, * ld-powerpc/tlsexe32.r,
* ld-powerpc/tlsexetoc.d, * ld-powerpc/tlsexetoc.g,
* ld-powerpc/tlsexetoc.r: Likewise.
2009-09-21 19:51:02 +08:00
|
|
|
|
2003-01-16 12:08:47 +08:00
|
|
|
#endif /* _ELF_PPC64_H */
|
