2016-07-05 18:28:46 +08:00
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2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
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* include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
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(SHF_ARM_PURECODE): ... this.
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2016-07-01 23:20:50 +08:00
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2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
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(AARCH64_CPU_HAS_ANY_FEATURES): New.
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(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
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(AARCH64_OPCODE_HAS_FEATURE): Remove.
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2016-06-30 17:46:51 +08:00
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2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
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* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
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of enabled FPU features.
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2016-05-27 16:52:45 +08:00
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2016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* opcode/sparc.h (enum sparc_opcode_arch_val): Move
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SPARC_OPCODE_ARCH_MAX into the enum.
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2016-06-28 16:21:04 +08:00
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2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
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* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
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MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.
include/
* elf/mips.h (R_MIPS16_PC16_S1): New relocation.
bfd/
* elf32-mips.c (elf_mips16_howto_table_rel): Add
R_MIPS16_PC16_S1.
(mips16_reloc_map): Likewise.
* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
(mips16_elf64_howto_table_rela): Likewise.
(mips16_reloc_map): Likewise.
* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
(elf_mips16_howto_table_rela): Likewise.
(mips16_reloc_map): Likewise.
* elfxx-mips.c (mips16_branch_reloc_p): New function.
(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
(b_reloc_p): Likewise.
(mips_elf_calculate_relocation): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-mips.c (mips16_reloc_p): Handle
BFD_RELOC_MIPS16_16_PCREL_S1.
(b_reloc_p): Likewise.
(limited_pcrel_reloc_p): Likewise.
(md_pcrel_from): Likewise.
(md_apply_fix): Likewise.
(tc_gen_reloc): Likewise.
(md_convert_frag): Likewise.
(mips_fix_adjustable): Update comment.
* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
implicit instruction padding, avoid MIPS16 JR->JRC conversion.
* testsuite/gas/mips/branch-weak-6.d: New test.
* testsuite/gas/mips/branch-weak-7.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
* testsuite/ld-mips-elf/mips16-branch.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 08:23:36 +08:00
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2016-06-28 Maciej W. Rozycki <macro@imgtec.com>
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* elf/mips.h (R_MIPS16_PC16_S1): New relocation.
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2016-06-05 04:46:58 +08:00
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2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* elf/xtensa.h (xtensa_make_property_section): New prototype.
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2016-06-16 13:44:11 +08:00
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2016-06-24 John Baldwin <jhb@FreeBSD.org>
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* elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
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(AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
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(AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
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(AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
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[ARC] Misc minor edits/fixes
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.
A couple of other minor edits (that make no functional change) are
also included.
gas/ChangeLog:
* config/tc-arc.c (options, md_longopts, md_parse_option):
Move -mspfp, -mdpfp and -mfpuda out of the sections for
dummy options. Correct erroneous enabling of SPFP
instructions when using -mnps400.
include/ChangeLog:
* opcode/arc.h: Make insn_class_t alphabetical again.
opcodes/ChangeLog:
* arc-opc.c: Correct description of availability of NPS400
features.
2016-06-22 03:25:29 +08:00
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2016-06-23 Graham Markall <graham.markall@embecosm.com>
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* opcode/arc.h: Make insn_class_t alphabetical again.
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2016-06-04 11:11:46 +08:00
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2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* elf/dlx.h: Wrap in extern C.
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* elf/xtensa.h: Likewise.
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* opcode/arc.h: Likewise.
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2016-05-28 23:54:51 +08:00
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2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
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tilegx_pipeline.
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2016-06-21 21:03:08 +08:00
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2016-06-21 Graham Markall <graham.markall@embecosm.com>
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* opcode/arc.h: Add nps400 extension and instruction
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subclass.
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Remove ARC_OPCODE_NPS400
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* elf/arc.h: Remove E_ARC_MACH_NPS400
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bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 17:12:48 +08:00
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2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
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* opcode/sparc.h (enum sparc_opcode_arch_val): Add
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SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
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SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
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SPARC_OPCODE_ARCH_V9M.
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2016-06-11 22:20:02 +08:00
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2016-06-14 John Baldwin <jhb@FreeBSD.org>
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* opcode/msp430-decode.h (MSP430_Size): Remove.
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(Msp430_Opcode_Decoded): Change type of size to int.
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2016-06-11 13:19:49 +08:00
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2016-06-11 Alan Modra <amodra@gmail.com>
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* coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
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2016-06-09 04:46:22 +08:00
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2016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
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* opcode/sparc.h: Add missing documentation for hyperprivileged
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registers in rd (%) and rs1 ($).
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PowerPC VLE
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07 20:34:38 +08:00
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2016-06-07 Alan Modra <amodra@gmail.com>
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* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
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PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
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PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
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PPC_APUINFO_VLE: Define.
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2016-06-07 16:56:42 +08:00
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2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
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* opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
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entries.
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(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
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2016-06-02 21:03:23 +08:00
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2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
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(struct arc_long_opcode): New structure.
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(arc_long_opcodes): Declare.
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(arc_num_long_opcodes): Declare.
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2016-05-29 16:29:22 +08:00
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2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* elf/mips.h: Add extern "C".
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* elf/sh.h: Likewise.
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* opcode/d10v.h: Likewise.
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* opcode/d30v.h: Likewise.
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* opcode/ia64.h: Likewise.
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* opcode/mips.h: Likewise.
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* opcode/ppc.h: Likewise.
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* opcode/sparc.h: Likewise.
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* opcode/tic6x.h: Likewise.
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* opcode/v850.h: Likewise.
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Return void from linker callbacks
The ldmain.c implementation of these linker callback functions always
return true, so any code handling a false return is dead. What's
more, some of the bfd backends abort if ever a false return is seen,
and there seems to be some confusion in gdb's compile-object-load.c.
The return value was never meant to be "oh yes, a multiple_definition
error occurred", but rather "out of memory or other catastrophic
failure".
This patch removes the status return on the callbacks that always
return true. I kept the return status for "notice" because that one
does happen to need to return "out of memory".
include/
* bfdlink.h (struct bfd_link_callbacks): Update comments.
Return void from multiple_definition, multiple_common,
add_to_set, constructor, warning, undefined_symbol,
reloc_overflow, reloc_dangerous and unattached_reloc.
bfd/
* aoutx.h: Adjust linker callback calls throughout file,
removing dead code.
* bout.c: Likewise.
* coff-alpha.c: Likewise.
* coff-arm.c: Likewise.
* coff-h8300.c: Likewise.
* coff-h8500.c: Likewise.
* coff-i960.c: Likewise.
* coff-mcore.c: Likewise.
* coff-mips.c: Likewise.
* coff-ppc.c: Likewise.
* coff-rs6000.c: Likewise.
* coff-sh.c: Likewise.
* coff-tic80.c: Likewise.
* coff-w65.c: Likewise.
* coff-z80.c: Likewise.
* coff-z8k.c: Likewise.
* coff64-rs6000.c: Likewise.
* cofflink.c: Likewise.
* ecoff.c: Likewise.
* elf-bfd.h: Likewise.
* elf-m10200.c: Likewise.
* elf-m10300.c: Likewise.
* elf32-arc.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-avr.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-cr16.c: Likewise.
* elf32-cr16c.c: Likewise.
* elf32-cris.c: Likewise.
* elf32-crx.c: Likewise.
* elf32-d10v.c: Likewise.
* elf32-epiphany.c: Likewise.
* elf32-fr30.c: Likewise.
* elf32-frv.c: Likewise.
* elf32-ft32.c: Likewise.
* elf32-h8300.c: Likewise.
* elf32-hppa.c: Likewise.
* elf32-i370.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-i860.c: Likewise.
* elf32-ip2k.c: Likewise.
* elf32-iq2000.c: Likewise.
* elf32-lm32.c: Likewise.
* elf32-m32c.c: Likewise.
* elf32-m32r.c: Likewise.
* elf32-m68hc1x.c: Likewise.
* elf32-m68k.c: Likewise.
* elf32-mep.c: Likewise.
* elf32-metag.c: Likewise.
* elf32-microblaze.c: Likewise.
* elf32-moxie.c: Likewise.
* elf32-msp430.c: Likewise.
* elf32-mt.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-nios2.c: Likewise.
* elf32-or1k.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-s390.c: Likewise.
* elf32-score.c: Likewise.
* elf32-score7.c: Likewise.
* elf32-sh.c: Likewise.
* elf32-sh64.c: Likewise.
* elf32-spu.c: Likewise.
* elf32-tic6x.c: Likewise.
* elf32-tilepro.c: Likewise.
* elf32-v850.c: Likewise.
* elf32-vax.c: Likewise.
* elf32-visium.c: Likewise.
* elf32-xstormy16.c: Likewise.
* elf32-xtensa.c: Likewise.
* elf64-alpha.c: Likewise.
* elf64-hppa.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-mmix.c: Likewise.
* elf64-ppc.c: Likewise.
* elf64-s390.c: Likewise.
* elf64-sh64.c: Likewise.
* elf64-x86-64.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfxx-mips.c: Likewise.
* elfxx-sparc.c: Likewise.
* elfxx-tilegx.c: Likewise.
* linker.c: Likewise.
* pdp11.c: Likewise.
* pe-mips.c: Likewise.
* reloc.c: Likewise.
* reloc16.c: Likewise.
* simple.c: Likewise.
* vms-alpha.c: Likewise.
* xcofflink.c: Likewise.
* elf32-rl78.c (get_symbol_value, get_romstart, get_ramstart): Delete
status param. Adjust calls to these and linker callbacks throughout.
* elf32-rx.c: (get_symbol_value, get_gp, get_romstart,
get_ramstart): Delete status param. Adjust calls to these and
linker callbacks throughout.
ld/
* ldmain.c (multiple_definition, multiple_common, add_to_set,
constructor_callback, warning_callback, undefined_symbol,
reloc_overflow, reloc_dangerous, unattached_reloc): Return void.
* emultempl/elf32.em: Adjust callback calls.
gdb/
* compile/compile-object-load.c (link_callbacks_multiple_definition,
link_callbacks_warning, link_callbacks_undefined_symbol,
link_callbacks_undefined_symbol, link_callbacks_reloc_overflow,
link_callbacks_reloc_dangerous,
link_callbacks_unattached_reloc): Return void.
2016-05-27 15:50:55 +08:00
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2016-05-28 Alan Modra <amodra@gmail.com>
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* bfdlink.h (struct bfd_link_callbacks): Update comments.
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Return void from multiple_definition, multiple_common,
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add_to_set, constructor, warning, undefined_symbol,
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reloc_overflow, reloc_dangerous and unattached_reloc.
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2016-05-23 19:54:24 +08:00
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2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* opcode/metag.h: wrap declarations in extern "C".
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[ARC] Update instruction type and delay slot info.
This patch corrects the instructioninformation passed into the
disassebler_info structure.
include/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add COND.
(flag_class_t): Add F_CLASS_EXTEND.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
information.
(print_insn_arc): Set insn_type information.
* arc-opc.c (C_CC): Add F_CLASS_COND.
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
(brne, brne_s, jeq_s, jne_s): Likewise.
2016-05-19 18:19:32 +08:00
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2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
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* opcode/arc.h (insn_subclass_t): Add COND.
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(flag_class_t): Add F_CLASS_EXTEND.
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2016-05-23 23:25:46 +08:00
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2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
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* opcode/arc.h (struct arc_opcode): Renamed attribute class to
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insn_class.
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(struct arc_flag_class): Renamed attribute class to flag_class.
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2016-05-19 11:48:48 +08:00
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2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
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plain symbol.
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2016-05-17 02:21:49 +08:00
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2016-04-29 Tom Tromey <tom@tromey.com>
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* dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
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DW_LANG_Rust_old>: New constants.
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2014-11-26 19:15:01 +08:00
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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* elf/mips.h (AFL_ASE_DSPR3): New macro.
|
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(AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
|
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* opcode/mips.h (ASE_DSPR3): New macro.
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2016-05-10 23:14:23 +08:00
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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Nick Clifton <nickc@redhat.com>
|
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* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
|
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|
|
enumerator.
|
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|
|
|
|
(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
|
|
|
|
|
|
(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
|
|
|
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|
|
(ARM_SYM_BRANCH_TYPE): Replace by ...
|
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|
(ARM_GET_SYM_BRANCH_TYPE): This and ...
|
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|
(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
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BFD_ASSERT is defined or not.
|
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2016-05-10 22:15:15 +08:00
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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* elf/arm.h (Tag_DSP_extension): Define.
|
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|
2016-05-10 22:06:41 +08:00
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
* arm.h (ARM_FSET_CPU_SUBSET): Define macro.
|
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|
2016-05-10 22:01:53 +08:00
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
|
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|
(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
|
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|
(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
|
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for the high core bits.
|
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2016-05-03 19:44:13 +08:00
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2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
|
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* opcode/arc.h (ARC_SYNTAX_1OP): Declare
|
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|
(ARC_SYNTAX_NOP): Likewsie.
|
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(ARC_OP1_MUST_BE_IMM): Update defined value.
|
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|
(ARC_OP1_IMM_IMPLIED): Likewise.
|
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|
(arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
|
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2016-04-28 16:11:03 +08:00
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|
2016-04-28 Nick Clifton <nickc@redhat.com>
|
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PR target/19722
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* opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
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2016-04-27 11:23:05 +08:00
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|
2016-04-27 Alan Modra <amodra@gmail.com>
|
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* bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
|
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undef. Formatting.
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2016-04-21 22:43:00 +08:00
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2016-04-21 Nick Clifton <nickc@redhat.com>
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* bfdlink.h: Add prototype for bfd_link_check_relocs.
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2016-04-20 20:26:37 +08:00
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2016-04-20 H.J. Lu <hongjiu.lu@intel.com>
|
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* bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
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2016-04-20 00:40:41 +08:00
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2016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
* elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
|
|
|
|
|
|
|
opcodes/arc: Add yet more nps instructions
Add some more arc/nps400 instructions and the associated operands.
There's also a test added into the assembler.
gas/ChangeLog:
* testsuite/gas/arc/nps400-6.d: New file.
* testsuite/gas/arc/nps400-6.s: New file.
include/ChangeLog:
* opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp
instructions.
* arc-opc.c (insert_nps_bitop_size): Delete.
(extract_nps_bitop_size): Delete.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
(extract_nps_qcmp_m3): Define.
(extract_nps_qcmp_m2): Define.
(extract_nps_qcmp_m1): Define.
(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
NPS_QCMP_M3.
2016-04-02 02:51:50 +08:00
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|
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
* opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
|
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|
2016-04-01 02:51:14 +08:00
|
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|
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
|
* opcode/arc.h (insn_class_t): Add NET and ACL class.
|
|
|
|
|
|
|
arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-03-30 07:02:19 +08:00
|
|
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|
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
|
|
|
|
|
|
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
|
|
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|
|
|
|
2016-04-06 22:08:04 +08:00
|
|
|
|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (flag_class_t): Update.
|
|
|
|
|
|
(ARC_OPCODE_NONE): Define.
|
|
|
|
|
|
(ARC_OPCODE_ARCALL): Likewise.
|
|
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|
|
|
(ARC_OPCODE_ARCFPX): Likewise.
|
|
|
|
|
|
(ARC_REGISTER_READONLY): Likewise.
|
|
|
|
|
|
(ARC_REGISTER_WRITEONLY): Likewise.
|
|
|
|
|
|
(ARC_REGISTER_NOSHORT_CUT): Likewise.
|
|
|
|
|
|
(arc_aux_reg): Add cpu.
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 22:03:53 +08:00
|
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|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
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|
|
|
* opcode/arc.h (arc_num_opcodes): Remove.
|
|
|
|
|
|
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
|
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|
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
|
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|
|
(ARC_SUFFIX_FLAG): Define.
|
|
|
|
|
|
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
|
|
|
|
|
|
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
|
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|
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|
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
|
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|
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
|
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|
|
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
|
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|
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
|
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|
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
|
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|
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
|
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|
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
|
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|
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
|
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|
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
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|
* opcode/arc.h (DPA, DPX, SPX): New subclass enums.
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|
(ARC_FPUDA): Define.
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|
(arc_aux_reg): Add new field.
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2016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
|
2016-04-05 23:05:09 +08:00
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* opcode/arc-func.h (replace_bits24): Changed.
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|
(replace_bits24_be): Created.
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|
[ARC] Add support for Quarkse opcodes.
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 20:49:22 +08:00
|
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|
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
|
|
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Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 22:03:53 +08:00
|
|
|
|
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
|
|
|
|
|
|
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
|
|
|
|
|
|
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
|
|
|
|
|
|
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
|
|
|
|
|
|
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
|
|
|
|
|
|
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
|
|
|
|
|
|
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
|
|
|
|
|
|
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
|
|
|
|
|
|
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
|
|
|
|
|
|
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
|
|
|
|
|
|
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
|
|
|
|
|
|
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
|
|
|
|
|
|
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
|
|
|
|
|
|
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
|
[ARC] Add support for Quarkse opcodes.
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 20:49:22 +08:00
|
|
|
|
|
2016-03-20 13:34:02 +08:00
|
|
|
|
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/i960.h: Add const qualifiers.
|
|
|
|
|
|
* opcode/tic4x.h (struct tic4x_inst): Likewise.
|
|
|
|
|
|
|
2016-03-16 06:01:34 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
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|
|
|
|
|
|
|
|
* opcodes/arc.h (insn_class_t): Add BITOP type.
|
|
|
|
|
|
|
arc/opcodes: Use flag operand class to handle multiple flag matches
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
2016-03-15 06:17:47 +08:00
|
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|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
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|
|
|
|
|
|
|
|
|
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
|
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|
|
|
new classes instead.
|
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|
|
2016-03-16 05:51:50 +08:00
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|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
|
|
|
|
* elf/arc.h (E_ARC_MACH_NPS400): Define.
|
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|
|
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
|
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|
|
arc: Remove EF_ARC_CPU_GENERIC constant.
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.
There are some non-gnu arc compilers that don't write an architecture
type into the e_flags field, instead leaving the field as 0, which is
the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine
type to distinguish between the old and newer arc architectures, setting
the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700
architectures, while using EM_ARC_COMPACT2 for newer arcem and archs
architectures.
Previously when displaying the machine flags for an older EM_ARC_COMPACT
machine, if the e_flags had not been filled in, then we relied on the
default case statement to display the message "Generic ARCompact", while
in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC
to print "ARC Generic", leaving the default case to print a message
about unrecognised cpu flag.
After this commit EF_ARC_CPU_GENERIC has been removed, for both machine
types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case
statement to handle the situation where the e_flags has not been filled
in. The message displayed is now "Unknown ARCompact" (for older arc
architectures) and "Unknown ARC" (for the newer architectures). The
switch from "Generic" to "Unknown" in the message string is for clarity,
calling the file "Generic" can give the impression that the file is
compiled for a common sub-set of the architectures, and would therefore
run on any type of machine (or at least any type of new or old machine
depending on if the machine type is ARC or ARCv2). However, this was
not what "Generic" meant, it really meant "Unknown", so that's what we
now say.
As part of the merging of the readelf flag reading code, I have unified
the strings used in displaying the ELF ABI. This means that for older
arc machines (arc600, arc601, and arc700) the string used for the
original ABI, and ABIv2 have changed, the current ABIv3 remains the
same. For the newer architectures (arcem and archs) the abi strings
remain unchanged in all cases.
bfd/ChangeLog:
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
in e_flags, this will have been set elsewhere.
binutils/ChangeLog:
* readelf.c (get_machine_flags): Move arc processing into...
(decode_ARC_machine_flags): ... new function. Remove use of
EF_ARC_CPU_GENERIC, change default case from "generic arc" to
"unknown arc". Merged ABI printing between two machine types.
gas/ChangeLog:
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
include/ChangeLog:
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-16 05:38:30 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
|
|
|
|
|
|
|
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
|
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|
|
|
|
2016-03-16 03:09:23 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arc.h (EF_ARC_MACH): Delete.
|
|
|
|
|
|
(EF_ARC_MACH_MSK): Remove out of date comment.
|
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|
|
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|
|
2016-03-01 19:41:12 +08:00
|
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|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
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|
|
|
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
|
|
|
|
|
|
|
2016-03-16 02:07:06 +08:00
|
|
|
|
2016-03-15 H.J. Lu <hongjiu.lu@intel.com>
|
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|
PR ld/19807
|
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|
* bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
|
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|
2016-03-08 21:19:52 +08:00
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|
2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
|
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|
Andrew Burgess <andrew.burgess@embecosm.com>
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|
* elf/arc-reloc.def: Add a call to ME within the formula for each
|
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|
|
relocation that requires middle-endian correction.
|
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|
2016-03-07 23:16:28 +08:00
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|
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
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|
|
* opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
|
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|
|
|
* opcode/h8300.h (struct h8_opcode): Likewise.
|
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|
|
* opcode/hppa.h (struct pa_opcode): Likewise.
|
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|
|
* opcode/msp430.h: Likewise.
|
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|
|
|
|
* opcode/spu.h (struct spu_opcode): Likewise.
|
|
|
|
|
|
* opcode/tic30.h (struct _register): Likewise.
|
|
|
|
|
|
* opcode/tic4x.h (struct tic4x_register): Likewise.
|
|
|
|
|
|
(struct tic4x_cond): Likewise.
|
|
|
|
|
|
(struct tic4x_indirect): Likewise.
|
|
|
|
|
|
(struct tic4x_inst): Likewise.
|
|
|
|
|
|
* opcode/visium.h (struct reg_entry): Likewise.
|
|
|
|
|
|
|
2016-03-04 19:28:28 +08:00
|
|
|
|
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
|
|
|
|
|
|
(ARM_CPU_HAS_FEATURE): Add comment.
|
|
|
|
|
|
|
2016-03-05 00:28:12 +08:00
|
|
|
|
2016-03-03 Than McIntosh <thanm@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* plugin-api.h: Add new hooks to the plugin transfer vector to
|
|
|
|
|
|
to support querying section alignment and section size.
|
|
|
|
|
|
(ld_plugin_get_input_section_alignment): New hook.
|
|
|
|
|
|
(ld_plugin_get_input_section_size): New hook.
|
|
|
|
|
|
(ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
|
|
|
|
|
|
and LDPT_GET_INPUT_SECTION_SIZE.
|
|
|
|
|
|
(ld_plugin_tv): Add tv_get_input_section_alignment and
|
|
|
|
|
|
tv_get_input_section_size.
|
|
|
|
|
|
|
2016-03-05 06:17:39 +08:00
|
|
|
|
2016-03-03 Evgenii Stepanov <eugenis@google.com>
|
2016-03-04 03:36:36 +08:00
|
|
|
|
|
|
|
|
|
|
* plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
|
|
|
|
|
|
|
2016-02-26 22:44:03 +08:00
|
|
|
|
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/19645
|
|
|
|
|
|
* bfdlink.h (bfd_link_elf_stt_common): New enum.
|
|
|
|
|
|
(bfd_link_info): Add elf_stt_common.
|
|
|
|
|
|
|
2016-02-26 20:16:15 +08:00
|
|
|
|
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/19636
|
|
|
|
|
|
PR ld/19704
|
|
|
|
|
|
PR ld/19719
|
|
|
|
|
|
* bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
|
|
|
|
|
|
|
2016-02-19 22:27:23 +08:00
|
|
|
|
2016-02-19 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arm.h (ARM_EXT2_FP16_INSN): New.
|
|
|
|
|
|
|
Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 20:09:01 +08:00
|
|
|
|
2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
Janek van Oirschot <jvanoirs@synopsys.com>
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 22:03:53 +08:00
|
|
|
|
* opcode/arc.h (arc_opcode arc_relax_opcodes)
|
|
|
|
|
|
(arc_num_relax_opcodes): Declare.
|
Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 20:09:01 +08:00
|
|
|
|
|
2016-02-10 00:34:24 +08:00
|
|
|
|
2016-02-09 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/metag.h (metag_scondtab): Mark as possibly unused.
|
|
|
|
|
|
* opcode/nds32.h (nds32_r45map): Likewise.
|
|
|
|
|
|
(nds32_r54map): Likewise.
|
|
|
|
|
|
* opcode/visium.h (gen_reg_table): Likewise.
|
|
|
|
|
|
(fp_reg_table, cc_table, opcode_table): Likewise.
|
|
|
|
|
|
|
2016-02-09 10:22:02 +08:00
|
|
|
|
2016-02-09 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 16583
|
|
|
|
|
|
* elf/common.h (AT_SUN_HWCAP): Undef before defining.
|
|
|
|
|
|
|
2016-02-04 17:55:10 +08:00
|
|
|
|
2016-02-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19561
|
|
|
|
|
|
* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
|
|
|
|
|
|
(RRUX): Synthesise using case 2 rather than 7.
|
|
|
|
|
|
|
2015-12-14 14:26:19 +08:00
|
|
|
|
2016-01-19 John Baldwin <jhb@FreeBSD.org>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (NT_FREEBSD_THRMISC): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_PROC): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_FILES): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_VMMAP): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_GROUPS): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_UMASK): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_RLIMIT): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_OSREL): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
|
|
|
|
|
|
(NT_FREEBSD_PROCSTAT_AUXV): Define.
|
|
|
|
|
|
|
Add PIC and TLS support to the ARC target.
bfd/ChangeLog:
* arc-plt.def: New file.
* arc-plt.h: Likewise.
* elf32-arc.c (elf_arc_abs_plt0_entry, elf_arc_abs_pltn_entry,
elf_arcV2_abs_plt0_entry, elf_arcV2_abs_pltn_entry,
elf_arc_pic_plt0_entry, elf_arc_pic_pltn_entry,
elf_arcV2_pic_plt0_entry, elf_arcV2_pic_pltn_entry): Remove.
(name_for_global_symbol): Added.
(ADD_RELA): Helper to create dynamic relocs.
(new_got_entry_to_list): Create a new got entry in linked list.
(symbol_has_entry_of_type): Search for specific type of entry in
list.
(is_reloc_for_GOT): return FALSE for any TLS related relocs.
(is_reloc_for_TLS, arc_elf_set_private_flags)
(arc_elf_print_private_bfd_data, arc_elf_copy_private_bfd_data)
(arc_elf_merge_private_bfd_data): New functions.
(debug_arc_reloc): Cleaned debug info printing.
(PDATA reloc): Changed not to perform address alignment.
(reverse_me): Added. Fix for ARC_32 relocs.
(arc_do_relocation): Return bfd_reloc_of when no relocation should
occur.
(arc_get_local_got_ents): Renamed from arc_get_local_got_offsets.
Changed function to access an array of list of GOT entries instead
of just an array of offsets.
(elf_arc_relocate_section): Added support for PIC and TLS related relocations.
(elf_arc_check_relocs): Likewise.
(elf_arc_adjust_dynamic_symbol, elf_arc_finish_dynamic_symbol,
(elf_arc_finish_dynamic_sections): Likewise
(arc_create_dynamic_sections): Modified conditions to create
dynamic sections.
(ADD_SYMBOL_REF_SEC_AND_RELOC): New macro.
(plt_do_relocs_for_symbol, relocate_plt_for_symbol)
(relocate_plt_for_entry): Changed to support new way to define PLT
related code.
(add_symbol_to_plt): Likewise.
(arc_elf_link_hash_table_create): New function.
include/ChangeLog:
* elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
(ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
(ARC_TLS_LE_32): Fixed formula.
(ARC_TLS_GD_LD): Use new special function.
* opcode/arc-func.h: Changed all the replacement
functions to clear the patching bits before doing an or it with the value
argument.
2016-01-19 23:25:58 +08:00
|
|
|
|
2016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
|
|
|
|
|
|
Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
|
|
|
|
|
|
(ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
|
|
|
|
|
|
(ARC_TLS_LE_32): Fixed formula.
|
|
|
|
|
|
(ARC_TLS_GD_LD): Use new special function.
|
|
|
|
|
|
* opcode/arc-func.h: Changed all the replacement
|
|
|
|
|
|
functions to clear the patching bits before doing an or it with the value
|
|
|
|
|
|
argument.
|
|
|
|
|
|
|
2016-01-18 23:58:47 +08:00
|
|
|
|
2016-01-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/19440
|
|
|
|
|
|
* coff/internal.h (internal_syment): Use int to hold section
|
|
|
|
|
|
number.
|
|
|
|
|
|
(N_UNDEF): Cast to int not short.
|
|
|
|
|
|
(N_ABS): Likewise.
|
|
|
|
|
|
(N_DEBUG): Likewise.
|
|
|
|
|
|
(N_TV): Likewise.
|
|
|
|
|
|
(P_TV): Likewise.
|
|
|
|
|
|
|
2016-01-11 19:06:56 +08:00
|
|
|
|
2016-01-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
Import this change from GCC mainline:
|
|
|
|
|
|
|
|
|
|
|
|
2016-01-07 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* longlong.h: Change !__SHMEDIA__ to
|
|
|
|
|
|
(!defined (__SHMEDIA__) || !__SHMEDIA__).
|
|
|
|
|
|
Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
|
|
|
|
|
|
|
2016-01-07 02:31:23 +08:00
|
|
|
|
2016-01-06 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/mips.h: Add a summary of MIPS16 operand codes.
|
|
|
|
|
|
|
2016-01-03 14:30:32 +08:00
|
|
|
|
2016-01-05 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
|
|
|
|
|
|
|
* libiberty.h (dupargv): Change arg to char * const *.
|
|
|
|
|
|
(writeargv, countargv): Likewise.
|
|
|
|
|
|
|
2016-01-01 19:25:12 +08:00
|
|
|
|
2016-01-01 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2016-01-01 18:44:31 +08:00
|
|
|
|
For older changes see ChangeLog-0415, aout/ChangeLog-9115,
|
|
|
|
|
|
cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
|
|
|
|
|
|
mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
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som/ChangeLog-1015, and vms/ChangeLog-1015
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Copyright (C) 2016 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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