2000-04-22 04:22:24 +08:00
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Resource Name; Writers; Writers; Semantics of Dependency
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ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none
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AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF
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AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF
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AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF
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Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
2002-12-05 10:08:02 +08:00
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AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF
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AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF
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2000-04-22 04:22:24 +08:00
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AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF
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Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
2002-12-05 10:08:02 +08:00
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AR[EFLAG]; mov-to-AR-EFLAG; mov-to-AR-EFLAG; impliedF
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AR[FCR]; mov-to-AR-FCR; mov-to-AR-FCR; impliedF
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AR[FDR]; mov-to-AR-FDR; mov-to-AR-FDR; impliedF
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AR[FIR]; mov-to-AR-FIR; mov-to-AR-FIR; impliedF
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2000-04-22 04:22:24 +08:00
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AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF
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AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF
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AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF
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AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF
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AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none
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AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF
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AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none
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AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF
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AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none
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AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF
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AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none
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AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF
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AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
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AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
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Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
2002-12-05 10:08:02 +08:00
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AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
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2000-04-22 04:22:24 +08:00
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AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF
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AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF
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AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF
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AR[PFS]; br.call, brl.call; br.call, brl.call; none
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AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF
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AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF
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AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF
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AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF
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AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none
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AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF
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BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF
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BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF
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BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none
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CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF
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CPUID#; IC:none; IC:none; none
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CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF
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CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF
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CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4
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CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF
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CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF
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CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF
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CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF
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CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF
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CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF
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CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF
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CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF
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CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF
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CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF
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CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF
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CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF
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CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF
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CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF
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CR[IVR]; IC:none; IC:none; SC
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CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC
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CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF
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CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF
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CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF
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CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF
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CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none
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DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF
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DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
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DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF
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DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
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DTR; itr.d; itr.d; impliedF
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DTR; itr.d; ptr.d; impliedF
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DTR; ptr.d; ptr.d; none
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FR%, % in 0 - 1; IC:none; IC:none; none
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FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF
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GR0; IC:none; IC:none; none
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GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF
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IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF
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InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC
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IP; IC:all; IC:all; none
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ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
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ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF
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ITR; itr.i; itr.i, ptr.i; impliedF
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ITR; ptr.i; ptr.i; none
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memory; IC:mem-writers; IC:mem-writers; none
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MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
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PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none
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PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF
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PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF
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PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF
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PR0; IC:pr-writers+1; IC:pr-writers+1; none
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Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.
gas/ChangeLog
* config/tc-ia64.c (dv_sem): Add "stop".
(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
match above.
(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/dv-imply.d: Regenerate.
* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
* ia64-asmtab.c: Regnerate.
2000-09-23 03:43:50 +08:00
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PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none
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PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none
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PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7; impliedF
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PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none
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PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none
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PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF
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2000-04-22 04:22:24 +08:00
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PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none
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PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none
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Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.
gas/ChangeLog
* config/tc-ia64.c (dv_sem): Add "stop".
(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
match above.
(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/dv-imply.d: Regenerate.
* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
* ia64-asmtab.c: Regnerate.
2000-09-23 03:43:50 +08:00
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PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF
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2000-04-22 04:22:24 +08:00
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PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.bn; bsw, rfi; bsw, rfi; impliedF
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PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF
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PSR.da; rfi; rfi; impliedF
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PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
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PSR.dd; rfi; rfi; impliedF
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PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.ed; rfi; rfi; impliedF
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PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.ia; rfi; rfi; impliedF
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PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.id; rfi; rfi; impliedF
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PSR.is; br.ia, rfi; br.ia, rfi; impliedF
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PSR.it; rfi; rfi; impliedF
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PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
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PSR.mc; rfi; rfi; impliedF
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PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none
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PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none
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PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.ri; rfi; rfi; impliedF
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PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
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PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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PSR.ss; rfi; rfi; impliedF
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PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
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PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
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RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF
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RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF
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