binutils-gdb/ld/emultempl/riscvelf.em

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Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
# This shell script emits a C file. -*- C -*-
# Copyright (C) 2004-2023 Free Software Foundation, Inc.
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
#
# This file is part of the GNU Binutils.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
fragment <<EOF
#include "ldmain.h"
#include "ldctor.h"
#include "elf/riscv.h"
#include "elfxx-riscv.h"
static void
riscv_elf_before_allocation (void)
{
gld${EMULATION_NAME}_before_allocation ();
if (link_info.discard == discard_sec_merge)
link_info.discard = discard_l;
if (!bfd_link_relocatable (&link_info))
{
/* We always need at least some relaxation to handle code alignment. */
if (RELAXATION_DISABLED_BY_USER)
TARGET_ENABLE_RELAXATION;
else
ENABLE_RELAXATION;
}
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
RISC-V: Don't separate pcgp relaxation to another relax pass. Commit abd20cb637008da9d32018b4b03973e119388a0a and ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 introduced additional complexity into the paths run by the RISC-V relaxation pass in order to resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo pairs. The first commit split up relaxation of these relocs into a pass which occurred after other relaxations in order to prevent the situation where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting our ability to find the corresponding pcrel_hi relocation from the address attached to the pcrel_lo. Since the relaxation was split into two passes the 'again' parameter could not be used to perform the entire relaxation process again and so the second commit added a way to restart ldelf_map_segments, thus starting the whole process again. Unfortunately this process could not account for the fact that we were not finished with the relaxation process so in some cases - such as the case where code would not fit in a memory region before the R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code would fail. This patch fixes all three of these concerns by reverting back to a system of having only one target relax pass but updating entries in the table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus we can keep track of the pairs accurately, and we can use the 'again' parameter to restart the entire target relax pass, behaving in the way that generic code expects. Unfortunately we must still have an additional pass to delay deleting AUIPC bytes to avoid ambiguity between pcrel_hi relocs stored in the table after deletion. This pass can only be run once so we may potentially miss out on relaxation opportunities but this is likely to be rare. https://sourceware.org/bugzilla/show_bug.cgi?id=28410 bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax. (riscv_elf_link_hash_table_create): Updated. (riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs. Update the pcgp_relocs table whenever bytes are deleted. (riscv_update_pcgp_relocs): Add function to update the section offset of pcrel_hi and pcrel_lo, and also update the symbol value of pcrel_hi. (_bfd_riscv_relax_call): Need to update the pcgp_relocs table when deleting codes. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN, we can't relax anything else, so set the sec->sec_flg0 to true. Besides, we don't need to update the pcgp_relocs table at this stage, so just pass NULL pointer as the pcgp_relocs table for riscv_relax_delete_bytes. (_bfd_riscv_relax_section): Use only one pass for all target relaxations. (_bfd_riscv_relax_delete): Likewise, we don't need to update the pcgp_relocs table at this stage, and don't need to set the `again' since restart_relax mechanism is abandoned. (bfd_elfNN_riscv_restart_relax_sections): Removed. (_bfd_riscv_relax_section): Updated. * elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed. (bfd_elf64_riscv_restart_relax_sections): Likewise. ld/ * emultempl/riscvelf.em: Revert restart_relax changes and set relax_pass to 3. * testsuite/ld-riscv-elf/align-small-region.d: New testcase. * testsuite/ld-riscv-elf/align-small-region.ld: Likewise. * testsuite/ld-riscv-elf/align-small-region.s: Likewise. * testsuite/ld-riscv-elf/restart-relax.d: Removed sine the restart_relax mechanism is abandoned. * testsuite/ld-riscv-elf/restart-relax.s: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-10-21 11:15:47 +08:00
link_info.relax_pass = 3;
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
}
static void
gld${EMULATION_NAME}_after_allocation (void)
{
int need_layout = 0;
/* Don't attempt to discard unused .eh_frame sections until the final link,
as we can't reliably tell if they're used until after relaxation. */
if (!bfd_link_relocatable (&link_info))
{
need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
if (need_layout < 0)
{
einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
return;
}
}
RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 2021-05-31 Nelson Chu <nelson.chu@sifive.com> Lifang Xia <lifang_xia@c-sky.com> The data segment phase exp_seg_relro_adjust means we are still adjusting the relro segments, so we will get the symbol values which havn't consider the relro. It is dangerous and we shouldn't do the relaxations at this stage. Otherwise, we may get the truncated fails when the relax range crossing the data segment. One of the solution is that, we use a pointer to monitor the data segment phase while relaxing, to know whether the relro has been handled or not. Once we check the phase is exp_seg_relro_adjust, we should skip this round of relaxations, since the incorrect symbol values will affect the correctness of relaxations. I think we probably need to record more information about data segment or alignments in the future, to make sure it is safe to doing relaxations. For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get the following truncated errors when using toolchains, which enable relro: (.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o After applying this patch, the truncated errors should be resolved. However, only linux toolchains support -z relro, so we only test these two testcases when supporting shared library. bfd/ PR 27566 * elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer to monitor the data segment phase. (bfd_elfNN_riscv_set_data_segment_info): New function called by after_allocation, to set the data_segment_phase from expld.dataseg. (_bfd_riscv_relax_section): Don't relax when data_segment_phase is exp_seg_relro_adjust (0x4). * elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern. (bfd_elf64_riscv_set_data_segment_info): Likewise. ld/ PR 27566 * emultempl/riscvelf.em (after_allocation): Call riscv_set_data_segment_info to set data segment phase before relaxing. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase. * testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise. * testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise. * testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
2021-05-12 23:26:33 +08:00
/* PR 27566, if the phase of data segment is exp_seg_relro_adjust,
that means we are still adjusting the relro, and shouldn't do the
relaxations at this stage. Otherwise, we will get the symbol
values beofore handling the relro, and may cause truncated fails
when the relax range crossing the data segment. One of the solution
is to monitor the data segment phase while relaxing, to know whether
the relro has been handled or not.
I think we probably need to record more information about data
segment or alignments in the future, to make sure it is safe
to doing relaxations. */
enum phase_enum *phase = &(expld.dataseg.phase);
bfd_elf${ELFSIZE}_riscv_set_data_segment_info (&link_info, (int *) phase);
RISC-V: Don't separate pcgp relaxation to another relax pass. Commit abd20cb637008da9d32018b4b03973e119388a0a and ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 introduced additional complexity into the paths run by the RISC-V relaxation pass in order to resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo pairs. The first commit split up relaxation of these relocs into a pass which occurred after other relaxations in order to prevent the situation where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting our ability to find the corresponding pcrel_hi relocation from the address attached to the pcrel_lo. Since the relaxation was split into two passes the 'again' parameter could not be used to perform the entire relaxation process again and so the second commit added a way to restart ldelf_map_segments, thus starting the whole process again. Unfortunately this process could not account for the fact that we were not finished with the relaxation process so in some cases - such as the case where code would not fit in a memory region before the R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code would fail. This patch fixes all three of these concerns by reverting back to a system of having only one target relax pass but updating entries in the table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus we can keep track of the pairs accurately, and we can use the 'again' parameter to restart the entire target relax pass, behaving in the way that generic code expects. Unfortunately we must still have an additional pass to delay deleting AUIPC bytes to avoid ambiguity between pcrel_hi relocs stored in the table after deletion. This pass can only be run once so we may potentially miss out on relaxation opportunities but this is likely to be rare. https://sourceware.org/bugzilla/show_bug.cgi?id=28410 bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax. (riscv_elf_link_hash_table_create): Updated. (riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs. Update the pcgp_relocs table whenever bytes are deleted. (riscv_update_pcgp_relocs): Add function to update the section offset of pcrel_hi and pcrel_lo, and also update the symbol value of pcrel_hi. (_bfd_riscv_relax_call): Need to update the pcgp_relocs table when deleting codes. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN, we can't relax anything else, so set the sec->sec_flg0 to true. Besides, we don't need to update the pcgp_relocs table at this stage, so just pass NULL pointer as the pcgp_relocs table for riscv_relax_delete_bytes. (_bfd_riscv_relax_section): Use only one pass for all target relaxations. (_bfd_riscv_relax_delete): Likewise, we don't need to update the pcgp_relocs table at this stage, and don't need to set the `again' since restart_relax mechanism is abandoned. (bfd_elfNN_riscv_restart_relax_sections): Removed. (_bfd_riscv_relax_section): Updated. * elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed. (bfd_elf64_riscv_restart_relax_sections): Likewise. ld/ * emultempl/riscvelf.em: Revert restart_relax changes and set relax_pass to 3. * testsuite/ld-riscv-elf/align-small-region.d: New testcase. * testsuite/ld-riscv-elf/align-small-region.ld: Likewise. * testsuite/ld-riscv-elf/align-small-region.s: Likewise. * testsuite/ld-riscv-elf/restart-relax.d: Removed sine the restart_relax mechanism is abandoned. * testsuite/ld-riscv-elf/restart-relax.s: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-10-21 11:15:47 +08:00
ldelf_map_segments (need_layout);
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
}
/* This is a convenient point to tell BFD about target specific flags.
After the output has been created, but before inputs are read. */
static void
riscv_create_output_section_statements (void)
{
/* See PR 22920 for an example of why this is necessary. */
if (strstr (bfd_get_target (link_info.output_bfd), "riscv") == NULL)
{
/* The RISC-V backend needs special fields in the output hash structure.
These will only be created if the output format is a RISC-V format,
hence we do not support linking and changing output formats at the
same time. Use a link followed by objcopy to change output formats. */
einfo (_("%F%P: error: cannot change output format"
" whilst linking %s binaries\n"), "RISC-V");
return;
}
}
Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-11-02 00:45:57 +08:00
EOF
LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation
LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=riscv_create_output_section_statements