mirror of
https://sourceware.org/git/binutils-gdb.git
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244 lines
4.0 KiB
ArmAsm
244 lines
4.0 KiB
ArmAsm
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//Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp
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// Spec Reference: cc2stat cc aq
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00000000;
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imm32 r1, 0x00000000;
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imm32 r2, 0x00000000;
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imm32 r3, 0x00000000;
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imm32 r4, 0x00000000;
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imm32 r5, 0x00000000;
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imm32 r6, 0x00000000;
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imm32 r7, 0x00000000;
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// test CC = AQ 0-0, 0-1, 1-0, 1-1
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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CC = AQ; //
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R0 = CC; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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CC = AQ; //
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R1 = CC; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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CC = AQ; //
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R2 = CC; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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CC = AQ; //
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R3 = CC; //
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// test cc |= AQ (0-0, 0-1, 1-0, 1-1)
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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CC |= AQ; //
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R4 = CC; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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CC |= AQ; //
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R5 = CC; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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CC |= AQ; //
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R6 = CC; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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CC |= AQ; //
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R7 = CC; //
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000001;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000001;
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CHECKREG r6, 0x00000001;
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CHECKREG r7, 0x00000001;
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// test CC &= AQ (0-0, 0-1, 1-0, 1-1)
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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CC &= AQ; //
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R4 = CC; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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CC &= AQ; //
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R5 = CC; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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CC &= AQ; //
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R6 = CC; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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CC &= AQ; //
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R7 = CC; //
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000001;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000001;
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// test CC ^= AQ (0-0, 0-1, 1-0, 1-1)
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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CC ^= AQ; //
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R4 = CC; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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CC ^= AQ; //
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R5 = CC; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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CC ^= AQ; //
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R6 = CC; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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CC ^= AQ; //
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R7 = CC; //
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000001;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000001;
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CHECKREG r6, 0x00000001;
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CHECKREG r7, 0x00000000;
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// test AQ = CC 0-0, 0-1, 1-0, 1-1
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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AQ = CC; //
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R0 = ASTAT; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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AQ = CC; //
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R1 = ASTAT; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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AQ = CC; //
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R2 = ASTAT; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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AQ = CC; //
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R3 = ASTAT; //
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// test AQ |= CC (0-0, 0-1, 1-0, 1-1)
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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AQ |= CC; //
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R4 = ASTAT; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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AQ |= CC; //
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R5 = ASTAT; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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AQ |= CC; //
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R6 = ASTAT; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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AQ |= CC; //
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R7 = ASTAT; //
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000060;
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CHECKREG r3, 0x00000060;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000040;
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CHECKREG r6, 0x00000060;
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CHECKREG r7, 0x00000060;
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// test AQ &= CC (0-0, 0-1, 1-0, 1-1)
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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AQ &= CC; //
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R4 = ASTAT; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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AQ &= CC; //
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R5 = ASTAT; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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AQ &= CC; //
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R6 = ASTAT; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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AQ &= CC; //
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R7 = ASTAT; //
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000060;
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CHECKREG r3, 0x00000060;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000020;
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CHECKREG r7, 0x00000060;
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// test AQ ^= CC (0-0, 0-1, 1-0, 1-1)
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R7 = 0x00;
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ASTAT = R7; // cc = 0, AQ = 0
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AQ ^= CC; //
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R4 = ASTAT; //
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R7 = 0x40 (X);
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ASTAT = R7; // cc = 0, AQ = 1
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AQ ^= CC; //
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R5 = ASTAT; //
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R7 = 0x20;
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ASTAT = R7; // cc = 1, AQ = 0
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AQ ^= CC; //
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R6 = ASTAT; //
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R7 = 0x60 (X);
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ASTAT = R7; // cc = 1, AQ = 1
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AQ ^= CC; //
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R7 = ASTAT; //
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000060;
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CHECKREG r3, 0x00000060;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000040;
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CHECKREG r6, 0x00000060;
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CHECKREG r7, 0x00000020;
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pass
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