2016-07-07 01:36:49 +08:00
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/* Target dependent code for GNU/Linux ARC.
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2024-01-12 23:30:44 +08:00
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Copyright 2020-2024 Free Software Foundation, Inc.
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2016-07-07 01:36:49 +08:00
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* GDB header files. */
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#include "linux-tdep.h"
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#include "objfiles.h"
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#include "opcode/arc.h"
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#include "osabi.h"
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#include "solib-svr4.h"
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2022-04-05 04:07:54 +08:00
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#include "disasm.h"
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2016-07-07 01:36:49 +08:00
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/* ARC header files. */
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#include "opcodes/arc-dis.h"
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2017-01-30 23:32:10 +08:00
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#include "arc-linux-tdep.h"
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2016-07-07 01:36:49 +08:00
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#include "arc-tdep.h"
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2017-01-30 23:32:10 +08:00
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#include "arch/arc.h"
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2021-01-14 03:32:39 +08:00
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/* Print an "arc-linux" debug statement. */
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#define arc_linux_debug_printf(fmt, ...) \
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debug_prefixed_printf_cond (arc_debug, "arc-linux", fmt, ##__VA_ARGS__)
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2017-01-30 23:32:10 +08:00
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#define REGOFF(offset) (offset * ARC_REGISTER_SIZE)
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2016-12-23 02:52:16 +08:00
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/* arc_linux_sc_reg_offsets[i] is the offset of register i in the `struct
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sigcontext'. Array index is an internal GDB register number, as defined in
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arc-tdep.h:arc_regnum.
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From <include/uapi/asm/sigcontext.h> and <include/uapi/asm/ptrace.h>.
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The layout of this struct is tightly bound to "arc_regnum" enum
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in arc-tdep.h. Any change of order in there, must be reflected
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here as well. */
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static const int arc_linux_sc_reg_offsets[] = {
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/* R0 - R12. */
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REGOFF (22), REGOFF (21), REGOFF (20), REGOFF (19),
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REGOFF (18), REGOFF (17), REGOFF (16), REGOFF (15),
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REGOFF (14), REGOFF (13), REGOFF (12), REGOFF (11),
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REGOFF (10),
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/* R13 - R25. */
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER,
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REGOFF (9), /* R26 (GP) */
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REGOFF (8), /* FP */
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REGOFF (23), /* SP */
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ARC_OFFSET_NO_REGISTER, /* ILINK */
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ARC_OFFSET_NO_REGISTER, /* R30 */
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REGOFF (7), /* BLINK */
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/* R32 - R59. */
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER,
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REGOFF (4), /* LP_COUNT */
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ARC_OFFSET_NO_REGISTER, /* RESERVED */
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ARC_OFFSET_NO_REGISTER, /* LIMM */
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ARC_OFFSET_NO_REGISTER, /* PCL */
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REGOFF (6), /* PC */
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REGOFF (5), /* STATUS32 */
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REGOFF (2), /* LP_START */
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REGOFF (3), /* LP_END */
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REGOFF (1), /* BTA */
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};
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2017-01-30 23:32:10 +08:00
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/* arc_linux_core_reg_offsets[i] is the offset in the .reg section of GDB
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regnum i. Array index is an internal GDB register number, as defined in
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arc-tdep.h:arc_regnum.
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From include/uapi/asm/ptrace.h in the ARC Linux sources. */
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/* The layout of this struct is tightly bound to "arc_regnum" enum
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in arc-tdep.h. Any change of order in there, must be reflected
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here as well. */
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static const int arc_linux_core_reg_offsets[] = {
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/* R0 - R12. */
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REGOFF (22), REGOFF (21), REGOFF (20), REGOFF (19),
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REGOFF (18), REGOFF (17), REGOFF (16), REGOFF (15),
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REGOFF (14), REGOFF (13), REGOFF (12), REGOFF (11),
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REGOFF (10),
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/* R13 - R25. */
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REGOFF (37), REGOFF (36), REGOFF (35), REGOFF (34),
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REGOFF (33), REGOFF (32), REGOFF (31), REGOFF (30),
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REGOFF (29), REGOFF (28), REGOFF (27), REGOFF (26),
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REGOFF (25),
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REGOFF (9), /* R26 (GP) */
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REGOFF (8), /* FP */
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REGOFF (23), /* SP */
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ARC_OFFSET_NO_REGISTER, /* ILINK */
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ARC_OFFSET_NO_REGISTER, /* R30 */
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REGOFF (7), /* BLINK */
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/* R32 - R59. */
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER, ARC_OFFSET_NO_REGISTER,
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ARC_OFFSET_NO_REGISTER,
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REGOFF (4), /* LP_COUNT */
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ARC_OFFSET_NO_REGISTER, /* RESERVED */
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ARC_OFFSET_NO_REGISTER, /* LIMM */
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ARC_OFFSET_NO_REGISTER, /* PCL */
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REGOFF (39), /* PC */
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REGOFF (5), /* STATUS32 */
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REGOFF (2), /* LP_START */
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REGOFF (3), /* LP_END */
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REGOFF (1), /* BTA */
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REGOFF (6) /* ERET */
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};
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2016-07-07 01:36:49 +08:00
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2016-12-23 02:52:16 +08:00
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/* Is THIS_FRAME a sigtramp function - the function that returns from
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signal handler into normal execution flow? This is the case if the PC is
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either at the start of, or in the middle of the two instructions:
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mov r8, __NR_rt_sigreturn ; __NR_rt_sigreturn == 139
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trap_s 0 ; `swi' for ARC700
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On ARC uClibc Linux this function is called __default_rt_sa_restorer.
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Returns TRUE if this is a sigtramp frame. */
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static bool
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gdb: pass frames as `const frame_info_ptr &`
We currently pass frames to function by value, as `frame_info_ptr`.
This is somewhat expensive:
- the size of `frame_info_ptr` is 64 bytes, which is a bit big to pass
by value
- the constructors and destructor link/unlink the object in the global
`frame_info_ptr::frame_list` list. This is an `intrusive_list`, so
it's not so bad: it's just assigning a few points, there's no memory
allocation as if it was `std::list`, but still it's useless to do
that over and over.
As suggested by Tom Tromey, change many function signatures to accept
`const frame_info_ptr &` instead of `frame_info_ptr`.
Some functions reassign their `frame_info_ptr` parameter, like:
void
the_func (frame_info_ptr frame)
{
for (; frame != nullptr; frame = get_prev_frame (frame))
{
...
}
}
I wondered what to do about them, do I leave them as-is or change them
(and need to introduce a separate local variable that can be
re-assigned). I opted for the later for consistency. It might not be
clear why some functions take `const frame_info_ptr &` while others take
`frame_info_ptr`. Also, if a function took a `frame_info_ptr` because
it did re-assign its parameter, I doubt that we would think to change it
to `const frame_info_ptr &` should the implementation change such that
it doesn't need to take `frame_info_ptr` anymore. It seems better to
have a simple rule and apply it everywhere.
Change-Id: I59d10addef687d157f82ccf4d54f5dde9a963fd0
Approved-By: Andrew Burgess <aburgess@redhat.com>
2024-02-20 02:07:47 +08:00
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arc_linux_is_sigtramp (const frame_info_ptr &this_frame)
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2016-12-23 02:52:16 +08:00
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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CORE_ADDR pc = get_frame_pc (this_frame);
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2021-01-14 03:32:39 +08:00
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arc_linux_debug_printf ("pc=%s", paddress(gdbarch, pc));
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2016-12-23 02:52:16 +08:00
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static const gdb_byte insns_be_hs[] = {
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0x20, 0x8a, 0x12, 0xc2, /* mov r8,nr_rt_sigreturn */
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0x78, 0x1e /* trap_s 0 */
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};
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static const gdb_byte insns_be_700[] = {
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0x20, 0x8a, 0x12, 0xc2, /* mov r8,nr_rt_sigreturn */
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0x22, 0x6f, 0x00, 0x3f /* swi */
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};
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gdb_byte arc_sigtramp_insns[sizeof (insns_be_700)];
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size_t insns_sz;
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if (arc_mach_is_arcv2 (gdbarch))
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{
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insns_sz = sizeof (insns_be_hs);
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memcpy (arc_sigtramp_insns, insns_be_hs, insns_sz);
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}
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else
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{
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insns_sz = sizeof (insns_be_700);
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memcpy (arc_sigtramp_insns, insns_be_700, insns_sz);
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}
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if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
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{
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/* On little endian targets, ARC code section is in what is called
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"middle endian", where half-words are in the big-endian order,
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only bytes inside the halfwords are in the little endian order.
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As a result it is very easy to convert big endian instruction to
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little endian, since it is needed to swap bytes in the halfwords,
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so there is no need to have information on whether that is a
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4-byte instruction or 2-byte. */
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gdb_assert ((insns_sz % 2) == 0);
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for (int i = 0; i < insns_sz; i += 2)
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std::swap (arc_sigtramp_insns[i], arc_sigtramp_insns[i+1]);
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}
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gdb_byte buf[insns_sz];
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/* Read the memory at the PC. Since we are stopped, any breakpoint must
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have been removed. */
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2021-01-16 00:16:04 +08:00
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if (!safe_frame_unwind_memory (this_frame, pc, {buf, insns_sz}))
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2016-12-23 02:52:16 +08:00
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{
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/* Failed to unwind frame. */
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return FALSE;
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}
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/* Is that code the sigtramp instruction sequence? */
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if (memcmp (buf, arc_sigtramp_insns, insns_sz) == 0)
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return TRUE;
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/* No - look one instruction earlier in the code... */
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2021-01-16 00:16:04 +08:00
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if (!safe_frame_unwind_memory (this_frame, pc - 4, {buf, insns_sz}))
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2016-12-23 02:52:16 +08:00
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{
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/* Failed to unwind frame. */
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return FALSE;
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}
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return (memcmp (buf, arc_sigtramp_insns, insns_sz) == 0);
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}
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/* Get sigcontext structure of sigtramp frame - it contains saved
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registers of interrupted frame.
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Stack pointer points to the rt_sigframe structure, and sigcontext can
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be found as in:
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struct rt_sigframe {
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struct siginfo info;
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struct ucontext uc;
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...
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};
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struct ucontext {
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unsigned long uc_flags;
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struct ucontext *uc_link;
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stack_t uc_stack;
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struct sigcontext uc_mcontext;
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sigset_t uc_sigmask;
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};
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sizeof (struct siginfo) == 0x80
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offsetof (struct ucontext, uc_mcontext) == 0x14
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GDB cannot include linux headers and use offsetof () because those are
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target headers and GDB might be built for a different run host. There
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doesn't seem to be an established mechanism to figure out those offsets
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via gdbserver, so the only way is to hardcode values in the GDB,
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meaning that GDB will be broken if values will change. That seems to
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be a very unlikely scenario and other arches (aarch64, alpha, amd64,
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etc) in GDB hardcode values. */
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static CORE_ADDR
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gdb: pass frames as `const frame_info_ptr &`
We currently pass frames to function by value, as `frame_info_ptr`.
This is somewhat expensive:
- the size of `frame_info_ptr` is 64 bytes, which is a bit big to pass
by value
- the constructors and destructor link/unlink the object in the global
`frame_info_ptr::frame_list` list. This is an `intrusive_list`, so
it's not so bad: it's just assigning a few points, there's no memory
allocation as if it was `std::list`, but still it's useless to do
that over and over.
As suggested by Tom Tromey, change many function signatures to accept
`const frame_info_ptr &` instead of `frame_info_ptr`.
Some functions reassign their `frame_info_ptr` parameter, like:
void
the_func (frame_info_ptr frame)
{
for (; frame != nullptr; frame = get_prev_frame (frame))
{
...
}
}
I wondered what to do about them, do I leave them as-is or change them
(and need to introduce a separate local variable that can be
re-assigned). I opted for the later for consistency. It might not be
clear why some functions take `const frame_info_ptr &` while others take
`frame_info_ptr`. Also, if a function took a `frame_info_ptr` because
it did re-assign its parameter, I doubt that we would think to change it
to `const frame_info_ptr &` should the implementation change such that
it doesn't need to take `frame_info_ptr` anymore. It seems better to
have a simple rule and apply it everywhere.
Change-Id: I59d10addef687d157f82ccf4d54f5dde9a963fd0
Approved-By: Andrew Burgess <aburgess@redhat.com>
2024-02-20 02:07:47 +08:00
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arc_linux_sigcontext_addr (const frame_info_ptr &this_frame)
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2016-12-23 02:52:16 +08:00
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{
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const int ucontext_offset = 0x80;
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const int sigcontext_offset = 0x14;
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return get_frame_sp (this_frame) + ucontext_offset + sigcontext_offset;
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}
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|
2016-07-07 01:36:49 +08:00
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|
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/* Implement the "cannot_fetch_register" gdbarch method. */
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static int
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arc_linux_cannot_fetch_register (struct gdbarch *gdbarch, int regnum)
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{
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/* Assume that register is readable if it is unknown. */
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switch (regnum)
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{
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|
|
|
case ARC_ILINK_REGNUM:
|
|
|
|
case ARC_RESERVED_REGNUM:
|
|
|
|
case ARC_LIMM_REGNUM:
|
|
|
|
return true;
|
|
|
|
case ARC_R30_REGNUM:
|
|
|
|
case ARC_R58_REGNUM:
|
|
|
|
case ARC_R59_REGNUM:
|
|
|
|
return !arc_mach_is_arcv2 (gdbarch);
|
|
|
|
}
|
|
|
|
return (regnum > ARC_BLINK_REGNUM) && (regnum < ARC_LP_COUNT_REGNUM);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Implement the "cannot_store_register" gdbarch method. */
|
|
|
|
|
|
|
|
static int
|
|
|
|
arc_linux_cannot_store_register (struct gdbarch *gdbarch, int regnum)
|
|
|
|
{
|
|
|
|
/* Assume that register is writable if it is unknown. */
|
|
|
|
switch (regnum)
|
|
|
|
{
|
|
|
|
case ARC_ILINK_REGNUM:
|
|
|
|
case ARC_RESERVED_REGNUM:
|
|
|
|
case ARC_LIMM_REGNUM:
|
|
|
|
case ARC_PCL_REGNUM:
|
|
|
|
return true;
|
|
|
|
case ARC_R30_REGNUM:
|
|
|
|
case ARC_R58_REGNUM:
|
|
|
|
case ARC_R59_REGNUM:
|
|
|
|
return !arc_mach_is_arcv2 (gdbarch);
|
|
|
|
}
|
|
|
|
return (regnum > ARC_BLINK_REGNUM) && (regnum < ARC_LP_COUNT_REGNUM);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For ARC Linux, breakpoints use the 16-bit TRAP_S 1 instruction, which
|
|
|
|
is 0x3e78 (little endian) or 0x783e (big endian). */
|
|
|
|
|
|
|
|
static const gdb_byte arc_linux_trap_s_be[] = { 0x78, 0x3e };
|
|
|
|
static const gdb_byte arc_linux_trap_s_le[] = { 0x3e, 0x78 };
|
|
|
|
static const int trap_size = 2; /* Number of bytes to insert "trap". */
|
|
|
|
|
|
|
|
/* Implement the "breakpoint_kind_from_pc" gdbarch method. */
|
|
|
|
|
|
|
|
static int
|
|
|
|
arc_linux_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
|
|
|
|
{
|
|
|
|
return trap_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Implement the "sw_breakpoint_from_kind" gdbarch method. */
|
|
|
|
|
|
|
|
static const gdb_byte *
|
|
|
|
arc_linux_sw_breakpoint_from_kind (struct gdbarch *gdbarch,
|
|
|
|
int kind, int *size)
|
|
|
|
{
|
gdb/arc: fix print_one_insn selftest
I noticed that the ARC print_one_insn selftest was failing. The
problem is that in print_one_insn_test the arc case falls through into
the special case that handles nios2, score, and riscv.
The special case for these targets hard codes the breakpoint kind to
'4'. This is find for bare metal arc (see arc-tdep.c,
arc_sw_breakpoint_from_kind), however, for arc/linux only breakpoint
kind '2' is supported (see arc-linux-tdep.c,
arc_linux_sw_breakpoint_from_kind).
So the code in print_one_insn_test as it is currently written passed
in an invalid breakpoint kind, this leads to GDB trying to disassemble
unexpected memory.
The fix is to reorder the code in print_one_insn_test so that the arc
case falls through into the default case. In the default we no longer
hard code the breakpoint kind, and everything should be good.
Additionally, given the arc code only expects specific breakpoint kind
values, I thought it would be nice to add some gdb_assert to validate
things. This assert would have triggered in this case and made it
easier to find the error.
After this commit, configure GDB with --enable-targets=all, then run
gdb.gdb/unittest.exp, there should no longer be any failures.
gdb/ChangeLog:
* arc-linux-tdep.c (arc_linux_sw_breakpoint_from_kind): Add an
assert.
* arc-tdep.c (arc_breakpoint_kind_from_pc): Likewise.
* disasm-selftests.c (print_one_insn_test): Fall throough from ARC
case to the default.
2020-11-16 23:31:16 +08:00
|
|
|
gdb_assert (kind == trap_size);
|
2016-07-07 01:36:49 +08:00
|
|
|
*size = kind;
|
|
|
|
return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
|
|
|
|
? arc_linux_trap_s_be
|
|
|
|
: arc_linux_trap_s_le);
|
|
|
|
}
|
|
|
|
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
/* Check for an atomic sequence of instructions beginning with an
|
|
|
|
LLOCK instruction and ending with a SCOND instruction.
|
|
|
|
|
|
|
|
These patterns are hand coded in libc's (glibc and uclibc). Take
|
|
|
|
a look at [1] for instance:
|
|
|
|
|
|
|
|
main+14: llock r2,[r0]
|
|
|
|
main+18: brne.nt r2,0,main+30
|
|
|
|
main+22: scond r3,[r0]
|
|
|
|
main+26: bne main+14
|
|
|
|
main+30: mov_s r0,0
|
|
|
|
|
|
|
|
If such a sequence is found, attempt to step over it.
|
|
|
|
A breakpoint is placed at the end of the sequence.
|
|
|
|
|
|
|
|
This function expects the INSN to be a "llock(d)" instruction.
|
|
|
|
|
|
|
|
[1]
|
|
|
|
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/ \
|
|
|
|
sysdeps/linux/arc/bits/atomic.h#n46
|
|
|
|
*/
|
|
|
|
|
|
|
|
static std::vector<CORE_ADDR>
|
gdb: refactor the non-printing disassemblers
This commit started from an observation I made while working on some
other disassembler patches, that is, that the function
gdb_buffered_insn_length, is broken ... sort of.
I noticed that the gdb_buffered_insn_length function doesn't set up
the application data field if the disassemble_info structure.
Further, I noticed that some architectures, for example, ARM, require
that the application_data field be set, see gdb_print_insn_arm in
arm-tdep.c.
And so, if we ever use gdb_buffered_insn_length for ARM, then GDB will
likely crash. Which is why I said only "sort of" broken. Right now
we don't use gdb_buffered_insn_length with ARM, so maybe it isn't
broken yet?
Anyway to prove to myself that there was a problem here I extended the
disassembler self tests in disasm-selftests.c to include a test of
gdb_buffered_insn_length. As I run the test for all architectures, I
do indeed see GDB crash for ARM.
To fix this we need gdb_buffered_insn_length to create a disassembler
that inherits from gdb_disassemble_info, but we also need this new
disassembler to not print anything.
And so, I introduce a new gdb_non_printing_disassembler class, this is
a disassembler that doesn't print anything to the output stream.
I then observed that both ARC and S12Z also create non-printing
disassemblers, but these are slightly different. While the
disassembler in gdb_non_printing_disassembler reads the instruction
from a buffer, the ARC and S12Z disassemblers read from target memory
using target_read_code.
And so, I further split gdb_non_printing_disassembler into two
sub-classes, gdb_non_printing_memory_disassembler and
gdb_non_printing_buffer_disassembler.
The new selftests now pass, but otherwise, there should be no user
visible changes after this commit.
2022-04-04 22:48:19 +08:00
|
|
|
handle_atomic_sequence (arc_instruction insn, disassemble_info *di)
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
{
|
|
|
|
const int atomic_seq_len = 24; /* Instruction sequence length. */
|
|
|
|
std::vector<CORE_ADDR> next_pcs;
|
|
|
|
|
|
|
|
/* Sanity check. */
|
|
|
|
gdb_assert (insn.insn_class == LLOCK);
|
|
|
|
|
|
|
|
/* Data size we are dealing with: LLOCK vs. LLOCKD */
|
|
|
|
arc_ldst_data_size llock_data_size_mode = insn.data_size_mode;
|
|
|
|
/* Indicator if any conditional branch is found in the sequence. */
|
|
|
|
bool found_bc = false;
|
|
|
|
/* Becomes true if "LLOCK(D) .. SCOND(D)" sequence is found. */
|
|
|
|
bool is_pattern_valid = false;
|
|
|
|
|
|
|
|
for (int insn_count = 0; insn_count < atomic_seq_len; ++insn_count)
|
|
|
|
{
|
|
|
|
arc_insn_decode (arc_insn_get_linear_next_pc (insn),
|
gdb: refactor the non-printing disassemblers
This commit started from an observation I made while working on some
other disassembler patches, that is, that the function
gdb_buffered_insn_length, is broken ... sort of.
I noticed that the gdb_buffered_insn_length function doesn't set up
the application data field if the disassemble_info structure.
Further, I noticed that some architectures, for example, ARM, require
that the application_data field be set, see gdb_print_insn_arm in
arm-tdep.c.
And so, if we ever use gdb_buffered_insn_length for ARM, then GDB will
likely crash. Which is why I said only "sort of" broken. Right now
we don't use gdb_buffered_insn_length with ARM, so maybe it isn't
broken yet?
Anyway to prove to myself that there was a problem here I extended the
disassembler self tests in disasm-selftests.c to include a test of
gdb_buffered_insn_length. As I run the test for all architectures, I
do indeed see GDB crash for ARM.
To fix this we need gdb_buffered_insn_length to create a disassembler
that inherits from gdb_disassemble_info, but we also need this new
disassembler to not print anything.
And so, I introduce a new gdb_non_printing_disassembler class, this is
a disassembler that doesn't print anything to the output stream.
I then observed that both ARC and S12Z also create non-printing
disassemblers, but these are slightly different. While the
disassembler in gdb_non_printing_disassembler reads the instruction
from a buffer, the ARC and S12Z disassemblers read from target memory
using target_read_code.
And so, I further split gdb_non_printing_disassembler into two
sub-classes, gdb_non_printing_memory_disassembler and
gdb_non_printing_buffer_disassembler.
The new selftests now pass, but otherwise, there should be no user
visible changes after this commit.
2022-04-04 22:48:19 +08:00
|
|
|
di, arc_delayed_print_insn, &insn);
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
|
|
|
|
if (insn.insn_class == BRCC)
|
2023-03-10 03:56:09 +08:00
|
|
|
{
|
|
|
|
/* If more than one conditional branch is found, this is not
|
|
|
|
the pattern we are interested in. */
|
|
|
|
if (found_bc)
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
break;
|
|
|
|
found_bc = true;
|
|
|
|
continue;
|
2023-03-10 03:56:09 +08:00
|
|
|
}
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
|
|
|
|
/* This is almost a happy ending. */
|
|
|
|
if (insn.insn_class == SCOND)
|
2023-03-10 03:56:09 +08:00
|
|
|
{
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
/* SCOND should match the LLOCK's data size. */
|
|
|
|
if (insn.data_size_mode == llock_data_size_mode)
|
|
|
|
is_pattern_valid = true;
|
|
|
|
break;
|
2023-03-10 03:56:09 +08:00
|
|
|
}
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (is_pattern_valid)
|
|
|
|
{
|
|
|
|
/* Get next instruction after scond(d). There is no limm. */
|
|
|
|
next_pcs.push_back (insn.address + insn.length);
|
|
|
|
}
|
|
|
|
|
|
|
|
return next_pcs;
|
|
|
|
}
|
|
|
|
|
2016-07-07 01:36:49 +08:00
|
|
|
/* Implement the "software_single_step" gdbarch method. */
|
|
|
|
|
|
|
|
static std::vector<CORE_ADDR>
|
|
|
|
arc_linux_software_single_step (struct regcache *regcache)
|
|
|
|
{
|
|
|
|
struct gdbarch *gdbarch = regcache->arch ();
|
gdb: move the type cast into gdbarch_tdep
I built GDB for all targets on a x86-64/GNU-Linux system, and
then (accidentally) passed GDB a RISC-V binary, and asked GDB to "run"
the binary on the native target. I got this error:
(gdb) show architecture
The target architecture is set to "auto" (currently "i386").
(gdb) file /tmp/hello.rv32.exe
Reading symbols from /tmp/hello.rv32.exe...
(gdb) show architecture
The target architecture is set to "auto" (currently "riscv:rv32").
(gdb) run
Starting program: /tmp/hello.rv32.exe
../../src/gdb/i387-tdep.c:596: internal-error: i387_supply_fxsave: Assertion `tdep->st0_regnum >= I386_ST0_REGNUM' failed.
What's going on here is this; initially the architecture is i386, this
is based on the default architecture, which is set based on the native
target. After loading the RISC-V executable the architecture of the
current inferior is updated based on the architecture of the
executable.
When we "run", GDB does a fork & exec, with the inferior being
controlled through ptrace. GDB sees an initial stop from the inferior
as soon as the inferior comes to life. In response to this stop GDB
ends up calling save_stop_reason (linux-nat.c), which ends up trying
to read register from the inferior, to do this we end up calling
target_ops::fetch_registers, which, for the x86-64 native target,
calls amd64_linux_nat_target::fetch_registers.
After this I eventually end up in i387_supply_fxsave, different x86
based targets will end in different functions to fetch registers, but
it doesn't really matter which function we end up in, the problem is
this line, which is repeated in many places:
i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
The problem here is that the ARCH in this line comes from the current
inferior, which, as we discussed above, will be a RISC-V gdbarch, the
tdep field will actually be of type riscv_gdbarch_tdep, not
i386_gdbarch_tdep. After this cast we are relying on undefined
behaviour, in my case I happen to trigger an assert, but this might
not always be the case.
The thing I tried that exposed this problem was of course, trying to
start an executable of the wrong architecture on a native target. I
don't think that the correct solution for this problem is to detect,
at the point of cast, that the gdbarch_tdep object is of the wrong
type, but, I did wonder, is there a way that we could protect
ourselves from incorrectly casting the gdbarch_tdep object?
I think that there is something we can do here, and this commit is the
first step in that direction, though no actual check is added by this
commit.
This commit can be split into two parts:
(1) In gdbarch.h and arch-utils.c. In these files I have modified
gdbarch_tdep (the function) so that it now takes a template argument,
like this:
template<typename TDepType>
static inline TDepType *
gdbarch_tdep (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep_1 (gdbarch);
return static_cast<TDepType *> (tdep);
}
After this change we are no better protected, but the cast is now
done within the gdbarch_tdep function rather than at the call sites,
this leads to the second, much larger change in this commit,
(2) Everywhere gdbarch_tdep is called, we make changes like this:
- i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
+ i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
There should be no functional change after this commit.
In the next commit I will build on this change to add an assertion in
gdbarch_tdep that checks we are casting to the correct type.
2022-05-19 20:20:17 +08:00
|
|
|
arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (gdbarch);
|
gdb: refactor the non-printing disassemblers
This commit started from an observation I made while working on some
other disassembler patches, that is, that the function
gdb_buffered_insn_length, is broken ... sort of.
I noticed that the gdb_buffered_insn_length function doesn't set up
the application data field if the disassemble_info structure.
Further, I noticed that some architectures, for example, ARM, require
that the application_data field be set, see gdb_print_insn_arm in
arm-tdep.c.
And so, if we ever use gdb_buffered_insn_length for ARM, then GDB will
likely crash. Which is why I said only "sort of" broken. Right now
we don't use gdb_buffered_insn_length with ARM, so maybe it isn't
broken yet?
Anyway to prove to myself that there was a problem here I extended the
disassembler self tests in disasm-selftests.c to include a test of
gdb_buffered_insn_length. As I run the test for all architectures, I
do indeed see GDB crash for ARM.
To fix this we need gdb_buffered_insn_length to create a disassembler
that inherits from gdb_disassemble_info, but we also need this new
disassembler to not print anything.
And so, I introduce a new gdb_non_printing_disassembler class, this is
a disassembler that doesn't print anything to the output stream.
I then observed that both ARC and S12Z also create non-printing
disassemblers, but these are slightly different. While the
disassembler in gdb_non_printing_disassembler reads the instruction
from a buffer, the ARC and S12Z disassemblers read from target memory
using target_read_code.
And so, I further split gdb_non_printing_disassembler into two
sub-classes, gdb_non_printing_memory_disassembler and
gdb_non_printing_buffer_disassembler.
The new selftests now pass, but otherwise, there should be no user
visible changes after this commit.
2022-04-04 22:48:19 +08:00
|
|
|
struct gdb_non_printing_memory_disassembler dis (gdbarch);
|
2016-07-07 01:36:49 +08:00
|
|
|
|
|
|
|
/* Read current instruction. */
|
|
|
|
struct arc_instruction curr_insn;
|
gdb: refactor the non-printing disassemblers
This commit started from an observation I made while working on some
other disassembler patches, that is, that the function
gdb_buffered_insn_length, is broken ... sort of.
I noticed that the gdb_buffered_insn_length function doesn't set up
the application data field if the disassemble_info structure.
Further, I noticed that some architectures, for example, ARM, require
that the application_data field be set, see gdb_print_insn_arm in
arm-tdep.c.
And so, if we ever use gdb_buffered_insn_length for ARM, then GDB will
likely crash. Which is why I said only "sort of" broken. Right now
we don't use gdb_buffered_insn_length with ARM, so maybe it isn't
broken yet?
Anyway to prove to myself that there was a problem here I extended the
disassembler self tests in disasm-selftests.c to include a test of
gdb_buffered_insn_length. As I run the test for all architectures, I
do indeed see GDB crash for ARM.
To fix this we need gdb_buffered_insn_length to create a disassembler
that inherits from gdb_disassemble_info, but we also need this new
disassembler to not print anything.
And so, I introduce a new gdb_non_printing_disassembler class, this is
a disassembler that doesn't print anything to the output stream.
I then observed that both ARC and S12Z also create non-printing
disassemblers, but these are slightly different. While the
disassembler in gdb_non_printing_disassembler reads the instruction
from a buffer, the ARC and S12Z disassemblers read from target memory
using target_read_code.
And so, I further split gdb_non_printing_disassembler into two
sub-classes, gdb_non_printing_memory_disassembler and
gdb_non_printing_buffer_disassembler.
The new selftests now pass, but otherwise, there should be no user
visible changes after this commit.
2022-04-04 22:48:19 +08:00
|
|
|
arc_insn_decode (regcache_read_pc (regcache), dis.disasm_info (),
|
|
|
|
arc_delayed_print_insn, &curr_insn);
|
2016-07-07 01:36:49 +08:00
|
|
|
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
if (curr_insn.insn_class == LLOCK)
|
gdb: refactor the non-printing disassemblers
This commit started from an observation I made while working on some
other disassembler patches, that is, that the function
gdb_buffered_insn_length, is broken ... sort of.
I noticed that the gdb_buffered_insn_length function doesn't set up
the application data field if the disassemble_info structure.
Further, I noticed that some architectures, for example, ARM, require
that the application_data field be set, see gdb_print_insn_arm in
arm-tdep.c.
And so, if we ever use gdb_buffered_insn_length for ARM, then GDB will
likely crash. Which is why I said only "sort of" broken. Right now
we don't use gdb_buffered_insn_length with ARM, so maybe it isn't
broken yet?
Anyway to prove to myself that there was a problem here I extended the
disassembler self tests in disasm-selftests.c to include a test of
gdb_buffered_insn_length. As I run the test for all architectures, I
do indeed see GDB crash for ARM.
To fix this we need gdb_buffered_insn_length to create a disassembler
that inherits from gdb_disassemble_info, but we also need this new
disassembler to not print anything.
And so, I introduce a new gdb_non_printing_disassembler class, this is
a disassembler that doesn't print anything to the output stream.
I then observed that both ARC and S12Z also create non-printing
disassemblers, but these are slightly different. While the
disassembler in gdb_non_printing_disassembler reads the instruction
from a buffer, the ARC and S12Z disassemblers read from target memory
using target_read_code.
And so, I further split gdb_non_printing_disassembler into two
sub-classes, gdb_non_printing_memory_disassembler and
gdb_non_printing_buffer_disassembler.
The new selftests now pass, but otherwise, there should be no user
visible changes after this commit.
2022-04-04 22:48:19 +08:00
|
|
|
return handle_atomic_sequence (curr_insn, dis.disasm_info ());
|
gdb: Do not interrupt atomic sequences for ARC
When stepping over thread-lock related codes (in uClibc), the inferior process
gets stuck and never manages to enter the critical section:
------8<-------
1 size_t fwrite(const void * __restrict ptr, size_t size,
2 size_t nmemb, register FILE * __restrict stream)
3 {
4 size_t retval;
5 __STDIO_AUTO_THREADLOCK_VAR;
6
7 > __STDIO_AUTO_THREADLOCK(stream);
8
9 retval = fwrite_unlocked(ptr, size, nmemb, stream);
10
11 __STDIO_AUTO_THREADUNLOCK(stream);
12
13 return retval;
14 }
------>8-------
Here, we are at line 7. Using the "next" command leads no where.
However, setting a breakpoint on line 9 and issuing "continue" works.
Looking at the assembly instructions reveals that we're dealing with the
critical section entry code [1] that should never be interrupted, in this
case by the debugger's implicit breakpoints:
------8<-------
...
1 add_s r0,r13,0x38
2 mov_s r3,1
3 llock r2,[r0] <-.
4 brne.nt r2,0,14 --. |
5 scond r3,[r0] | |
6 bne -10 --|--'
7 brne_s r2,0,84 <-'
...
------>8-------
Lines 3 until 5 (inclusive) are supposed to be executed atomically.
Therefore, GDB should never (implicitly) insert a breakpoint on lines
4 and 5, else the program will try to acquire the lock again by jumping
back to line 3 and gets stuck in an infinite loop.
The solution is to make GDB aware of these patterns so it inserts
breakpoints after the sequence -- line 6 in this example.
[1]
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/tree/libc/sysdeps/linux/arc/bits/atomic.h#n46
------8<-------
({ \
__typeof(oldval) prev; \
\
__asm__ __volatile__( \
"1: llock %0, [%1] \n" \
" brne %0, %2, 2f \n" \
" scond %3, [%1] \n" \
" bnz 1b \n" \
"2: \n" \
: "=&r"(prev) \
: "r"(mem), "ir"(oldval), \
"r"(newval) /* can't be "ir". scond can't take limm for "b" */\
: "cc", "memory"); \
\
prev; \
})
------>8-------
"llock" (Load Locked) loads the 32-bit word pointed by the source
operand. If the load is completed without any interruption or
exception, the physical address is remembered, in Lock Physical Address
(LPA), and the Lock Flag (LF) is set to 1. LF is a non-architecturally
visible flag and is cleared whenever an interrupt or exception takes
place. LF is also cleared (atomically) whenever another process writes
to the LPA.
"scond" (Store Conditional) will write to the destination address if
and only if the LF is set to 1. When finished, with or without a write,
it atomically copies the LF value to ZF (Zero Flag).
These two instructions together provide the mechanism for entering a
critical section. The code snippet above comes from uClibc:
-----------------------
v3 (after Tom's remarks[2]):
handle_atomic_sequence()
- no need to initialize the std::vector with "{}"
- fix typo in comments: "conditial" -> "conditional"
- add braces to the body of "if" condition because of the comment line
arc_linux_software_single_step()
- make the performance slightly more efficient by moving a few
variables after the likely "return" point.
v2 (after Simon's remarks[3]):
- handle_atomic_sequence() gets a copy of an instruction instead of
a reference.
- handle_atomic_sequence() asserts if the given instruction is an llock.
[2]
https://sourceware.org/pipermail/gdb-patches/2021-February/175805.html
[3]
https://sourceware.org/pipermail/gdb-patches/2021-January/175487.html
gdb/ChangeLog:
PR tdep/27369
* arc-linux-tdep.c (handle_atomic_sequence): New.
(arc_linux_software_single_step): Call handle_atomic_sequence().
2019-11-01 00:33:08 +08:00
|
|
|
|
|
|
|
CORE_ADDR next_pc = arc_insn_get_linear_next_pc (curr_insn);
|
2016-07-07 01:36:49 +08:00
|
|
|
std::vector<CORE_ADDR> next_pcs;
|
|
|
|
|
|
|
|
/* For instructions with delay slots, the fall thru is not the
|
|
|
|
instruction immediately after the current instruction, but the one
|
|
|
|
after that. */
|
|
|
|
if (curr_insn.has_delay_slot)
|
|
|
|
{
|
|
|
|
struct arc_instruction next_insn;
|
gdb: refactor the non-printing disassemblers
This commit started from an observation I made while working on some
other disassembler patches, that is, that the function
gdb_buffered_insn_length, is broken ... sort of.
I noticed that the gdb_buffered_insn_length function doesn't set up
the application data field if the disassemble_info structure.
Further, I noticed that some architectures, for example, ARM, require
that the application_data field be set, see gdb_print_insn_arm in
arm-tdep.c.
And so, if we ever use gdb_buffered_insn_length for ARM, then GDB will
likely crash. Which is why I said only "sort of" broken. Right now
we don't use gdb_buffered_insn_length with ARM, so maybe it isn't
broken yet?
Anyway to prove to myself that there was a problem here I extended the
disassembler self tests in disasm-selftests.c to include a test of
gdb_buffered_insn_length. As I run the test for all architectures, I
do indeed see GDB crash for ARM.
To fix this we need gdb_buffered_insn_length to create a disassembler
that inherits from gdb_disassemble_info, but we also need this new
disassembler to not print anything.
And so, I introduce a new gdb_non_printing_disassembler class, this is
a disassembler that doesn't print anything to the output stream.
I then observed that both ARC and S12Z also create non-printing
disassemblers, but these are slightly different. While the
disassembler in gdb_non_printing_disassembler reads the instruction
from a buffer, the ARC and S12Z disassemblers read from target memory
using target_read_code.
And so, I further split gdb_non_printing_disassembler into two
sub-classes, gdb_non_printing_memory_disassembler and
gdb_non_printing_buffer_disassembler.
The new selftests now pass, but otherwise, there should be no user
visible changes after this commit.
2022-04-04 22:48:19 +08:00
|
|
|
arc_insn_decode (next_pc, dis.disasm_info (), arc_delayed_print_insn,
|
|
|
|
&next_insn);
|
2016-07-07 01:36:49 +08:00
|
|
|
next_pcs.push_back (arc_insn_get_linear_next_pc (next_insn));
|
|
|
|
}
|
|
|
|
else
|
|
|
|
next_pcs.push_back (next_pc);
|
|
|
|
|
|
|
|
ULONGEST status32;
|
|
|
|
regcache_cooked_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch),
|
|
|
|
&status32);
|
|
|
|
|
|
|
|
if (curr_insn.is_control_flow)
|
|
|
|
{
|
|
|
|
CORE_ADDR branch_pc = arc_insn_get_branch_target (curr_insn);
|
|
|
|
if (branch_pc != next_pc)
|
|
|
|
next_pcs.push_back (branch_pc);
|
|
|
|
}
|
|
|
|
/* Is current instruction the last in a loop body? */
|
|
|
|
else if (tdep->has_hw_loops)
|
|
|
|
{
|
|
|
|
/* If STATUS32.L is 1, then ZD-loops are disabled. */
|
|
|
|
if ((status32 & ARC_STATUS32_L_MASK) == 0)
|
|
|
|
{
|
|
|
|
ULONGEST lp_end, lp_start, lp_count;
|
|
|
|
regcache_cooked_read_unsigned (regcache, ARC_LP_START_REGNUM,
|
|
|
|
&lp_start);
|
|
|
|
regcache_cooked_read_unsigned (regcache, ARC_LP_END_REGNUM, &lp_end);
|
|
|
|
regcache_cooked_read_unsigned (regcache, ARC_LP_COUNT_REGNUM,
|
|
|
|
&lp_count);
|
|
|
|
|
2021-01-14 03:32:39 +08:00
|
|
|
arc_linux_debug_printf ("lp_start = %s, lp_end = %s, "
|
|
|
|
"lp_count = %s, next_pc = %s",
|
|
|
|
paddress (gdbarch, lp_start),
|
|
|
|
paddress (gdbarch, lp_end),
|
|
|
|
pulongest (lp_count),
|
|
|
|
paddress (gdbarch, next_pc));
|
2016-07-07 01:36:49 +08:00
|
|
|
|
|
|
|
if (next_pc == lp_end && lp_count > 1)
|
|
|
|
{
|
|
|
|
/* The instruction is in effect a jump back to the start of
|
|
|
|
the loop. */
|
|
|
|
next_pcs.push_back (lp_start);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Is this a delay slot? Then next PC is in BTA register. */
|
|
|
|
if ((status32 & ARC_STATUS32_DE_MASK) != 0)
|
|
|
|
{
|
|
|
|
ULONGEST bta;
|
|
|
|
regcache_cooked_read_unsigned (regcache, ARC_BTA_REGNUM, &bta);
|
|
|
|
next_pcs.push_back (bta);
|
|
|
|
}
|
|
|
|
|
|
|
|
return next_pcs;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Implement the "skip_solib_resolver" gdbarch method.
|
|
|
|
|
|
|
|
See glibc_skip_solib_resolver for details. */
|
|
|
|
|
|
|
|
static CORE_ADDR
|
|
|
|
arc_linux_skip_solib_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
|
|
|
|
{
|
|
|
|
/* For uClibc 0.9.26+.
|
|
|
|
|
|
|
|
An unresolved PLT entry points to "__dl_linux_resolve", which calls
|
|
|
|
"_dl_linux_resolver" to do the resolving and then eventually jumps to
|
|
|
|
the function.
|
|
|
|
|
|
|
|
So we look for the symbol `_dl_linux_resolver', and if we are there,
|
|
|
|
gdb sets a breakpoint at the return address, and continues. */
|
|
|
|
struct bound_minimal_symbol resolver
|
|
|
|
= lookup_minimal_symbol ("_dl_linux_resolver", NULL, NULL);
|
|
|
|
|
|
|
|
if (arc_debug)
|
|
|
|
{
|
|
|
|
if (resolver.minsym != nullptr)
|
|
|
|
{
|
2022-01-28 21:09:50 +08:00
|
|
|
CORE_ADDR res_addr = resolver.value_address ();
|
2021-01-14 03:32:39 +08:00
|
|
|
arc_linux_debug_printf ("pc = %s, resolver at %s",
|
|
|
|
print_core_address (gdbarch, pc),
|
|
|
|
print_core_address (gdbarch, res_addr));
|
2016-07-07 01:36:49 +08:00
|
|
|
}
|
|
|
|
else
|
2021-01-14 03:32:39 +08:00
|
|
|
arc_linux_debug_printf ("pc = %s, no resolver found",
|
|
|
|
print_core_address (gdbarch, pc));
|
2016-07-07 01:36:49 +08:00
|
|
|
}
|
|
|
|
|
2022-01-28 21:09:50 +08:00
|
|
|
if (resolver.minsym != nullptr && resolver.value_address () == pc)
|
2016-07-07 01:36:49 +08:00
|
|
|
{
|
|
|
|
/* Find the return address. */
|
|
|
|
return frame_unwind_caller_pc (get_current_frame ());
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* No breakpoint required. */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-11-11 02:34:57 +08:00
|
|
|
/* Populate REGCACHE with register REGNUM from BUF. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
supply_register (struct regcache *regcache, int regnum, const gdb_byte *buf)
|
|
|
|
{
|
|
|
|
/* Skip non-existing registers. */
|
|
|
|
if ((arc_linux_core_reg_offsets[regnum] == ARC_OFFSET_NO_REGISTER))
|
|
|
|
return;
|
|
|
|
|
|
|
|
regcache->raw_supply (regnum, buf + arc_linux_core_reg_offsets[regnum]);
|
|
|
|
}
|
|
|
|
|
2017-01-30 23:32:10 +08:00
|
|
|
void
|
|
|
|
arc_linux_supply_gregset (const struct regset *regset,
|
|
|
|
struct regcache *regcache,
|
|
|
|
int regnum, const void *gregs, size_t size)
|
|
|
|
{
|
2023-10-19 10:44:11 +08:00
|
|
|
static_assert (ARC_LAST_REGNUM
|
2017-01-30 23:32:10 +08:00
|
|
|
< ARRAY_SIZE (arc_linux_core_reg_offsets));
|
|
|
|
|
|
|
|
const bfd_byte *buf = (const bfd_byte *) gregs;
|
|
|
|
|
2020-12-22 19:27:00 +08:00
|
|
|
/* REGNUM == -1 means writing all the registers. */
|
2020-11-11 02:34:57 +08:00
|
|
|
if (regnum == -1)
|
|
|
|
for (int reg = 0; reg <= ARC_LAST_REGNUM; reg++)
|
|
|
|
supply_register (regcache, reg, buf);
|
|
|
|
else if (regnum <= ARC_LAST_REGNUM)
|
|
|
|
supply_register (regcache, regnum, buf);
|
|
|
|
else
|
|
|
|
gdb_assert_not_reached ("Invalid regnum in arc_linux_supply_gregset.");
|
2017-01-30 23:32:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
arc_linux_supply_v2_regset (const struct regset *regset,
|
|
|
|
struct regcache *regcache, int regnum,
|
|
|
|
const void *v2_regs, size_t size)
|
|
|
|
{
|
|
|
|
const bfd_byte *buf = (const bfd_byte *) v2_regs;
|
|
|
|
|
|
|
|
/* user_regs_arcv2 is defined in linux arch/arc/include/uapi/asm/ptrace.h. */
|
2020-11-11 02:34:57 +08:00
|
|
|
if (regnum == -1 || regnum == ARC_R30_REGNUM)
|
|
|
|
regcache->raw_supply (ARC_R30_REGNUM, buf);
|
|
|
|
if (regnum == -1 || regnum == ARC_R58_REGNUM)
|
|
|
|
regcache->raw_supply (ARC_R58_REGNUM, buf + REGOFF (1));
|
|
|
|
if (regnum == -1 || regnum == ARC_R59_REGNUM)
|
|
|
|
regcache->raw_supply (ARC_R59_REGNUM, buf + REGOFF (2));
|
2017-01-30 23:32:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Populate BUF with register REGNUM from the REGCACHE. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
collect_register (const struct regcache *regcache, struct gdbarch *gdbarch,
|
|
|
|
int regnum, gdb_byte *buf)
|
|
|
|
{
|
2020-11-12 19:50:33 +08:00
|
|
|
int offset;
|
|
|
|
|
2017-01-30 23:32:10 +08:00
|
|
|
/* Skip non-existing registers. */
|
2020-11-12 19:50:33 +08:00
|
|
|
if (arc_linux_core_reg_offsets[regnum] == ARC_OFFSET_NO_REGISTER)
|
2017-01-30 23:32:10 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* The address where the execution has stopped is in pseudo-register
|
|
|
|
STOP_PC. However, when kernel code is returning from the exception,
|
|
|
|
it uses the value from ERET register. Since, TRAP_S (the breakpoint
|
|
|
|
instruction) commits, the ERET points to the next instruction. In
|
|
|
|
other words: ERET != STOP_PC. To jump back from the kernel code to
|
|
|
|
the correct address, ERET must be overwritten by GDB's STOP_PC. Else,
|
|
|
|
the program will continue at the address after the current instruction.
|
|
|
|
*/
|
|
|
|
if (regnum == gdbarch_pc_regnum (gdbarch))
|
2020-11-12 19:50:33 +08:00
|
|
|
offset = arc_linux_core_reg_offsets[ARC_ERET_REGNUM];
|
|
|
|
else
|
|
|
|
offset = arc_linux_core_reg_offsets[regnum];
|
|
|
|
regcache->raw_collect (regnum, buf + offset);
|
2017-01-30 23:32:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
arc_linux_collect_gregset (const struct regset *regset,
|
|
|
|
const struct regcache *regcache,
|
|
|
|
int regnum, void *gregs, size_t size)
|
|
|
|
{
|
2023-10-19 10:44:11 +08:00
|
|
|
static_assert (ARC_LAST_REGNUM
|
2017-01-30 23:32:10 +08:00
|
|
|
< ARRAY_SIZE (arc_linux_core_reg_offsets));
|
|
|
|
|
|
|
|
gdb_byte *buf = (gdb_byte *) gregs;
|
|
|
|
struct gdbarch *gdbarch = regcache->arch ();
|
|
|
|
|
2020-12-22 19:27:00 +08:00
|
|
|
/* REGNUM == -1 means writing all the registers. */
|
2017-01-30 23:32:10 +08:00
|
|
|
if (regnum == -1)
|
|
|
|
for (int reg = 0; reg <= ARC_LAST_REGNUM; reg++)
|
|
|
|
collect_register (regcache, gdbarch, reg, buf);
|
|
|
|
else if (regnum <= ARC_LAST_REGNUM)
|
|
|
|
collect_register (regcache, gdbarch, regnum, buf);
|
|
|
|
else
|
|
|
|
gdb_assert_not_reached ("Invalid regnum in arc_linux_collect_gregset.");
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
arc_linux_collect_v2_regset (const struct regset *regset,
|
|
|
|
const struct regcache *regcache, int regnum,
|
|
|
|
void *v2_regs, size_t size)
|
|
|
|
{
|
|
|
|
bfd_byte *buf = (bfd_byte *) v2_regs;
|
|
|
|
|
2020-11-11 02:34:57 +08:00
|
|
|
if (regnum == -1 || regnum == ARC_R30_REGNUM)
|
|
|
|
regcache->raw_collect (ARC_R30_REGNUM, buf);
|
|
|
|
if (regnum == -1 || regnum == ARC_R58_REGNUM)
|
|
|
|
regcache->raw_collect (ARC_R58_REGNUM, buf + REGOFF (1));
|
|
|
|
if (regnum == -1 || regnum == ARC_R59_REGNUM)
|
|
|
|
regcache->raw_collect (ARC_R59_REGNUM, buf + REGOFF (2));
|
2017-01-30 23:32:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Linux regset definitions. */
|
|
|
|
|
|
|
|
static const struct regset arc_linux_gregset = {
|
|
|
|
arc_linux_core_reg_offsets,
|
|
|
|
arc_linux_supply_gregset,
|
|
|
|
arc_linux_collect_gregset,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regset arc_linux_v2_regset = {
|
|
|
|
NULL,
|
|
|
|
arc_linux_supply_v2_regset,
|
|
|
|
arc_linux_collect_v2_regset,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Implement the `iterate_over_regset_sections` gdbarch method. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
arc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
|
|
|
|
iterate_over_regset_sections_cb *cb,
|
|
|
|
void *cb_data,
|
|
|
|
const struct regcache *regcache)
|
|
|
|
{
|
|
|
|
/* There are 40 registers in Linux user_regs_struct, although some of
|
|
|
|
them are now just a mere paddings, kept to maintain binary
|
|
|
|
compatibility with older tools. */
|
|
|
|
const int sizeof_gregset = 40 * ARC_REGISTER_SIZE;
|
|
|
|
|
|
|
|
cb (".reg", sizeof_gregset, sizeof_gregset, &arc_linux_gregset, NULL,
|
|
|
|
cb_data);
|
|
|
|
cb (".reg-arc-v2", ARC_LINUX_SIZEOF_V2_REGSET, ARC_LINUX_SIZEOF_V2_REGSET,
|
|
|
|
&arc_linux_v2_regset, NULL, cb_data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Implement the `core_read_description` gdbarch method. */
|
|
|
|
|
|
|
|
static const struct target_desc *
|
|
|
|
arc_linux_core_read_description (struct gdbarch *gdbarch,
|
|
|
|
struct target_ops *target,
|
|
|
|
bfd *abfd)
|
|
|
|
{
|
|
|
|
arc_arch_features features
|
|
|
|
= arc_arch_features_create (abfd,
|
|
|
|
gdbarch_bfd_arch_info (gdbarch)->mach);
|
|
|
|
return arc_lookup_target_description (features);
|
|
|
|
}
|
|
|
|
|
2016-07-07 01:36:49 +08:00
|
|
|
/* Initialization specific to Linux environment. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
arc_linux_init_osabi (struct gdbarch_info info, struct gdbarch *gdbarch)
|
|
|
|
{
|
gdb: move the type cast into gdbarch_tdep
I built GDB for all targets on a x86-64/GNU-Linux system, and
then (accidentally) passed GDB a RISC-V binary, and asked GDB to "run"
the binary on the native target. I got this error:
(gdb) show architecture
The target architecture is set to "auto" (currently "i386").
(gdb) file /tmp/hello.rv32.exe
Reading symbols from /tmp/hello.rv32.exe...
(gdb) show architecture
The target architecture is set to "auto" (currently "riscv:rv32").
(gdb) run
Starting program: /tmp/hello.rv32.exe
../../src/gdb/i387-tdep.c:596: internal-error: i387_supply_fxsave: Assertion `tdep->st0_regnum >= I386_ST0_REGNUM' failed.
What's going on here is this; initially the architecture is i386, this
is based on the default architecture, which is set based on the native
target. After loading the RISC-V executable the architecture of the
current inferior is updated based on the architecture of the
executable.
When we "run", GDB does a fork & exec, with the inferior being
controlled through ptrace. GDB sees an initial stop from the inferior
as soon as the inferior comes to life. In response to this stop GDB
ends up calling save_stop_reason (linux-nat.c), which ends up trying
to read register from the inferior, to do this we end up calling
target_ops::fetch_registers, which, for the x86-64 native target,
calls amd64_linux_nat_target::fetch_registers.
After this I eventually end up in i387_supply_fxsave, different x86
based targets will end in different functions to fetch registers, but
it doesn't really matter which function we end up in, the problem is
this line, which is repeated in many places:
i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
The problem here is that the ARCH in this line comes from the current
inferior, which, as we discussed above, will be a RISC-V gdbarch, the
tdep field will actually be of type riscv_gdbarch_tdep, not
i386_gdbarch_tdep. After this cast we are relying on undefined
behaviour, in my case I happen to trigger an assert, but this might
not always be the case.
The thing I tried that exposed this problem was of course, trying to
start an executable of the wrong architecture on a native target. I
don't think that the correct solution for this problem is to detect,
at the point of cast, that the gdbarch_tdep object is of the wrong
type, but, I did wonder, is there a way that we could protect
ourselves from incorrectly casting the gdbarch_tdep object?
I think that there is something we can do here, and this commit is the
first step in that direction, though no actual check is added by this
commit.
This commit can be split into two parts:
(1) In gdbarch.h and arch-utils.c. In these files I have modified
gdbarch_tdep (the function) so that it now takes a template argument,
like this:
template<typename TDepType>
static inline TDepType *
gdbarch_tdep (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep_1 (gdbarch);
return static_cast<TDepType *> (tdep);
}
After this change we are no better protected, but the cast is now
done within the gdbarch_tdep function rather than at the call sites,
this leads to the second, much larger change in this commit,
(2) Everywhere gdbarch_tdep is called, we make changes like this:
- i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch);
+ i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
There should be no functional change after this commit.
In the next commit I will build on this change to add an assertion in
gdbarch_tdep that checks we are casting to the correct type.
2022-05-19 20:20:17 +08:00
|
|
|
arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (gdbarch);
|
2016-07-07 01:36:49 +08:00
|
|
|
|
2021-01-14 03:32:39 +08:00
|
|
|
arc_linux_debug_printf ("GNU/Linux OS/ABI initialization.");
|
2016-07-07 01:36:49 +08:00
|
|
|
|
2016-12-23 02:52:16 +08:00
|
|
|
/* Fill in target-dependent info in ARC-private structure. */
|
|
|
|
tdep->is_sigtramp = arc_linux_is_sigtramp;
|
|
|
|
tdep->sigcontext_addr = arc_linux_sigcontext_addr;
|
|
|
|
tdep->sc_reg_offset = arc_linux_sc_reg_offsets;
|
|
|
|
tdep->sc_num_regs = ARRAY_SIZE (arc_linux_sc_reg_offsets);
|
|
|
|
|
2016-07-07 01:36:49 +08:00
|
|
|
/* If we are using Linux, we have in uClibc
|
|
|
|
(libc/sysdeps/linux/arc/bits/setjmp.h):
|
|
|
|
|
|
|
|
typedef int __jmp_buf[13+1+1+1]; //r13-r25, fp, sp, blink
|
|
|
|
|
|
|
|
Where "blink" is a stored PC of a caller function.
|
|
|
|
*/
|
|
|
|
tdep->jb_pc = 15;
|
|
|
|
|
gdb: make displaced stepping implementation capable of managing multiple buffers
The displaced_step_buffer class, introduced in the previous patch,
manages access to a single displaced step buffer. Change it into
displaced_step_buffers (note the plural), which manages access to
multiple displaced step buffers.
When preparing a displaced step for a thread, it looks for an unused
buffer.
For now, all users still pass a single displaced step buffer, so no real
behavior change is expected here. The following patch makes a user pass
more than one buffer, so the functionality introduced by this patch is
going to be useful in the next one.
gdb/ChangeLog:
* displaced-stepping.h (struct displaced_step_buffer): Rename
to...
(struct displaced_step_buffers): ... this.
<m_addr, m_current_thread, m_copy_insn_closure>: Remove.
<struct displaced_step_buffer>: New inner class.
<m_buffers>: New.
* displaced-stepping.c (displaced_step_buffer::prepare): Rename
to...
(displaced_step_buffers::prepare): ... this, adjust for multiple
buffers.
(displaced_step_buffer::finish): Rename to...
(displaced_step_buffers::finish): ... this, adjust for multiple
buffers.
(displaced_step_buffer::copy_insn_closure_by_addr): Rename to...
(displaced_step_buffers::copy_insn_closure_by_addr): ... this,
adjust for multiple buffers.
(displaced_step_buffer::restore_in_ptid): Rename to...
(displaced_step_buffers::restore_in_ptid): ... this, adjust for
multiple buffers.
* linux-tdep.h (linux_init_abi): Change supports_displaced_step
for num_disp_step_buffers.
* linux-tdep.c (struct linux_gdbarch_data)
<num_disp_step_buffers>: New field.
(struct linux_info) <disp_step_buf>: Rename to...
<disp_step_bufs>: ... this, change type to
displaced_step_buffers.
(linux_displaced_step_prepare): Use
linux_gdbarch_data::num_disp_step_buffers to create that number
of buffers.
(linux_displaced_step_finish): Adjust.
(linux_displaced_step_copy_insn_closure_by_addr): Adjust.
(linux_displaced_step_restore_all_in_ptid): Adjust.
(linux_init_abi): Change supports_displaced_step parameter for
num_disp_step_buffers, save it in linux_gdbarch_data.
* aarch64-linux-tdep.c (aarch64_linux_init_abi): Adjust.
* alpha-linux-tdep.c (alpha_linux_init_abi): Adjust.
* amd64-linux-tdep.c (amd64_linux_init_abi_common): Change
supports_displaced_step parameter for num_disp_step_buffers.
(amd64_linux_init_abi): Adjust.
(amd64_x32_linux_init_abi): Adjust.
* arc-linux-tdep.c (arc_linux_init_osabi): Adjust.
* arm-linux-tdep.c (arm_linux_init_abi): Adjust.
* bfin-linux-tdep.c (bfin_linux_init_abi): Adjust.
* cris-linux-tdep.c (cris_linux_init_abi): Adjust.
* csky-linux-tdep.c (csky_linux_init_abi): Adjust.
* frv-linux-tdep.c (frv_linux_init_abi): Adjust.
* hppa-linux-tdep.c (hppa_linux_init_abi): Adjust.
* i386-linux-tdep.c (i386_linux_init_abi): Adjust.
* ia64-linux-tdep.c (ia64_linux_init_abi): Adjust.
* m32r-linux-tdep.c (m32r_linux_init_abi): Adjust.
* m68k-linux-tdep.c (m68k_linux_init_abi):
* microblaze-linux-tdep.c (microblaze_linux_init_abi):
* mips-linux-tdep.c (mips_linux_init_abi): Adjust.
* mn10300-linux-tdep.c (am33_linux_init_osabi): Adjust.
* nios2-linux-tdep.c (nios2_linux_init_abi): Adjust.
* or1k-linux-tdep.c (or1k_linux_init_abi): Adjust.
* ppc-linux-tdep.c (ppc_linux_init_abi): Adjust.
* riscv-linux-tdep.c (riscv_linux_init_abi): Adjust.
* rs6000-tdep.c (struct ppc_inferior_data) <disp_step_buf>:
Change type to displaced_step_buffers.
* s390-linux-tdep.c (s390_linux_init_abi_any): Adjust.
* sh-linux-tdep.c (sh_linux_init_abi): Adjust.
* sparc-linux-tdep.c (sparc32_linux_init_abi): Adjust.
* sparc64-linux-tdep.c (sparc64_linux_init_abi): Adjust.
* tic6x-linux-tdep.c (tic6x_uclinux_init_abi): Adjust.
* tilegx-linux-tdep.c (tilegx_linux_init_abi): Adjust.
* xtensa-linux-tdep.c (xtensa_linux_init_abi): Adjust.
Change-Id: Ia9c02f207da2c9e1d9188020139619122392bb70
2020-12-05 05:43:56 +08:00
|
|
|
linux_init_abi (info, gdbarch, 0);
|
2016-07-07 01:36:49 +08:00
|
|
|
|
|
|
|
/* Set up target dependent GDB architecture entries. */
|
|
|
|
set_gdbarch_cannot_fetch_register (gdbarch, arc_linux_cannot_fetch_register);
|
|
|
|
set_gdbarch_cannot_store_register (gdbarch, arc_linux_cannot_store_register);
|
|
|
|
set_gdbarch_breakpoint_kind_from_pc (gdbarch,
|
|
|
|
arc_linux_breakpoint_kind_from_pc);
|
|
|
|
set_gdbarch_sw_breakpoint_from_kind (gdbarch,
|
|
|
|
arc_linux_sw_breakpoint_from_kind);
|
|
|
|
set_gdbarch_fetch_tls_load_module_address (gdbarch,
|
|
|
|
svr4_fetch_objfile_link_map);
|
|
|
|
set_gdbarch_software_single_step (gdbarch, arc_linux_software_single_step);
|
|
|
|
set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
|
|
|
|
set_gdbarch_skip_solib_resolver (gdbarch, arc_linux_skip_solib_resolver);
|
2017-01-30 23:32:10 +08:00
|
|
|
set_gdbarch_iterate_over_regset_sections
|
|
|
|
(gdbarch, arc_linux_iterate_over_regset_sections);
|
|
|
|
set_gdbarch_core_read_description (gdbarch, arc_linux_core_read_description);
|
2016-07-07 01:36:49 +08:00
|
|
|
|
|
|
|
/* GNU/Linux uses SVR4-style shared libraries, with 32-bit ints, longs
|
|
|
|
and pointers (ILP32). */
|
|
|
|
set_solib_svr4_fetch_link_map_offsets (gdbarch,
|
2021-08-17 07:17:25 +08:00
|
|
|
linux_ilp32_fetch_link_map_offsets);
|
2016-07-07 01:36:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Suppress warning from -Wmissing-prototypes. */
|
|
|
|
extern initialize_file_ftype _initialize_arc_linux_tdep;
|
|
|
|
|
|
|
|
void
|
|
|
|
_initialize_arc_linux_tdep ()
|
|
|
|
{
|
|
|
|
gdbarch_register_osabi (bfd_arch_arc, 0, GDB_OSABI_LINUX,
|
|
|
|
arc_linux_init_osabi);
|
|
|
|
}
|