mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-24 12:35:55 +08:00
438 lines
9.5 KiB
ArmAsm
438 lines
9.5 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp
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// Spec Reference: dsp32shift rot
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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imm32 r0, 0x01230000;
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imm32 r1, 0x12345678;
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imm32 r2, 0x83456789;
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imm32 r3, 0x9456789a;
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imm32 r4, 0xa56789ab;
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imm32 r5, 0xb6789abc;
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imm32 r6, 0xc789abcd;
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imm32 r7, 0xd89abcde;
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R1 = ROT R0 BY R0.L;
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R2 = ROT R1 BY R0.L;
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R3 = ROT R2 BY R0.L;
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R4 = ROT R3 BY R0.L;
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R5 = ROT R4 BY R0.L;
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R6 = ROT R5 BY R0.L;
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R7 = ROT R6 BY R0.L;
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R0 = ROT R7 BY R0.L;
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CHECKREG r0, 0x01230000;
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CHECKREG r1, 0x01230000;
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CHECKREG r2, 0x01230000;
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CHECKREG r3, 0x01230000;
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CHECKREG r4, 0x01230000;
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CHECKREG r5, 0x01230000;
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CHECKREG r6, 0x01230000;
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CHECKREG r7, 0x01230000;
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A0 = 0;
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A0.L = R0.L;
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A0.H = R0.H;
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A0 = ROT A0 BY R1.L;
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R6 = A0.w;
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imm32 r4, 0x30003000;
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imm32 r1, 5;
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R7 = ROT R4 BY R1.L;
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CHECKREG r6, 0x01230000;
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CHECKREG r7, 0x00060003;
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imm32 r0, 0x11230001;
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imm32 r1, 0xc2345678;
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imm32 r2, 0xd3456789;
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imm32 r3, 0xb456789a;
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imm32 r4, 0x056789ab;
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imm32 r5, 0x36789abc;
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imm32 r6, 0x1789abcd;
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imm32 r7, 0x189abcde;
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R1.L = 5;
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R2 = ROT R0 BY R1.L;
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R3 = ROT R1 BY R1.L;
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R4 = ROT R2 BY R1.L;
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R5 = ROT R3 BY R1.L;
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R6 = ROT R4 BY R1.L;
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R7 = ROT R5 BY R1.L;
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R0 = ROT R6 BY R1.L;
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R1 = ROT R7 BY R1.L;
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CHECKREG r0, 0x00108908;
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CHECKREG r1, 0x005613A0;
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CHECKREG r2, 0x24600021;
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CHECKREG r3, 0x468000AC;
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CHECKREG r4, 0x8C000422;
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CHECKREG r5, 0xD0001584;
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CHECKREG r6, 0x80008448;
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CHECKREG r7, 0x0002B09D;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x8456789a;
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imm32 r4, 0x956789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0xc789abcd;
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imm32 r7, 0x789abcde;
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R2 = 15;
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R3 = ROT R0 BY R2.L;
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R4 = ROT R1 BY R2.L;
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R5 = ROT R2 BY R2.L;
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R6 = ROT R3 BY R2.L;
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R7 = ROT R4 BY R2.L;
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R0 = ROT R5 BY R2.L;
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R1 = ROT R6 BY R2.L;
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R2 = ROT R7 BY R2.L;
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CHECKREG r0, 0xC0000001;
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CHECKREG r1, 0x10006009;
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CHECKREG r2, 0x45678891;
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CHECKREG r3, 0x80010048;
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CHECKREG r4, 0x2B3C448D;
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CHECKREG r5, 0x00078000;
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CHECKREG r6, 0x80242000;
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CHECKREG r7, 0x22468ACF;
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imm32 r0, 0x21230003;
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imm32 r1, 0x22345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x2456789a;
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imm32 r4, 0x256789ab;
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imm32 r5, 0x26789abc;
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imm32 r6, 0x2789abcd;
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imm32 r7, 0x289abcde;
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R3.L = 24;
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R4 = ROT R0 BY R3.L;
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R5 = ROT R1 BY R3.L;
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R6 = ROT R2 BY R3.L;
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R7 = ROT R3 BY R3.L;
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R0 = ROT R4 BY R3.L;
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R1 = ROT R5 BY R3.L;
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R2 = ROT R6 BY R3.L;
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R3 = ROT R7 BY R3.L;
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CHECKREG r0, 0x8001C848;
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CHECKREG r1, 0x2BBC088D;
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CHECKREG r2, 0xB34488D1;
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CHECKREG r3, 0x000C4915;
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CHECKREG r4, 0x03909180;
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CHECKREG r5, 0x78111A2B;
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CHECKREG r6, 0x8911A2B3;
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CHECKREG r7, 0x18922B00;
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imm32 r0, 0x01230004;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R4.L = -1;
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R0 = ROT R0 BY R4.L;
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R1 = ROT R1 BY R4.L;
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R2 = ROT R2 BY R4.L;
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R3 = ROT R3 BY R4.L;
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R4 = ROT R4 BY R4.L;
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R5 = ROT R5 BY R4.L;
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R6 = ROT R6 BY R4.L;
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R7 = ROT R7 BY R4.L;
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CHECKREG r0, 0x80918002;
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CHECKREG r1, 0x091A2B3C;
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CHECKREG r2, 0x11A2B3C4;
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CHECKREG r3, 0x9A2B3C4D;
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CHECKREG r4, 0x22B3FFFF;
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CHECKREG r5, 0xAB3C4D5E;
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CHECKREG r6, 0x33C4D5E6;
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CHECKREG r7, 0xBC4D5E6F;
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imm32 r0, 0x01230005;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R5.L = -6;
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R6 = ROT R0 BY R5.L;
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R7 = ROT R1 BY R5.L;
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R0 = ROT R2 BY R5.L;
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R1 = ROT R3 BY R5.L;
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R2 = ROT R4 BY R5.L;
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R3 = ROT R5 BY R5.L;
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R4 = ROT R6 BY R5.L;
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R5 = ROT R7 BY R5.L;
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CHECKREG r0, 0x4C8D159E;
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CHECKREG r1, 0xD0D159E2;
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CHECKREG r2, 0x59159E26;
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CHECKREG r3, 0xD559E3FF;
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CHECKREG r4, 0x04A01230;
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CHECKREG r5, 0xCB012345;
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CHECKREG r6, 0x28048C00;
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CHECKREG r7, 0xC048D159;
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imm32 r0, 0x01230006;
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imm32 r1, 0x82345678;
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imm32 r2, 0x73456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0xd56789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0xc789abcd;
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imm32 r7, 0x789abcde;
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R6.L = -15;
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R7 = ROT R0 BY R6.L;
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R0 = ROT R1 BY R6.L;
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R1 = ROT R2 BY R6.L;
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R2 = ROT R3 BY R6.L;
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R3 = ROT R4 BY R6.L;
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R4 = ROT R5 BY R6.L;
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R5 = ROT R6 BY R6.L;
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R6 = ROT R7 BY R6.L;
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CHECKREG r0, 0x59E10468;
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CHECKREG r1, 0x9E26E68A;
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CHECKREG r2, 0xE26A68AC;
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CHECKREG r3, 0x26AFAACF;
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CHECKREG r4, 0x6AF0ACF1;
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CHECKREG r5, 0xFFC58F13;
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CHECKREG r6, 0x091A0030;
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CHECKREG r7, 0x00180246;
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imm32 r0, 0x01230007;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R7.L = -27;
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R0 = ROT R0 BY R7.L;
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R1 = ROT R1 BY R7.L;
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R2 = ROT R2 BY R7.L;
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R3 = ROT R3 BY R7.L;
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R4 = ROT R4 BY R7.L;
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R5 = ROT R5 BY R7.L;
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R6 = ROT R6 BY R7.L;
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R7 = ROT R7 BY R7.L;
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CHECKREG r0, 0x48C001C0;
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CHECKREG r1, 0x8D159E02;
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CHECKREG r2, 0xD159E244;
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CHECKREG r3, 0x159E2686;
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CHECKREG r4, 0x59E26AE8;
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CHECKREG r5, 0x9E26AF2A;
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CHECKREG r6, 0xE26AF36C;
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CHECKREG r7, 0x26BFF96F;
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imm32 r0, 0x01230008;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R0.L = 7;
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//r0 = rot (r0 by rl0);
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R1 = ROT R1 BY R0.L;
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R2 = ROT R2 BY R0.L;
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R3 = ROT R3 BY R0.L;
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R4 = ROT R4 BY R0.L;
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R5 = ROT R5 BY R0.L;
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R6 = ROT R6 BY R0.L;
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R7 = ROT R7 BY R0.L;
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CHECKREG r0, 0x01230007;
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CHECKREG r1, 0x1A2B3C04;
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CHECKREG r2, 0xA2B3C4C8;
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CHECKREG r3, 0x2B3C4D4D;
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CHECKREG r4, 0xB3C4D591;
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CHECKREG r5, 0x3C4D5E15;
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CHECKREG r6, 0xC4D5E6D9;
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CHECKREG r7, 0x4D5E6F5E;
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imm32 r0, 0x01230009;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R1.L = 16;
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R0 = ROT R0 BY R1.L;
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//r1 = rot (r1 by rl1);
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R2 = ROT R2 BY R1.L;
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R3 = ROT R3 BY R1.L;
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R4 = ROT R4 BY R1.L;
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R5 = ROT R5 BY R1.L;
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R6 = ROT R6 BY R1.L;
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R7 = ROT R7 BY R1.L;
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CHECKREG r0, 0x00090091;
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CHECKREG r1, 0x12340010;
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CHECKREG r2, 0x678991A2;
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CHECKREG r3, 0x789A9A2B;
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CHECKREG r4, 0x89AB22B3;
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CHECKREG r5, 0x9ABCAB3C;
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CHECKREG r6, 0xABCD33C4;
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CHECKREG r7, 0xBCDEBC4D;
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imm32 r0, 0x0123000a;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R2.L = 31;
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R0 = ROT R0 BY R2.L;
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R1 = ROT R1 BY R2.L;
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//r2 = rot (r2 by rl2);
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R3 = ROT R3 BY R2.L;
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R4 = ROT R4 BY R2.L;
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R5 = ROT R5 BY R2.L;
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R6 = ROT R6 BY R2.L;
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R7 = ROT R7 BY R2.L;
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CHECKREG r0, 0x0048C002;
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CHECKREG r1, 0x448D159E;
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CHECKREG r2, 0x2345001F;
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CHECKREG r3, 0x0D159E26;
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CHECKREG r4, 0xD159E26A;
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CHECKREG r5, 0x559E26AF;
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CHECKREG r6, 0x99E26AF3;
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CHECKREG r7, 0x1E26AF37;
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imm32 r0, 0x0123000b;
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imm32 r1, 0x92345678;
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imm32 r2, 0x93456789;
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imm32 r3, 0xc456789a;
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imm32 r4, 0xa56789ab;
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imm32 r5, 0xb6789abc;
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imm32 r6, 0xe789abcd;
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imm32 r7, 0xf89abcde;
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R3.L = 33;
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R0 = ROT R0 BY R3.L;
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R1 = ROT R1 BY R3.L;
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R2 = ROT R2 BY R3.L;
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//r3 = rot (r3 by rl3);
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R4 = ROT R4 BY R3.L;
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R5 = ROT R5 BY R3.L;
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R6 = ROT R6 BY R3.L;
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|
R7 = ROT R7 BY R3.L;
|
||
|
|
CHECKREG r0, 0x048C002E;
|
||
|
|
CHECKREG r1, 0x48D159E1;
|
||
|
|
CHECKREG r2, 0x4D159E25;
|
||
|
|
CHECKREG r3, 0xC4560021;
|
||
|
|
CHECKREG r4, 0x959E26AD;
|
||
|
|
CHECKREG r5, 0xD9E26AF1;
|
||
|
|
CHECKREG r6, 0x9E26AF35;
|
||
|
|
CHECKREG r7, 0xE26AF37B;
|
||
|
|
|
||
|
|
imm32 r0, 0x0123000c;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R4.L = -2;
|
||
|
|
R0 = ROT R0 BY R4.L;
|
||
|
|
R1 = ROT R1 BY R4.L;
|
||
|
|
R2 = ROT R2 BY R4.L;
|
||
|
|
R3 = ROT R3 BY R4.L;
|
||
|
|
//r4 = rot (r4 by rl4);
|
||
|
|
R5 = ROT R5 BY R4.L;
|
||
|
|
R6 = ROT R6 BY R4.L;
|
||
|
|
R7 = ROT R7 BY R4.L;
|
||
|
|
CHECKREG r0, 0x4048C003;
|
||
|
|
CHECKREG r1, 0x048D159E;
|
||
|
|
CHECKREG r2, 0x88D159E2;
|
||
|
|
CHECKREG r3, 0x0D159E26;
|
||
|
|
CHECKREG r4, 0x4567FFFE;
|
||
|
|
CHECKREG r5, 0x559E26AF;
|
||
|
|
CHECKREG r6, 0x99E26AF3;
|
||
|
|
CHECKREG r7, 0x1E26AF37;
|
||
|
|
|
||
|
|
imm32 r0, 0x0123000d;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R5.L = -14;
|
||
|
|
R0 = ROT R0 BY R5.L;
|
||
|
|
R1 = ROT R1 BY R5.L;
|
||
|
|
R2 = ROT R2 BY R5.L;
|
||
|
|
R3 = ROT R3 BY R5.L;
|
||
|
|
R4 = ROT R4 BY R5.L;
|
||
|
|
//r5 = rot (r5 by rl5);
|
||
|
|
R6 = ROT R6 BY R5.L;
|
||
|
|
R7 = ROT R7 BY R5.L;
|
||
|
|
CHECKREG r0, 0x006C048C;
|
||
|
|
CHECKREG r1, 0xB3C048D1;
|
||
|
|
CHECKREG r2, 0x3C488D15;
|
||
|
|
CHECKREG r3, 0xC4D4D159;
|
||
|
|
CHECKREG r4, 0x4D5D159E;
|
||
|
|
CHECKREG r5, 0x5678FFF2;
|
||
|
|
CHECKREG r6, 0x5E699E26;
|
||
|
|
CHECKREG r7, 0xE6F5E26A;
|
||
|
|
|
||
|
|
imm32 r0, 0x0123000e;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R6.L = -16;
|
||
|
|
R0 = ROT R0 BY R6.L;
|
||
|
|
R1 = ROT R1 BY R6.L;
|
||
|
|
R2 = ROT R2 BY R6.L;
|
||
|
|
R3 = ROT R3 BY R6.L;
|
||
|
|
R4 = ROT R4 BY R6.L;
|
||
|
|
R5 = ROT R5 BY R6.L;
|
||
|
|
//r6 = rot (r6 by rl6);
|
||
|
|
R7 = ROT R7 BY R6.L;
|
||
|
|
CHECKREG r0, 0x001D0123;
|
||
|
|
CHECKREG r1, 0xACF01234;
|
||
|
|
CHECKREG r2, 0xCF122345;
|
||
|
|
CHECKREG r3, 0xF1343456;
|
||
|
|
CHECKREG r4, 0x13564567;
|
||
|
|
CHECKREG r5, 0x35795678;
|
||
|
|
CHECKREG r6, 0x6789FFF0;
|
||
|
|
CHECKREG r7, 0x79BD789A;
|
||
|
|
|
||
|
|
imm32 r0, 0x0123000f;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x83456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0xd56789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x9789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R7.L = -32;
|
||
|
|
R0 = ROT R0 BY R7.L;
|
||
|
|
R1 = ROT R1 BY R7.L;
|
||
|
|
R2 = ROT R2 BY R7.L;
|
||
|
|
R3 = ROT R3 BY R7.L;
|
||
|
|
R4 = ROT R4 BY R7.L;
|
||
|
|
R5 = ROT R5 BY R7.L;
|
||
|
|
R6 = ROT R6 BY R7.L;
|
||
|
|
R7 = ROT R7 BY R7.L;
|
||
|
|
CHECKREG r0, 0x0246001f;
|
||
|
|
CHECKREG r1, 0x2468ACF0;
|
||
|
|
CHECKREG r2, 0x068ACF12;
|
||
|
|
CHECKREG r3, 0x68ACF135;
|
||
|
|
CHECKREG r4, 0xAACF1356;
|
||
|
|
CHECKREG r5, 0xACF13579;
|
||
|
|
CHECKREG r6, 0x2F13579A;
|
||
|
|
CHECKREG r7, 0xF135FFC1;
|
||
|
|
pass
|