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64 lines
1.1 KiB
ArmAsm
64 lines
1.1 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp
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# mach: bfin
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.include "testutils.inc"
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start
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// Spec Reference: dsp32shiftimm ashift: ashift
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imm32 r0, 0xa1230001;
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imm32 r1, 0x1b345678;
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imm32 r2, 0x23c56789;
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imm32 r3, 0x34d6789a;
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imm32 r4, 0x85a789ab;
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imm32 r5, 0x967c9abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb8912cde;
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R0 = R0 << 0;
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R1 = R1 << 3;
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R2 = R2 << 7;
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R3 = R3 << 8;
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R4 = R4 << 15;
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R5 = R5 << 24;
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R6 = R6 << 31;
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R7 = R7 << 20;
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CHECKREG r0, 0xA1230001;
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CHECKREG r1, 0xD9A2B3C0;
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CHECKREG r2, 0xE2B3C480;
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CHECKREG r3, 0xD6789A00;
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CHECKREG r4, 0xC4D58000;
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CHECKREG r5, 0xBC000000;
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CHECKREG r6, 0x80000000;
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CHECKREG r7, 0xCDE00000;
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imm32 r0, 0xa1230001;
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imm32 r1, 0x1b345678;
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imm32 r2, 0x23c56789;
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imm32 r3, 0x34d6789a;
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imm32 r4, 0x85a789ab;
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imm32 r5, 0x967c9abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb8912cde;
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R6 = R0 >>> 1;
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R7 = R1 >>> 3;
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R0 = R2 >>> 7;
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R1 = R3 >>> 8;
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R2 = R4 >>> 15;
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R3 = R5 >>> 24;
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R4 = R6 >>> 31;
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R5 = R7 >>> 20;
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CHECKREG r0, 0x00478ACF;
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CHECKREG r1, 0x0034D678;
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CHECKREG r2, 0xFFFF0B4F;
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CHECKREG r3, 0xFFFFFF96;
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CHECKREG r4, 0xFFFFFFFF;
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CHECKREG r5, 0x00000036;
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CHECKREG r6, 0xD0918000;
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CHECKREG r7, 0x03668ACF;
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pass
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