2017-04-21 19:18:06 +08:00
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2017-04-21 Nick Clifton <nickc@redhat.com>
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PR binutils/21380
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* aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
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LD3R and LD4R.
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2017-04-13 09:03:53 +08:00
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2017-04-13 Alan Modra <amodra@gmail.com>
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* epiphany-desc.c: Regenerate.
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* fr30-desc.c: Regenerate.
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* frv-desc.c: Regenerate.
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* ip2k-desc.c: Regenerate.
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* iq2000-desc.c: Regenerate.
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* lm32-desc.c: Regenerate.
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* m32c-desc.c: Regenerate.
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* m32r-desc.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mt-desc.c: Regenerate.
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* or1k-desc.c: Regenerate.
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* xc16x-desc.c: Regenerate.
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* xstormy16-desc.c: Regenerate.
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2017-04-11 06:03:50 +08:00
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2017-04-11 Alan Modra <amodra@gmail.com>
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2017-04-11 06:10:24 +08:00
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* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
|
2017-04-11 06:13:21 +08:00
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PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
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PPC_OPCODE_TMR for e6500.
|
2017-04-11 06:03:50 +08:00
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* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
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(PPCVEC3): Define as PPC_OPCODE_POWER9.
|
2017-04-11 06:06:43 +08:00
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(PPCVSX2): Define as PPC_OPCODE_POWER8.
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(PPCVSX3): Define as PPC_OPCODE_POWER9.
|
2017-04-11 06:10:24 +08:00
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(PPCHTM): Define as PPC_OPCODE_POWER8.
|
2017-04-11 06:13:21 +08:00
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(powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
|
2017-04-11 06:03:50 +08:00
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2017-04-10 14:05:11 +08:00
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2017-04-10 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
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* ppc-opc.c (MULHW): Add PPC_OPCODE_476.
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(powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
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removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
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2017-04-10 08:10:28 +08:00
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2017-04-09 Pip Cet <pipcet@gmail.com>
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* wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
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|
appropriate floating-point precision directly.
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Remove E6500 insns from PPC_OPCODE_ALTIVEC2
This isn't losing anything from the testsuite. All of these insns
appear in testsuite/gas/ppc/e6500.s
opcodes/
* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
vector instructions with E6500 not PPCVEC2.
gas/
* testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
* testsuite/gas/ppc/altivec2.d: Adjust to suit.
2017-04-07 16:33:46 +08:00
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|
2017-04-07 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
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|
lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
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lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
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|
lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
|
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vector instructions with E6500 not PPCVEC2.
|
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|
2017-04-07 00:17:15 +08:00
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2017-04-06 Pip Cet <pipcet@gmail.com>
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* Makefile.am: Add wasm32-dis.c.
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* configure.ac: Add wasm32-dis.c to wasm32 target.
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* disassemble.c: Add wasm32 disassembler code.
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* wasm32-dis.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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* po/opcodes.pot: Regenerate.
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|
2017-04-06 02:21:33 +08:00
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|
2017-04-05 Pedro Alves <palves@redhat.com>
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* arc-dis.c (parse_option, parse_disassembler_options): Constify.
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* arm-dis.c (parse_arm_disassembler_options): Constify.
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* ppc-dis.c (powerpc_init_dialect): Constify local.
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* vax-dis.c (parse_disassembler_options): Constify.
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|
2017-04-04 01:08:29 +08:00
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|
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
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* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
|
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|
|
RISCV_GP_SYMBOL.
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|
2017-03-30 17:57:21 +08:00
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2017-03-30 Pip Cet <pipcet@gmail.com>
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* configure.ac: Add (empty) bfd_wasm32_arch target.
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* configure: Regenerate
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* po/opcodes.pot: Regenerate.
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|
2017-03-30 03:20:23 +08:00
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|
2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
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Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
|
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|
|
OSA2015.
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|
* opcodes/sparc-opc.c (asi_table): New ASIs.
|
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|
2017-03-29 11:13:06 +08:00
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|
2017-03-29 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
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|
"raw" option.
|
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|
(lookup_powerpc): Don't special case -1 dialect. Handle
|
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|
PPC_OPCODE_RAW.
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|
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
|
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|
lookup_powerpc call, pass it on second.
|
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|
2017-03-27 05:49:48 +08:00
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|
2017-03-27 Alan Modra <amodra@gmail.com>
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|
|
PR 21303
|
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|
* ppc-dis.c (struct ppc_mopt): Comment.
|
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|
(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
|
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|
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 18:14:30 +08:00
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|
2017-03-27 Rinat Zelig <rinat@mellanox.com>
|
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* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
|
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|
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
|
|
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|
F_NPS_M, F_NPS_CORE, F_NPS_ALL.
|
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|
(insert_nps_misc_imm_offset): New function.
|
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|
(extract_nps_misc imm_offset): New function.
|
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|
|
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
|
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(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
|
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|
2017-03-21 21:21:02 +08:00
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|
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-mkopc.c (main): Remove vx2 check.
|
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* s390-opc.txt: Remove vx2 instruction flags.
|
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|
2017-03-21 19:37:33 +08:00
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|
2017-03-21 Rinat Zelig <rinat@mellanox.com>
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|
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* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
|
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|
* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
|
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|
|
(insert_nps_imm_offset): New function.
|
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|
(extract_nps_imm_offset): New function.
|
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|
(insert_nps_imm_entry): New function.
|
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|
(extract_nps_imm_entry): New function.
|
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|
2017-03-17 16:36:12 +08:00
|
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|
|
2017-03-17 Alan Modra <amodra@gmail.com>
|
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|
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|
|
|
|
|
|
PR 21248
|
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|
|
|
* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
|
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|
|
|
|
mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
|
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|
|
|
|
those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
|
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|
2017-03-07 18:15:02 +08:00
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|
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
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|
|
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
|
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|
<c.andi>: Likewise.
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|
<c.addiw> Likewise.
|
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|
2017-03-07 19:56:40 +08:00
|
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|
|
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
|
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* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
|
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|
2017-03-14 03:46:33 +08:00
|
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|
|
2017-03-13 Andrew Waterman <andrew@sifive.com>
|
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|
|
* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
|
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|
<srl> Likewise.
|
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|
<srai> Likewise.
|
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|
<sra> Likewise.
|
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|
|
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-10 01:58:46 +08:00
|
|
|
|
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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|
|
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|
|
* i386-gen.c (opcode_modifiers): Replace S with Load.
|
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|
* i386-opc.h (S): Removed.
|
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|
|
(Load): New.
|
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|
|
|
|
(i386_opcode_modifier): Replace s with load.
|
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|
|
|
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
|
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|
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|
|
and {evex}. Replace S with Load.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2017-03-09 23:43:48 +08:00
|
|
|
|
2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
* i386-opc.tbl: Use CpuCET on rdsspq.
|
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|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2017-03-09 10:49:03 +08:00
|
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|
|
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
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|
|
|
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|
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|
|
* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
|
|
|
|
|
|
<vsx>: Do not use PPC_OPCODE_VSX3;
|
|
|
|
|
|
|
2017-03-09 04:00:42 +08:00
|
|
|
|
2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
|
|
|
|
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|
|
2017-03-07 07:26:37 +08:00
|
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|
|
2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (REG_0F1E_MOD_3): New enum.
|
|
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|
|
(MOD_0F1E_PREFIX_1): Likewise.
|
|
|
|
|
|
(MOD_0F38F5_PREFIX_2): Likewise.
|
|
|
|
|
|
(MOD_0F38F6_PREFIX_0): Likewise.
|
|
|
|
|
|
(RM_0F1E_MOD_3_REG_7): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_0_0F01_REG_5): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
|
|
|
|
|
|
(PREFIX_0F1E): Likewise.
|
|
|
|
|
|
(PREFIX_MOD_0_0FAE_REG_5): Likewise.
|
|
|
|
|
|
(PREFIX_0F38F5): Likewise.
|
|
|
|
|
|
(dis386_twobyte): Use PREFIX_0F1E.
|
|
|
|
|
|
(reg_table): Add REG_0F1E_MOD_3.
|
|
|
|
|
|
(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
|
|
|
|
|
|
PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
|
|
|
|
|
|
PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
|
|
|
|
|
|
PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
|
|
|
|
|
|
(three_byte_table): Use PREFIX_0F38F5.
|
|
|
|
|
|
(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
|
|
|
|
|
|
Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
|
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|
|
|
(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
|
|
|
|
|
|
RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
|
|
|
|
|
|
PREFIX_MOD_3_0F01_REG_5_RM_2.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuCET.
|
|
|
|
|
|
* i386-opc.h (CpuCET): New enum.
|
|
|
|
|
|
(CpuUnused): Commented out.
|
|
|
|
|
|
(i386_cpu_flags): Add cpucet.
|
|
|
|
|
|
* i386-opc.tbl: Add Intel CET instructions.
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2017-03-06 17:09:34 +08:00
|
|
|
|
2017-03-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21124
|
|
|
|
|
|
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
|
|
|
|
|
|
(extract_raq, extract_ras, extract_rbx): New functions.
|
|
|
|
|
|
(powerpc_operands): Use opposite corresponding insert function.
|
|
|
|
|
|
(Q_MASK): Define.
|
|
|
|
|
|
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
|
|
|
|
|
|
register restriction.
|
|
|
|
|
|
|
2017-03-01 02:32:07 +08:00
|
|
|
|
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* disassemble.c Include "safe-ctype.h".
|
|
|
|
|
|
(disassemble_init_for_target): Handle s390 init.
|
|
|
|
|
|
(remove_whitespace_and_extra_commas): New function.
|
|
|
|
|
|
(disassembler_options_cmp): Likewise.
|
|
|
|
|
|
* arm-dis.c: Include "libiberty.h".
|
|
|
|
|
|
(NUM_ELEM): Delete.
|
|
|
|
|
|
(regnames): Use long disassembler style names.
|
|
|
|
|
|
Add force-thumb and no-force-thumb options.
|
|
|
|
|
|
(NUM_ARM_REGNAMES): Rename from this...
|
|
|
|
|
|
(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
|
|
|
|
|
|
(get_arm_regname_num_options): Delete.
|
|
|
|
|
|
(set_arm_regname_option): Likewise.
|
|
|
|
|
|
(get_arm_regnames): Likewise.
|
|
|
|
|
|
(parse_disassembler_options): Likewise.
|
|
|
|
|
|
(parse_arm_disassembler_option): Rename from this...
|
|
|
|
|
|
(parse_arm_disassembler_options): ...to this. Make static.
|
|
|
|
|
|
Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
|
|
|
|
|
|
(print_insn): Use parse_arm_disassembler_options.
|
|
|
|
|
|
(disassembler_options_arm): New function.
|
|
|
|
|
|
(print_arm_disassembler_options): Handle updated regnames.
|
|
|
|
|
|
* ppc-dis.c: Include "libiberty.h".
|
|
|
|
|
|
(ppc_opts): Add "32" and "64" entries.
|
|
|
|
|
|
(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
|
|
|
|
|
|
(powerpc_init_dialect): Add break to switch statement.
|
|
|
|
|
|
Use new FOR_EACH_DISASSEMBLER_OPTION macro.
|
|
|
|
|
|
(disassembler_options_powerpc): New function.
|
|
|
|
|
|
(print_ppc_disassembler_options): Use ARRAY_SIZE.
|
|
|
|
|
|
Remove printing of "32" and "64".
|
|
|
|
|
|
* s390-dis.c: Include "libiberty.h".
|
|
|
|
|
|
(init_flag): Remove unneeded variable.
|
|
|
|
|
|
(struct s390_options_t): New structure type.
|
|
|
|
|
|
(options): New structure.
|
|
|
|
|
|
(init_disasm): Rename from this...
|
|
|
|
|
|
(disassemble_init_s390): ...to this. Add initializations for
|
|
|
|
|
|
current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
|
|
|
|
|
|
(print_insn_s390): Delete call to init_disasm.
|
|
|
|
|
|
(disassembler_options_s390): New function.
|
|
|
|
|
|
(print_s390_disassembler_options): Print using information from
|
|
|
|
|
|
struct 'options'.
|
|
|
|
|
|
* po/opcodes.pot: Regenerate.
|
|
|
|
|
|
|
2017-02-28 17:53:35 +08:00
|
|
|
|
2017-02-28 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (PCMPESTR_Fixup): New.
|
|
|
|
|
|
(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
|
|
|
|
|
|
(prefix_table): Use PCMPESTR_Fixup.
|
|
|
|
|
|
(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
|
|
|
|
|
|
PCMPESTR_Fixup.
|
|
|
|
|
|
(vex_w_table): Delete VPCMPESTR{I,M} entries.
|
|
|
|
|
|
* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
|
|
|
|
|
|
Split 64-bit and non-64-bit variants.
|
|
|
|
|
|
* opcodes/i386-tbl.h: Re-generate.
|
|
|
|
|
|
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
|
|
|
|
|
|
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
|
|
|
|
|
|
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
|
|
|
|
|
|
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
|
|
|
|
|
|
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
|
|
|
|
|
|
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
|
|
|
|
|
|
(OP_SVE_V_HSD): New macros.
|
|
|
|
|
|
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
|
|
|
|
|
|
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
|
|
|
|
|
|
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
|
|
|
|
|
|
(aarch64_opcode_table): Add new SVE instructions.
|
|
|
|
|
|
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
|
|
|
|
|
|
for rotation operands. Add new SVE operands.
|
|
|
|
|
|
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
|
|
|
|
|
|
(ins_sve_quad_index): Likewise.
|
|
|
|
|
|
(ins_imm_rotate): Split into...
|
|
|
|
|
|
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
|
|
|
|
|
|
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
|
|
|
|
|
|
functions.
|
|
|
|
|
|
(aarch64_ins_sve_addr_ri_s4): New function.
|
|
|
|
|
|
(aarch64_ins_sve_quad_index): Likewise.
|
|
|
|
|
|
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
|
|
|
|
|
|
(ext_sve_quad_index): Likewise.
|
|
|
|
|
|
(ext_imm_rotate): Split into...
|
|
|
|
|
|
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
|
|
|
|
|
|
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
|
|
|
|
|
|
functions.
|
|
|
|
|
|
(aarch64_ext_sve_addr_ri_s4): New function.
|
|
|
|
|
|
(aarch64_ext_sve_quad_index): Likewise.
|
|
|
|
|
|
(aarch64_ext_sve_index): Allow quad indices.
|
|
|
|
|
|
(do_misc_decoding): Likewise.
|
|
|
|
|
|
* aarch64-dis-2.c: Regenerate.
|
|
|
|
|
|
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
|
|
|
|
|
|
aarch64_field_kinds.
|
|
|
|
|
|
(OPD_F_OD_MASK): Widen by one bit.
|
|
|
|
|
|
(OPD_F_NO_ZR): Bump accordingly.
|
|
|
|
|
|
(get_operand_field_width): New function.
|
|
|
|
|
|
* aarch64-opc.c (fields): Add new SVE fields.
|
|
|
|
|
|
(operand_general_constraint_met_p): Handle new SVE operands.
|
|
|
|
|
|
(aarch64_print_operand): Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Regenerate.
|
|
|
|
|
|
|
2017-02-25 02:27:26 +08:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
|
|
|
|
|
|
(aarch64_feature_compnum): ...this.
|
|
|
|
|
|
(SIMD_V8_3): Replace with...
|
|
|
|
|
|
(COMPNUM): ...this.
|
|
|
|
|
|
(CNUM_INSN): New macro.
|
|
|
|
|
|
(aarch64_opcode_table): Use it for the complex number instructions.
|
|
|
|
|
|
|
2017-02-24 17:04:26 +08:00
|
|
|
|
2017-02-24 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
|
|
|
|
|
|
|
2017-02-23 23:49:37 +08:00
|
|
|
|
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
Add support for associating SPARC ASIs with an architecture level.
|
|
|
|
|
|
* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
|
|
|
|
|
|
* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
|
|
|
|
|
|
decoding of SPARC ASIs.
|
|
|
|
|
|
|
2017-02-23 18:03:55 +08:00
|
|
|
|
2017-02-23 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
|
|
|
|
|
|
82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
|
|
|
|
|
|
|
2017-02-22 17:36:05 +08:00
|
|
|
|
2017-02-21 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
|
|
|
|
|
|
1 (instead of to itself). Correct typo.
|
|
|
|
|
|
|
2017-02-15 07:37:04 +08:00
|
|
|
|
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
|
|
|
|
|
|
pseudoinstructions.
|
|
|
|
|
|
|
2017-02-16 00:54:21 +08:00
|
|
|
|
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
|
|
|
|
|
|
(aarch64_sys_reg_supported_p): Handle them.
|
|
|
|
|
|
|
2017-02-15 18:57:51 +08:00
|
|
|
|
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-opc.c (UIMM6_20R): Define.
|
|
|
|
|
|
(SIMM12_20): Use above.
|
|
|
|
|
|
(SIMM12_20R): Define.
|
|
|
|
|
|
(SIMM3_5_S): Use above.
|
|
|
|
|
|
(UIMM7_A32_11R_S): Define.
|
|
|
|
|
|
(UIMM7_9_S): Use above.
|
|
|
|
|
|
(UIMM3_13R_S): Define.
|
|
|
|
|
|
(SIMM11_A32_7_S): Use above.
|
|
|
|
|
|
(SIMM9_8R): Define.
|
|
|
|
|
|
(UIMM10_A32_8_S): Use above.
|
|
|
|
|
|
(UIMM8_8R_S): Define.
|
|
|
|
|
|
(W6): Use above.
|
|
|
|
|
|
(arc_relax_opcodes): Use all above defines.
|
|
|
|
|
|
|
2017-02-15 16:52:53 +08:00
|
|
|
|
2017-02-15 Vineet Gupta <vgupta@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arc-regs.h: Distinguish some of the registers different on
|
|
|
|
|
|
ARC700 and HS38 cpus.
|
|
|
|
|
|
|
2017-02-14 18:08:21 +08:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
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|
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
|
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|
|
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
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2017-02-11 14:47:59 +08:00
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2017-02-11 Stafford Horne <shorne@gmail.com>
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Alan Modra <amodra@gmail.com>
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* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
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|
Use insn_bytes_value and insn_int_value directly instead. Don't
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|
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free allocated memory until function exit.
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2017-02-10 12:18:23 +08:00
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2017-02-10 Nicholas Piggin <npiggin@gmail.com>
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* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
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|
2017-02-03 17:04:21 +08:00
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2017-02-03 Nick Clifton <nickc@redhat.com>
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PR 21096
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* aarch64-opc.c (print_register_list): Ensure that the register
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|
|
list index will fir into the tb buffer.
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|
|
(print_register_offset_address): Likewise.
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|
|
* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
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|
2017-01-27 20:00:55 +08:00
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2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
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|
|
PR 21056
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|
|
* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
|
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|
|
instructions when the previous fetch packet ends with a 32-bit
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|
|
instruction.
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|
2017-01-25 20:19:27 +08:00
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|
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
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|
|
* pru-opc.c: Remove vague reference to a future GDB port.
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|
2017-01-20 20:25:07 +08:00
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|
|
2017-01-20 Nick Clifton <nickc@redhat.com>
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|
|
* po/ga.po: Updated Irish translation.
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|
2017-01-19 01:08:34 +08:00
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|
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
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|
|
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
|
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|
2017-01-13 20:27:39 +08:00
|
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|
|
2017-01-13 Yao Qi <yao.qi@linaro.org>
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|
|
* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
|
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|
if FETCH_DATA returns 0.
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|
(m68k_scan_mask): Likewise.
|
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|
|
(print_insn_m68k): Update code to handle -1 return value.
|
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|
2017-01-13 20:21:22 +08:00
|
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|
|
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
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|
|
* m68k-dis.c (enum print_insn_arg_error): New.
|
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|
|
(NEXTBYTE): Replace -3 with
|
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|
|
|
|
PRINT_INSN_ARG_MEMORY_ERROR.
|
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|
(NEXTULONG): Likewise.
|
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|
(NEXTSINGLE): Likewise.
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|
(NEXTDOUBLE): Likewise.
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|
(NEXTDOUBLE): Likewise.
|
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|
|
(NEXTPACKED): Likewise.
|
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|
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|
|
(FETCH_ARG): Likewise.
|
|
|
|
|
|
(FETCH_DATA): Update comments.
|
|
|
|
|
|
(print_insn_arg): Update comments. Replace magic numbers with
|
|
|
|
|
|
enum.
|
|
|
|
|
|
(match_insn_m68k): Likewise.
|
|
|
|
|
|
|
2017-01-13 00:42:17 +08:00
|
|
|
|
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
|
|
|
|
|
|
* i386-dis-evex.h (evex_table): Updated.
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
|
|
|
|
|
|
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
|
|
|
|
|
|
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
|
|
|
|
|
|
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
|
|
|
|
|
|
* i386-init.h: Regenerate.
|
|
|
|
|
|
* i386-tbl.h: Ditto.
|
|
|
|
|
|
|
2017-01-12 17:40:41 +08:00
|
|
|
|
2017-01-12 Yao Qi <yao.qi@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430-dis.c (msp430_singleoperand): Return -1 if
|
|
|
|
|
|
msp430dis_opcode_signed returns false.
|
|
|
|
|
|
(msp430_doubleoperand): Likewise.
|
|
|
|
|
|
(msp430_branchinstr): Return -1 if
|
|
|
|
|
|
msp430dis_opcode_unsigned returns false.
|
|
|
|
|
|
(msp430x_calla_instr): Likewise.
|
|
|
|
|
|
(print_insn_msp430): Likewise.
|
|
|
|
|
|
|
2017-01-05 17:11:47 +08:00
|
|
|
|
2017-01-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 20946
|
|
|
|
|
|
* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
|
|
|
|
|
|
could not be matched.
|
|
|
|
|
|
(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
|
|
|
|
|
|
NULL.
|
|
|
|
|
|
|
2017-01-04 20:27:10 +08:00
|
|
|
|
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
|
|
|
|
|
|
(aarch64_opcode_table): Use RCPC_INSN.
|
|
|
|
|
|
|
2017-01-04 01:42:01 +08:00
|
|
|
|
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
|
|
|
|
|
|
extension.
|
|
|
|
|
|
* riscv-opcodes/all-opcodes: Likewise.
|
|
|
|
|
|
|
2017-01-04 00:02:36 +08:00
|
|
|
|
2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
|
|
|
|
|
|
|
|
|
|
|
|
* riscv-dis.c (print_insn_args): Add fall through comment.
|
|
|
|
|
|
|
2017-01-03 23:51:11 +08:00
|
|
|
|
2017-01-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/sr.po: New Serbian translation.
|
|
|
|
|
|
* configure.ac (ALL_LINGUAS): Add sr.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2017-01-02 21:27:58 +08:00
|
|
|
|
2017-01-02 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* epiphany-desc.h: Regenerate.
|
|
|
|
|
|
* epiphany-opc.h: Regenerate.
|
|
|
|
|
|
* fr30-desc.h: Regenerate.
|
|
|
|
|
|
* fr30-opc.h: Regenerate.
|
|
|
|
|
|
* frv-desc.h: Regenerate.
|
|
|
|
|
|
* frv-opc.h: Regenerate.
|
|
|
|
|
|
* ip2k-desc.h: Regenerate.
|
|
|
|
|
|
* ip2k-opc.h: Regenerate.
|
|
|
|
|
|
* iq2000-desc.h: Regenerate.
|
|
|
|
|
|
* iq2000-opc.h: Regenerate.
|
|
|
|
|
|
* lm32-desc.h: Regenerate.
|
|
|
|
|
|
* lm32-opc.h: Regenerate.
|
|
|
|
|
|
* m32c-desc.h: Regenerate.
|
|
|
|
|
|
* m32c-opc.h: Regenerate.
|
|
|
|
|
|
* m32r-desc.h: Regenerate.
|
|
|
|
|
|
* m32r-opc.h: Regenerate.
|
|
|
|
|
|
* mep-desc.h: Regenerate.
|
|
|
|
|
|
* mep-opc.h: Regenerate.
|
|
|
|
|
|
* mt-desc.h: Regenerate.
|
|
|
|
|
|
* mt-opc.h: Regenerate.
|
|
|
|
|
|
* or1k-desc.h: Regenerate.
|
|
|
|
|
|
* or1k-opc.h: Regenerate.
|
|
|
|
|
|
* xc16x-desc.h: Regenerate.
|
|
|
|
|
|
* xc16x-opc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-desc.h: Regenerate.
|
|
|
|
|
|
* xstormy16-opc.h: Regenerate.
|
|
|
|
|
|
|
2017-01-02 11:36:43 +08:00
|
|
|
|
2017-01-02 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2017-01-02 11:25:05 +08:00
|
|
|
|
For older changes see ChangeLog-2016
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
2017-01-02 11:25:05 +08:00
|
|
|
|
Copyright (C) 2017 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
