binutils-gdb/gdb/arch/riscv.c

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/* Copyright (C) 2018-2022 Free Software Foundation, Inc.
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
Rename common to gdbsupport This is the next patch in the ongoing series to move gdbsever to the top level. This patch just renames the "common" directory. The idea is to do this move in two parts: first rename the directory (this patch), then move the directory to the top. This approach makes the patches a bit more tractable. I chose the name "gdbsupport" for the directory. However, as this patch was largely written by sed, we could pick a new name without too much difficulty. Tested by the buildbot. gdb/ChangeLog 2019-07-09 Tom Tromey <tom@tromey.com> * contrib/ari/gdb_ari.sh: Change common to gdbsupport. * configure: Rebuild. * configure.ac: Change common to gdbsupport. * gdbsupport: Rename from common. * acinclude.m4: Change common to gdbsupport. * Makefile.in (CONFIG_SRC_SUBDIR, COMMON_SFILES) (HFILES_NO_SRCDIR, stamp-version, ALLDEPFILES): Change common to gdbsupport. * aarch64-tdep.c, ada-lang.c, ada-lang.h, agent.c, alloc.c, amd64-darwin-tdep.c, amd64-dicos-tdep.c, amd64-fbsd-nat.c, amd64-fbsd-tdep.c, amd64-linux-nat.c, amd64-linux-tdep.c, amd64-nbsd-tdep.c, amd64-obsd-tdep.c, amd64-sol2-tdep.c, amd64-tdep.c, amd64-windows-tdep.c, arch-utils.c, arch/aarch64-insn.c, arch/aarch64.c, arch/aarch64.h, arch/amd64.c, arch/amd64.h, arch/arm-get-next-pcs.c, arch/arm-linux.c, arch/arm.c, arch/i386.c, arch/i386.h, arch/ppc-linux-common.c, arch/riscv.c, arch/riscv.h, arch/tic6x.c, arm-tdep.c, auto-load.c, auxv.c, ax-gdb.c, ax-general.c, ax.h, breakpoint.c, breakpoint.h, btrace.c, btrace.h, build-id.c, build-id.h, c-lang.h, charset.c, charset.h, cli/cli-cmds.c, cli/cli-cmds.h, cli/cli-decode.c, cli/cli-dump.c, cli/cli-option.h, cli/cli-script.c, coff-pe-read.c, command.h, compile/compile-c-support.c, compile/compile-c.h, compile/compile-cplus-symbols.c, compile/compile-cplus-types.c, compile/compile-cplus.h, compile/compile-loc2c.c, compile/compile.c, completer.c, completer.h, contrib/ari/gdb_ari.sh, corefile.c, corelow.c, cp-support.c, cp-support.h, cp-valprint.c, csky-tdep.c, ctf.c, darwin-nat.c, debug.c, defs.h, disasm-selftests.c, disasm.c, disasm.h, dtrace-probe.c, dwarf-index-cache.c, dwarf-index-cache.h, dwarf-index-write.c, dwarf2-frame.c, dwarf2expr.c, dwarf2loc.c, dwarf2read.c, event-loop.c, event-top.c, exceptions.c, exec.c, extension.h, fbsd-nat.c, features/aarch64-core.c, features/aarch64-fpu.c, features/aarch64-pauth.c, features/aarch64-sve.c, features/i386/32bit-avx.c, features/i386/32bit-avx512.c, features/i386/32bit-core.c, features/i386/32bit-linux.c, features/i386/32bit-mpx.c, features/i386/32bit-pkeys.c, features/i386/32bit-segments.c, features/i386/32bit-sse.c, features/i386/64bit-avx.c, features/i386/64bit-avx512.c, features/i386/64bit-core.c, features/i386/64bit-linux.c, features/i386/64bit-mpx.c, features/i386/64bit-pkeys.c, features/i386/64bit-segments.c, features/i386/64bit-sse.c, features/i386/x32-core.c, features/riscv/32bit-cpu.c, features/riscv/32bit-csr.c, features/riscv/32bit-fpu.c, features/riscv/64bit-cpu.c, features/riscv/64bit-csr.c, features/riscv/64bit-fpu.c, features/tic6x-c6xp.c, features/tic6x-core.c, features/tic6x-gp.c, filename-seen-cache.h, findcmd.c, findvar.c, fork-child.c, gcore.c, gdb_bfd.c, gdb_bfd.h, gdb_proc_service.h, gdb_regex.c, gdb_select.h, gdb_usleep.c, gdbarch-selftests.c, gdbthread.h, gdbtypes.h, gnu-nat.c, go32-nat.c, guile/guile.c, guile/scm-ports.c, guile/scm-safe-call.c, guile/scm-type.c, i386-fbsd-nat.c, i386-fbsd-tdep.c, i386-go32-tdep.c, i386-linux-nat.c, i386-linux-tdep.c, i386-tdep.c, i387-tdep.c, ia64-libunwind-tdep.c, ia64-linux-nat.c, inf-child.c, inf-ptrace.c, infcall.c, infcall.h, infcmd.c, inferior-iter.h, inferior.c, inferior.h, inflow.c, inflow.h, infrun.c, infrun.h, inline-frame.c, language.h, linespec.c, linux-fork.c, linux-nat.c, linux-tdep.c, linux-thread-db.c, location.c, machoread.c, macrotab.h, main.c, maint.c, maint.h, memattr.c, memrange.h, mi/mi-cmd-break.h, mi/mi-cmd-env.c, mi/mi-cmd-stack.c, mi/mi-cmd-var.c, mi/mi-interp.c, mi/mi-main.c, mi/mi-parse.h, minsyms.c, mips-linux-tdep.c, namespace.h, nat/aarch64-linux-hw-point.c, nat/aarch64-linux-hw-point.h, nat/aarch64-linux.c, nat/aarch64-sve-linux-ptrace.c, nat/amd64-linux-siginfo.c, nat/fork-inferior.c, nat/linux-btrace.c, nat/linux-btrace.h, nat/linux-namespaces.c, nat/linux-nat.h, nat/linux-osdata.c, nat/linux-personality.c, nat/linux-procfs.c, nat/linux-ptrace.c, nat/linux-ptrace.h, nat/linux-waitpid.c, nat/mips-linux-watch.c, nat/mips-linux-watch.h, nat/ppc-linux.c, nat/x86-dregs.c, nat/x86-dregs.h, nat/x86-linux-dregs.c, nat/x86-linux.c, nto-procfs.c, nto-tdep.c, objfile-flags.h, objfiles.c, objfiles.h, obsd-nat.c, observable.h, osdata.c, p-valprint.c, parse.c, parser-defs.h, ppc-linux-nat.c, printcmd.c, probe.c, proc-api.c, procfs.c, producer.c, progspace.h, psymtab.h, python/py-framefilter.c, python/py-inferior.c, python/py-ref.h, python/py-type.c, python/python.c, record-btrace.c, record-full.c, record.c, record.h, regcache-dump.c, regcache.c, regcache.h, remote-fileio.c, remote-fileio.h, remote-sim.c, remote.c, riscv-tdep.c, rs6000-aix-tdep.c, rust-exp.y, s12z-tdep.c, selftest-arch.c, ser-base.c, ser-event.c, ser-pipe.c, ser-tcp.c, ser-unix.c, skip.c, solib-aix.c, solib-target.c, solib.c, source-cache.c, source.c, source.h, sparc-nat.c, spu-linux-nat.c, stack.c, stap-probe.c, symfile-add-flags.h, symfile.c, symfile.h, symtab.c, symtab.h, target-descriptions.c, target-descriptions.h, target-memory.c, target.c, target.h, target/waitstatus.c, target/waitstatus.h, thread-iter.h, thread.c, tilegx-tdep.c, top.c, top.h, tracefile-tfile.c, tracefile.c, tracepoint.c, tracepoint.h, tui/tui-io.c, ui-file.c, ui-out.h, unittests/array-view-selftests.c, unittests/child-path-selftests.c, unittests/cli-utils-selftests.c, unittests/common-utils-selftests.c, unittests/copy_bitwise-selftests.c, unittests/environ-selftests.c, unittests/format_pieces-selftests.c, unittests/function-view-selftests.c, unittests/lookup_name_info-selftests.c, unittests/memory-map-selftests.c, unittests/memrange-selftests.c, unittests/mkdir-recursive-selftests.c, unittests/observable-selftests.c, unittests/offset-type-selftests.c, unittests/optional-selftests.c, unittests/parse-connection-spec-selftests.c, unittests/ptid-selftests.c, unittests/rsp-low-selftests.c, unittests/scoped_fd-selftests.c, unittests/scoped_mmap-selftests.c, unittests/scoped_restore-selftests.c, unittests/string_view-selftests.c, unittests/style-selftests.c, unittests/tracepoint-selftests.c, unittests/unpack-selftests.c, unittests/utils-selftests.c, unittests/xml-utils-selftests.c, utils.c, utils.h, valarith.c, valops.c, valprint.c, value.c, value.h, varobj.c, varobj.h, windows-nat.c, x86-linux-nat.c, xml-support.c, xml-support.h, xml-tdesc.h, xstormy16-tdep.c, xtensa-linux-nat.c, dwarf2read.h: Change common to gdbsupport. gdb/gdbserver/ChangeLog 2019-07-09 Tom Tromey <tom@tromey.com> * configure: Rebuild. * configure.ac: Change common to gdbsupport. * acinclude.m4: Change common to gdbsupport. * Makefile.in (SFILES, OBS, GDBREPLAY_OBS, IPA_OBJS) (version-generated.c, gdbsupport/%-ipa.o, gdbsupport/%.o): Change common to gdbsupport. * ax.c, event-loop.c, fork-child.c, gdb_proc_service.h, gdbreplay.c, gdbthread.h, hostio-errno.c, hostio.c, i387-fp.c, inferiors.c, inferiors.h, linux-aarch64-tdesc-selftest.c, linux-amd64-ipa.c, linux-i386-ipa.c, linux-low.c, linux-tic6x-low.c, linux-x86-low.c, linux-x86-tdesc-selftest.c, linux-x86-tdesc.c, lynx-i386-low.c, lynx-low.c, mem-break.h, nto-x86-low.c, regcache.c, regcache.h, remote-utils.c, server.c, server.h, spu-low.c, symbol.c, target.h, tdesc.c, tdesc.h, thread-db.c, tracepoint.c, win32-i386-low.c, win32-low.c: Change common to gdbsupport.
2019-05-06 10:29:24 +08:00
#include "gdbsupport/common-defs.h"
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
#include "riscv.h"
#include <stdlib.h>
gdb/riscv: Create each unique target description only once GDB relies on the fact that if two target descriptions have the same contents, then they will be the same object instance (having the same address). One place where this is a requirement is in GDBARCH_LIST_LOOKUP_BY_INFO which is used to find previously created gdbarch objects. In GDBARCH_LIST_LOOKUP_BY_INFO a pointer comparison is made on the gdbarch's target description, if the pointers are different then it is assumed the gdbarches have different, non-compatible target descriptions. Previously we would create duplicate target descriptions in the belief that RISCV_GDBARCH_INIT would spot this duplication and discard the second instance. However, this was incorrect, and instead we ended up creating duplicate gdbarch objects. With this commit every unique feature set will create one and only one target description, the feature set and resulting target description is then cached so that the same target description object can be returned later. Many other target avoid this problem by creating a small number of named target descriptions, and returning one of these. However, we currently have 8 possible target descriptions (32 vs 64 bit for x-reg and f-reg, and h/w or s/w float abi) and creating each of these just to avoid a dynamic cache seems pointless. gdb/ChangeLog: * arch/riscv.h (riscv_gdbarch_features::hash): New method. * arch/riscv.c (struct riscv_gdbarch_features_hasher): New. (riscv_tdesc_cache): New global. (riscv_create_target_description): Look in the cache before creating a new target description.
2018-11-29 23:51:58 +08:00
#include <unordered_map>
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
#include "../features/riscv/32bit-cpu.c"
#include "../features/riscv/64bit-cpu.c"
#include "../features/riscv/32bit-fpu.c"
#include "../features/riscv/64bit-fpu.c"
gdb/riscv: rewrite target description validation, add rv32e support This commit started as adding rv32e support to gdb. The rv32e architecture is a cut-down rv32i, it only has 16 x-registers compared to the usual 32, and an rv32e target should not have any floating point registers. In order to add this I needed to adjust the target description validation checks that are performed from riscv_gdbarch_init, and I finally got fed up with the current scheme of doing these checks and rewrote this code. Unfortunately the rv32e changes are currently mixed in with the rewrite of the validation scheme. I could split these apart if anyone is really interested in seeing these two ideas as separate patches. The main idea behind this change is that where previously I tried to have a purely data driven approach, a set of tables one for each expected feature, and then a single generic function that would validate a feature given a table, I have created a new class for each feature. Each class has its own check member function which allows the logic for how to check each feature to be different. I think the new scheme is much easier to follow. There are some other changes that I made to the validation code as part of this commit. I've relaxed some of the checks related to the floating point CSRs. Previously the 3 CSRs fflags, frm, and fcsr all had to be present in either the fpu feature or the csr feature. This requirement is now relaxed, if the CSRs are not present then gdb will not reject the target description. My thinking here is that there's no gdb functionality that specifically requires these registers, and so, if a target offers a description without these registers nothing else in gdb should stop working. And as part of the rv32e support targets now only have to provide the first 16 x-registers and $pc. The second half of the x-registers (x16 -> x31) are now optional. gdb/ChangeLog: * arch/riscv.c: Include 'rv32e-xregs.c'. (riscv_create_target_description): Update to handle rv32e. * arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New member variable. <operator==>: Update to account for new field. <hash>: Likewise. * features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml. * features/riscv/rv32e-xregs.c: Generated. * features/riscv/rv32e-xregs.xml: New file. * riscv-tdep.c (riscv_debug_breakpoints): Move from later in the file. (riscv_debug_infcall): Likewise. (riscv_debug_unwinder): Likewise. (riscv_debug_gdbarch): Likewise. (enum riscv_register_required_status): Delete. (struct riscv_register_feature): Add constructor, delete default constructor, copy, and assign constructors. (struct riscv_register_feature::register_info) <required>: Delete. <check>: Update comment and arguments. (struct riscv_register_feature) <name>: Change to member function. <prefer_first_name>: Delete. <tdesc_feature>: New member function. <registers>: Rename to... <m_registers>: ...this. <m_feature_name>: New member variable. (riscv_register_feature::register_info::check): Update arguments. (riscv_xreg_feature): Rewrite as class, create a single static instance of the class. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_create_csr_aliases): Has become a member function inside riscv_csr_feature class. (riscv_abi_embedded): New function definition. (riscv_register_name): Adjust to use new feature objects. (struct riscv_call_info) <riscv_call_info>: Check for rv32e abi, and adjust available argument registers. (riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag. (riscv_check_tdesc_feature): Delete. (riscv_tdesc_unknown_reg): Adjust to use new feature objects. (riscv_gdbarch_init): Delete target description checking code, and instead call to the new feature objects to perform the checks. Reorder handling of no abi information case, allows small code simplification. (_initialize_riscv_tdep): Remove call, this is now done in the riscv_csr_feature constructor. * riscv-tdep.h (riscv_abi_embedded): Declare.
2020-11-24 02:03:32 +08:00
#include "../features/riscv/rv32e-xregs.c"
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
#ifndef GDBSERVER
#define STATIC_IN_GDB static
#else
#define STATIC_IN_GDB
#endif
gdb/riscv: Create each unique target description only once GDB relies on the fact that if two target descriptions have the same contents, then they will be the same object instance (having the same address). One place where this is a requirement is in GDBARCH_LIST_LOOKUP_BY_INFO which is used to find previously created gdbarch objects. In GDBARCH_LIST_LOOKUP_BY_INFO a pointer comparison is made on the gdbarch's target description, if the pointers are different then it is assumed the gdbarches have different, non-compatible target descriptions. Previously we would create duplicate target descriptions in the belief that RISCV_GDBARCH_INIT would spot this duplication and discard the second instance. However, this was incorrect, and instead we ended up creating duplicate gdbarch objects. With this commit every unique feature set will create one and only one target description, the feature set and resulting target description is then cached so that the same target description object can be returned later. Many other target avoid this problem by creating a small number of named target descriptions, and returning one of these. However, we currently have 8 possible target descriptions (32 vs 64 bit for x-reg and f-reg, and h/w or s/w float abi) and creating each of these just to avoid a dynamic cache seems pointless. gdb/ChangeLog: * arch/riscv.h (riscv_gdbarch_features::hash): New method. * arch/riscv.c (struct riscv_gdbarch_features_hasher): New. (riscv_tdesc_cache): New global. (riscv_create_target_description): Look in the cache before creating a new target description.
2018-11-29 23:51:58 +08:00
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
/* See arch/riscv.h. */
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
STATIC_IN_GDB target_desc_up
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
riscv_create_target_description (const struct riscv_gdbarch_features features)
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
{
gdb/riscv: Create each unique target description only once GDB relies on the fact that if two target descriptions have the same contents, then they will be the same object instance (having the same address). One place where this is a requirement is in GDBARCH_LIST_LOOKUP_BY_INFO which is used to find previously created gdbarch objects. In GDBARCH_LIST_LOOKUP_BY_INFO a pointer comparison is made on the gdbarch's target description, if the pointers are different then it is assumed the gdbarches have different, non-compatible target descriptions. Previously we would create duplicate target descriptions in the belief that RISCV_GDBARCH_INIT would spot this duplication and discard the second instance. However, this was incorrect, and instead we ended up creating duplicate gdbarch objects. With this commit every unique feature set will create one and only one target description, the feature set and resulting target description is then cached so that the same target description object can be returned later. Many other target avoid this problem by creating a small number of named target descriptions, and returning one of these. However, we currently have 8 possible target descriptions (32 vs 64 bit for x-reg and f-reg, and h/w or s/w float abi) and creating each of these just to avoid a dynamic cache seems pointless. gdb/ChangeLog: * arch/riscv.h (riscv_gdbarch_features::hash): New method. * arch/riscv.c (struct riscv_gdbarch_features_hasher): New. (riscv_tdesc_cache): New global. (riscv_create_target_description): Look in the cache before creating a new target description.
2018-11-29 23:51:58 +08:00
/* Now we should create a new target description. */
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
target_desc_up tdesc = allocate_target_description ();
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
#ifndef IN_PROCESS_AGENT
std::string arch_name = "riscv";
if (features.xlen == 4)
gdb/riscv: rewrite target description validation, add rv32e support This commit started as adding rv32e support to gdb. The rv32e architecture is a cut-down rv32i, it only has 16 x-registers compared to the usual 32, and an rv32e target should not have any floating point registers. In order to add this I needed to adjust the target description validation checks that are performed from riscv_gdbarch_init, and I finally got fed up with the current scheme of doing these checks and rewrote this code. Unfortunately the rv32e changes are currently mixed in with the rewrite of the validation scheme. I could split these apart if anyone is really interested in seeing these two ideas as separate patches. The main idea behind this change is that where previously I tried to have a purely data driven approach, a set of tables one for each expected feature, and then a single generic function that would validate a feature given a table, I have created a new class for each feature. Each class has its own check member function which allows the logic for how to check each feature to be different. I think the new scheme is much easier to follow. There are some other changes that I made to the validation code as part of this commit. I've relaxed some of the checks related to the floating point CSRs. Previously the 3 CSRs fflags, frm, and fcsr all had to be present in either the fpu feature or the csr feature. This requirement is now relaxed, if the CSRs are not present then gdb will not reject the target description. My thinking here is that there's no gdb functionality that specifically requires these registers, and so, if a target offers a description without these registers nothing else in gdb should stop working. And as part of the rv32e support targets now only have to provide the first 16 x-registers and $pc. The second half of the x-registers (x16 -> x31) are now optional. gdb/ChangeLog: * arch/riscv.c: Include 'rv32e-xregs.c'. (riscv_create_target_description): Update to handle rv32e. * arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New member variable. <operator==>: Update to account for new field. <hash>: Likewise. * features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml. * features/riscv/rv32e-xregs.c: Generated. * features/riscv/rv32e-xregs.xml: New file. * riscv-tdep.c (riscv_debug_breakpoints): Move from later in the file. (riscv_debug_infcall): Likewise. (riscv_debug_unwinder): Likewise. (riscv_debug_gdbarch): Likewise. (enum riscv_register_required_status): Delete. (struct riscv_register_feature): Add constructor, delete default constructor, copy, and assign constructors. (struct riscv_register_feature::register_info) <required>: Delete. <check>: Update comment and arguments. (struct riscv_register_feature) <name>: Change to member function. <prefer_first_name>: Delete. <tdesc_feature>: New member function. <registers>: Rename to... <m_registers>: ...this. <m_feature_name>: New member variable. (riscv_register_feature::register_info::check): Update arguments. (riscv_xreg_feature): Rewrite as class, create a single static instance of the class. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_create_csr_aliases): Has become a member function inside riscv_csr_feature class. (riscv_abi_embedded): New function definition. (riscv_register_name): Adjust to use new feature objects. (struct riscv_call_info) <riscv_call_info>: Check for rv32e abi, and adjust available argument registers. (riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag. (riscv_check_tdesc_feature): Delete. (riscv_tdesc_unknown_reg): Adjust to use new feature objects. (riscv_gdbarch_init): Delete target description checking code, and instead call to the new feature objects to perform the checks. Reorder handling of no abi information case, allows small code simplification. (_initialize_riscv_tdep): Remove call, this is now done in the riscv_csr_feature constructor. * riscv-tdep.h (riscv_abi_embedded): Declare.
2020-11-24 02:03:32 +08:00
{
if (features.embedded)
arch_name.append (":rv32e");
else
arch_name.append (":rv32i");
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
else if (features.xlen == 8)
arch_name.append (":rv64i");
else if (features.xlen == 16)
arch_name.append (":rv128i");
if (features.flen == 4)
arch_name.append ("f");
else if (features.flen == 8)
arch_name.append ("d");
else if (features.flen == 16)
arch_name.append ("q");
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
set_tdesc_architecture (tdesc.get (), arch_name.c_str ());
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
#endif
long regnum = 0;
/* For now we only support creating 32-bit or 64-bit x-registers. */
if (features.xlen == 4)
gdb/riscv: rewrite target description validation, add rv32e support This commit started as adding rv32e support to gdb. The rv32e architecture is a cut-down rv32i, it only has 16 x-registers compared to the usual 32, and an rv32e target should not have any floating point registers. In order to add this I needed to adjust the target description validation checks that are performed from riscv_gdbarch_init, and I finally got fed up with the current scheme of doing these checks and rewrote this code. Unfortunately the rv32e changes are currently mixed in with the rewrite of the validation scheme. I could split these apart if anyone is really interested in seeing these two ideas as separate patches. The main idea behind this change is that where previously I tried to have a purely data driven approach, a set of tables one for each expected feature, and then a single generic function that would validate a feature given a table, I have created a new class for each feature. Each class has its own check member function which allows the logic for how to check each feature to be different. I think the new scheme is much easier to follow. There are some other changes that I made to the validation code as part of this commit. I've relaxed some of the checks related to the floating point CSRs. Previously the 3 CSRs fflags, frm, and fcsr all had to be present in either the fpu feature or the csr feature. This requirement is now relaxed, if the CSRs are not present then gdb will not reject the target description. My thinking here is that there's no gdb functionality that specifically requires these registers, and so, if a target offers a description without these registers nothing else in gdb should stop working. And as part of the rv32e support targets now only have to provide the first 16 x-registers and $pc. The second half of the x-registers (x16 -> x31) are now optional. gdb/ChangeLog: * arch/riscv.c: Include 'rv32e-xregs.c'. (riscv_create_target_description): Update to handle rv32e. * arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New member variable. <operator==>: Update to account for new field. <hash>: Likewise. * features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml. * features/riscv/rv32e-xregs.c: Generated. * features/riscv/rv32e-xregs.xml: New file. * riscv-tdep.c (riscv_debug_breakpoints): Move from later in the file. (riscv_debug_infcall): Likewise. (riscv_debug_unwinder): Likewise. (riscv_debug_gdbarch): Likewise. (enum riscv_register_required_status): Delete. (struct riscv_register_feature): Add constructor, delete default constructor, copy, and assign constructors. (struct riscv_register_feature::register_info) <required>: Delete. <check>: Update comment and arguments. (struct riscv_register_feature) <name>: Change to member function. <prefer_first_name>: Delete. <tdesc_feature>: New member function. <registers>: Rename to... <m_registers>: ...this. <m_feature_name>: New member variable. (riscv_register_feature::register_info::check): Update arguments. (riscv_xreg_feature): Rewrite as class, create a single static instance of the class. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_create_csr_aliases): Has become a member function inside riscv_csr_feature class. (riscv_abi_embedded): New function definition. (riscv_register_name): Adjust to use new feature objects. (struct riscv_call_info) <riscv_call_info>: Check for rv32e abi, and adjust available argument registers. (riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag. (riscv_check_tdesc_feature): Delete. (riscv_tdesc_unknown_reg): Adjust to use new feature objects. (riscv_gdbarch_init): Delete target description checking code, and instead call to the new feature objects to perform the checks. Reorder handling of no abi information case, allows small code simplification. (_initialize_riscv_tdep): Remove call, this is now done in the riscv_csr_feature constructor. * riscv-tdep.h (riscv_abi_embedded): Declare.
2020-11-24 02:03:32 +08:00
{
if (features.embedded)
regnum = create_feature_riscv_rv32e_xregs (tdesc.get (), regnum);
else
regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum);
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
else if (features.xlen == 8)
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
/* For now we only support creating 32-bit or 64-bit f-registers. */
if (features.flen == 4)
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
regnum = create_feature_riscv_32bit_fpu (tdesc.get (), regnum);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
else if (features.flen == 8)
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
regnum = create_feature_riscv_64bit_fpu (tdesc.get (), regnum);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
gdb/riscv: add support for vector registers in target descriptions This commit adds support to RISC-V GDB for vector registers in the incoming target description. The vector registers should be described in a feature called "org.gnu.gdb.riscv.vector", and should contain the register v0 to v31. There's no restriction on the size or type of these registers, so the target description can set these up as it requires. However, if the target feature is present then all of the registers must be present, and they must all be the same size, these requirements are, I believe, inline with the RISC-V vector extension. The DWARF register numbers for the vector registers have been added, and the code to map between GDB's internal numbering and the DWARF numbering has been updated. I have not yet added a feature/riscv/*.xml file for the vector extension, the consequence of this is that we can't, right now, detect vector registers on a native target, this patch is all about supporting vectors on a remote target. It is worth noting that I don't actually have access to a RISC-V target with vectors, so the only testing that this patch has had has been done using 'set tdesc filename ....' to load a target description to which I have manually added the vector feature. This has shown that the vector register feature can be successfully parsed, and that the registers show up in the expected register groups. Additionally, the RISC-V vector extension is currently at v0.10, which is also the v1.0 draft release. However, this extension is not yet finalised. It is possible (but unlikely I think) that the register set could change between now and the final release of the vector extension. If this were to happen then we would potentially end up changing the requirements for the new org.gnu.gdb.riscv.vector feature. I really don't think it is likely that the register set will change this late in the process, and even if it did, changing the feature requirements will not be a problem as far as I am concerned (when the alternative is GDB just continues without this feature for now). gdb/ChangeLog: * NEWS: Mention new target feature name. * arch/riscv.c (riscv_create_target_description): GDB doesn't currently create target descriptions containing vector registers. * arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member variable. <operator==>: Also compare vlen. <hash>: Also include vlen. * riscv-tdep.c (riscv_feature_name_vector): New static global. (struct riscv_vector_feature): New struct. (riscv_vector_feature): New static global. (riscv_register_reggroup_p): Ensure vector registers are part of the 'all' group, and part of the 'vector' group. (riscv_dwarf_reg_to_regnum): Handle vector registers. (riscv_gdbarch_init): Check vector register feature. * riscv-tdep.h: Add vector registers to GDB's internal register numbers, and to the DWARF register numbers. gdb/doc/ChangeLog: * gdb.texinfo (RISC-V Features): Mention vector register feature.
2021-05-04 18:41:09 +08:00
/* Currently GDB only supports vector features coming from remote
targets. We don't support creating vector features on native targets
(yet). */
if (features.vlen != 0)
error (_("unable to create vector feature"));
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
return tdesc;
}
#ifndef GDBSERVER
/* Wrapper used by std::unordered_map to generate hash for feature set. */
struct riscv_gdbarch_features_hasher
{
std::size_t
operator() (const riscv_gdbarch_features &features) const noexcept
{
return features.hash ();
}
};
/* Cache of previously seen target descriptions, indexed by the feature set
that created them. */
static std::unordered_map<riscv_gdbarch_features,
gdb/riscv: delete target descriptions when gdb exits It was pointed out on IRC that the RISC-V target allocates target descriptions and stores them in a global map, and doesn't delete these target descriptions when GDB shuts down. This isn't a particular problem, the total number of target descriptions we can create is very limited so creating these on demand and holding them for the entire run on GDB seems reasonable. However, not deleting these objects on GDB exit means extra warnings are printed from tools like valgrind, and the address sanitiser, making it harder to spot real issues. As it's reasonably easy to have GDB correctly delete these objects on exit, lets just do that. I started by noticing that we already have a target_desc_up type, a wrapper around unique_ptr that calls a function that will correctly delete target descriptions, so I want to use that, but.... ...that type is declared in gdb/target-descriptions.h. If I try to include that file in gdb/arch/riscv.c I run into a problem, that file is compiled into both GDB and GDBServer. OK, I could guard the include with #ifdef, but surely we can do better. So then I decided to move the target_desc_up type into gdbsupport/tdesc.h, this is the interface file for generic code shared between GDB and GDBserver (relating to target descriptions). The actual implementation for the delete function still lives in gdb/target-description.c, but now gdb/arch/riscv.c can see the declaration. Problem solved.... ... but, though RISC-V doesn't use it I've now exposed the target_desc_up type to gdbserver, so in future someone _might_ start using it, which is fine, except right now there's no definition of the delete function - remember the delete I used is only defined in GDB code. No problem, I add an implementation of the delete operator into gdbserver/tdesc.cc, and all is good..... except.... I start getting this error from GCC: tdesc.cc:109:10: error: deleting object of polymorphic class type ‘target_desc’ which has non-virtual destructor might cause undefined behavior [-Werror=delete-non-virtual-dtor] Which is caused because gdbserver's target_desc type inherits from tdesc_element which has a virtual method, and so GCC worries that target_desc might be used as a base class. The solution is to declare gdbserver's target_desc class as final. This is fine so long as we never intent to inherit from target_desc (in gdbserver). But if we did then we'd want to make target_desc's destructor virtual anyway, so the error above would be resolved, and there wouldn't be an issue. gdb/ChangeLog: * arch/riscv.c (riscv_tdesc_cache): Change map type. (riscv_lookup_target_description): Return pointer out of unique_ptr. * target-descriptions.c (allocate_target_description): Add comment. (target_desc_deleter::operator()): Likewise. * target-descriptions.h (struct target_desc_deleter): Moved to gdbsupport/tdesc.h. (target_desc_up): Likewise. gdbserver/ChangeLog: * tdesc.cc (allocate_target_description): Add header comment. (target_desc_deleter::operator()): New function. * tdesc.h (struct target_desc): Declare as final. gdbsupport/ChangeLog: * tdesc.h (struct target_desc_deleter): Moved here from gdb/target-descriptions.h, extend comment. (target_desc_up): Likewise.
2020-07-17 00:48:12 +08:00
const target_desc_up,
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
riscv_gdbarch_features_hasher> riscv_tdesc_cache;
/* See arch/riscv.h. */
const target_desc *
riscv_lookup_target_description (const struct riscv_gdbarch_features features)
{
gdb/riscv: delete target descriptions when gdb exits It was pointed out on IRC that the RISC-V target allocates target descriptions and stores them in a global map, and doesn't delete these target descriptions when GDB shuts down. This isn't a particular problem, the total number of target descriptions we can create is very limited so creating these on demand and holding them for the entire run on GDB seems reasonable. However, not deleting these objects on GDB exit means extra warnings are printed from tools like valgrind, and the address sanitiser, making it harder to spot real issues. As it's reasonably easy to have GDB correctly delete these objects on exit, lets just do that. I started by noticing that we already have a target_desc_up type, a wrapper around unique_ptr that calls a function that will correctly delete target descriptions, so I want to use that, but.... ...that type is declared in gdb/target-descriptions.h. If I try to include that file in gdb/arch/riscv.c I run into a problem, that file is compiled into both GDB and GDBServer. OK, I could guard the include with #ifdef, but surely we can do better. So then I decided to move the target_desc_up type into gdbsupport/tdesc.h, this is the interface file for generic code shared between GDB and GDBserver (relating to target descriptions). The actual implementation for the delete function still lives in gdb/target-description.c, but now gdb/arch/riscv.c can see the declaration. Problem solved.... ... but, though RISC-V doesn't use it I've now exposed the target_desc_up type to gdbserver, so in future someone _might_ start using it, which is fine, except right now there's no definition of the delete function - remember the delete I used is only defined in GDB code. No problem, I add an implementation of the delete operator into gdbserver/tdesc.cc, and all is good..... except.... I start getting this error from GCC: tdesc.cc:109:10: error: deleting object of polymorphic class type ‘target_desc’ which has non-virtual destructor might cause undefined behavior [-Werror=delete-non-virtual-dtor] Which is caused because gdbserver's target_desc type inherits from tdesc_element which has a virtual method, and so GCC worries that target_desc might be used as a base class. The solution is to declare gdbserver's target_desc class as final. This is fine so long as we never intent to inherit from target_desc (in gdbserver). But if we did then we'd want to make target_desc's destructor virtual anyway, so the error above would be resolved, and there wouldn't be an issue. gdb/ChangeLog: * arch/riscv.c (riscv_tdesc_cache): Change map type. (riscv_lookup_target_description): Return pointer out of unique_ptr. * target-descriptions.c (allocate_target_description): Add comment. (target_desc_deleter::operator()): Likewise. * target-descriptions.h (struct target_desc_deleter): Moved to gdbsupport/tdesc.h. (target_desc_up): Likewise. gdbserver/ChangeLog: * tdesc.cc (allocate_target_description): Add header comment. (target_desc_deleter::operator()): New function. * tdesc.h (struct target_desc): Declare as final. gdbsupport/ChangeLog: * tdesc.h (struct target_desc_deleter): Moved here from gdb/target-descriptions.h, extend comment. (target_desc_up): Likewise.
2020-07-17 00:48:12 +08:00
/* Lookup in the cache. If we find it then return the pointer out of
the target_desc_up (which is a unique_ptr). This is safe as the
riscv_tdesc_cache will exist until GDB exits. */
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
const auto it = riscv_tdesc_cache.find (features);
if (it != riscv_tdesc_cache.end ())
gdb/riscv: delete target descriptions when gdb exits It was pointed out on IRC that the RISC-V target allocates target descriptions and stores them in a global map, and doesn't delete these target descriptions when GDB shuts down. This isn't a particular problem, the total number of target descriptions we can create is very limited so creating these on demand and holding them for the entire run on GDB seems reasonable. However, not deleting these objects on GDB exit means extra warnings are printed from tools like valgrind, and the address sanitiser, making it harder to spot real issues. As it's reasonably easy to have GDB correctly delete these objects on exit, lets just do that. I started by noticing that we already have a target_desc_up type, a wrapper around unique_ptr that calls a function that will correctly delete target descriptions, so I want to use that, but.... ...that type is declared in gdb/target-descriptions.h. If I try to include that file in gdb/arch/riscv.c I run into a problem, that file is compiled into both GDB and GDBServer. OK, I could guard the include with #ifdef, but surely we can do better. So then I decided to move the target_desc_up type into gdbsupport/tdesc.h, this is the interface file for generic code shared between GDB and GDBserver (relating to target descriptions). The actual implementation for the delete function still lives in gdb/target-description.c, but now gdb/arch/riscv.c can see the declaration. Problem solved.... ... but, though RISC-V doesn't use it I've now exposed the target_desc_up type to gdbserver, so in future someone _might_ start using it, which is fine, except right now there's no definition of the delete function - remember the delete I used is only defined in GDB code. No problem, I add an implementation of the delete operator into gdbserver/tdesc.cc, and all is good..... except.... I start getting this error from GCC: tdesc.cc:109:10: error: deleting object of polymorphic class type ‘target_desc’ which has non-virtual destructor might cause undefined behavior [-Werror=delete-non-virtual-dtor] Which is caused because gdbserver's target_desc type inherits from tdesc_element which has a virtual method, and so GCC worries that target_desc might be used as a base class. The solution is to declare gdbserver's target_desc class as final. This is fine so long as we never intent to inherit from target_desc (in gdbserver). But if we did then we'd want to make target_desc's destructor virtual anyway, so the error above would be resolved, and there wouldn't be an issue. gdb/ChangeLog: * arch/riscv.c (riscv_tdesc_cache): Change map type. (riscv_lookup_target_description): Return pointer out of unique_ptr. * target-descriptions.c (allocate_target_description): Add comment. (target_desc_deleter::operator()): Likewise. * target-descriptions.h (struct target_desc_deleter): Moved to gdbsupport/tdesc.h. (target_desc_up): Likewise. gdbserver/ChangeLog: * tdesc.cc (allocate_target_description): Add header comment. (target_desc_deleter::operator()): New function. * tdesc.h (struct target_desc): Declare as final. gdbsupport/ChangeLog: * tdesc.h (struct target_desc_deleter): Moved here from gdb/target-descriptions.h, extend comment. (target_desc_up): Likewise.
2020-07-17 00:48:12 +08:00
return it->second.get ();
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
target_desc_up tdesc (riscv_create_target_description (features));
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
gdb: Have allocate_target_description return a unique_ptr Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type.
2020-07-20 21:18:04 +08:00
/* Add to the cache, and return a pointer borrowed from the
target_desc_up. This is safe as the cache (and the pointers
contained within it) are not deleted until GDB exits. */
target_desc *ptr = tdesc.get ();
riscv_tdesc_cache.emplace (features, std::move (tdesc));
return ptr;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 23:10:52 +08:00
}
gdb/riscv: Update API for looking up target descriptions In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description.
2020-02-19 09:24:37 +08:00
#endif /* !GDBSERVER */