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90 lines
1.5 KiB
ArmAsm
90 lines
1.5 KiB
ArmAsm
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//Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
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// Spec Reference: ldimmhalf dreg lo
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS -1;
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// test Dreg
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R0.L = 0x0001;
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R1.L = 0x0003;
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R2.L = 0x0005;
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R3.L = 0x0007;
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R4.L = 0x0009;
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R5.L = 0x000b;
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R6.L = 0x000d;
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R7.L = 0x000f;
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CHECKREG r0, 0xFFFF0001;
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CHECKREG r1, 0xFFFF0003;
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CHECKREG r2, 0xFFFF0005;
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CHECKREG r3, 0xFFFF0007;
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CHECKREG r4, 0xFFFF0009;
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CHECKREG r5, 0xFFFF000b;
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CHECKREG r6, 0xFFFF000D;
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CHECKREG r7, 0xFFFF000F;
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R0.L = 0x0020;
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R1.L = 0x0040;
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R2.L = 0x0060;
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R3.L = 0x0080;
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R4.L = 0x00a0;
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R5.L = 0x00b0;
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R6.L = 0x00c0;
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R7.L = 0x00d0;
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CHECKREG r0, 0xFFFF0020;
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CHECKREG r1, 0xFFFF0040;
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CHECKREG r2, 0xFFFF0060;
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CHECKREG r3, 0xFFFF0080;
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CHECKREG r4, 0xFFFF00a0;
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CHECKREG r5, 0xFFFF00b0;
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CHECKREG r6, 0xFFFF00c0;
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CHECKREG r7, 0xFFFF00d0;
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R0.L = 0x0100;
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R1.L = 0x0200;
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R2.L = 0x0300;
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R3.L = 0x0400;
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R4.L = 0x0500;
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R5.L = 0x0600;
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R6.L = 0x0700;
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R7.L = 0x0800;
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CHECKREG r0, 0xFFFF0100;
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CHECKREG r1, 0xFFFF0200;
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CHECKREG r2, 0xFFFF0300;
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CHECKREG r3, 0xFFFF0400;
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CHECKREG r4, 0xFFFF0500;
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CHECKREG r5, 0xFFFF0600;
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CHECKREG r6, 0xFFFF0700;
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CHECKREG r7, 0xFFFF0800;
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R0 = 0;
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R1 = 0;
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R2 = 0;
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R3 = 0;
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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R0.L = 0x7fff;
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R1.L = 0x7ffe;
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R2.L = -32768;
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R3.L = -32767;
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R4.L = 32767;
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R5.L = 32766;
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R6.L = 32765;
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R7.L = 32764;
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CHECKREG r0, 0x00007fff;
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CHECKREG r1, 0x00007ffe;
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CHECKREG r2, 0x00008000;
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CHECKREG r3, 0x00008001;
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CHECKREG r4, 0x00007FFF;
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CHECKREG r5, 0x00007FFE;
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CHECKREG r6, 0x00007FFD;
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CHECKREG r7, 0x00007FFC;
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pass
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