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325 lines
8.7 KiB
Plaintext
325 lines
8.7 KiB
Plaintext
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/* IQ2000 opcode support. -*- C -*-
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Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
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Contributed by Red Hat Inc; developed under contract from Fujitsu.
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This file is part of the GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* This file is an addendum to iq2000.cpu. Heavy use of C code isn't
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appropriate in .cpu files, so it resides here. This especially applies
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to assembly/disassembly where parsing/printing can be quite involved.
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Such things aren't really part of the specification of the cpu, per se,
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so .cpu files provide the general framework and .opc files handle the
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nitty-gritty details as necessary.
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Each section is delimited with start and end markers.
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<arch>-opc.h additions use: "-- opc.h"
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<arch>-opc.c additions use: "-- opc.c"
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<arch>-asm.c additions use: "-- asm.c"
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<arch>-dis.c additions use: "-- dis.c"
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<arch>-ibd.h additions use: "-- ibd.h"
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*/
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/* -- opc.h */
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/* Allows reason codes to be output when assembler errors occur. */
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#define CGEN_VERBOSE_ASSEMBLER_ERRORS
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/* Override disassembly hashing - there are variable bits in the top
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byte of these instructions. */
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#define CGEN_DIS_HASH_SIZE 8
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#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
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/* following activates check beyond hashing since some iq2000 and iq10
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instructions have same mnemonics but different functionality. */
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#define CGEN_VALIDATE_INSN_SUPPORTED
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extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, CGEN_INSN *insn);
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/* -- asm.c */
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static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
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static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
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static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
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static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
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/* Special check to ensure that instruction exists for given machine */
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int
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iq2000_cgen_insn_supported (cd, insn)
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CGEN_CPU_DESC cd;
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CGEN_INSN *insn;
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{
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int machs = cd->machs;
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return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0);
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}
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static int iq2000_cgen_isa_register (strp)
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const char **strp;
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{
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int len;
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int ch1, ch2;
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if (**strp == 'r' || **strp == 'R')
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{
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len = strlen (*strp);
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if (len == 2)
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{
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ch1 = (*strp)[1];
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if ('0' <= ch1 && ch1 <= '9')
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return 1;
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}
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else if (len == 3)
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{
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ch1 = (*strp)[1];
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ch2 = (*strp)[2];
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if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9'))
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return 1;
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if ('3' == ch1 && (ch2 == '0' || ch2 == '1'))
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return 1;
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}
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}
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if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h')
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return 1;
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return 0;
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}
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/* Handle negated literal. */
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static const char *
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parse_mimm (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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long *valuep;
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{
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const char *errmsg;
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long value;
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/* Verify this isn't a register */
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if (iq2000_cgen_isa_register (strp))
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errmsg = _("immediate value cannot be register");
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else
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{
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long value;
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errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
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if (errmsg == NULL)
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{
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long x = (-value) & 0xFFFF0000;
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if (x != 0 && x != 0xFFFF0000)
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errmsg = _("immediate value out of range");
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else
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*valuep = (-value & 0xFFFF);
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}
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}
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return errmsg;
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}
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/* Handle signed/unsigned literal. */
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static const char *
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parse_imm (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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const char *errmsg;
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long value;
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if (iq2000_cgen_isa_register (strp))
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errmsg = _("immediate value cannot be register");
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else
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{
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long value;
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errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
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if (errmsg == NULL)
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{
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long x = value & 0xFFFF0000;
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if (x != 0 && x != 0xFFFF0000)
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errmsg = _("immediate value out of range");
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else
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*valuep = (value & 0xFFFF);
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}
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}
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return errmsg;
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}
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/* Handle iq10 21-bit jmp offset. */
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static const char *
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parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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int reloc;
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enum cgen_parse_operand_result *type_addr;
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unsigned long *valuep;
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{
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const char *errmsg;
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bfd_vma value;
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enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
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&result_type, &value);
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if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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{
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/* check value is within 23-bits (remembering that 2-bit shift right will occur) */
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if (value > 0x7fffff)
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return _("21-bit offset out of range");
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}
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*valuep = (value & 0x7FFFFF);
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return errmsg;
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}
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/* Handle high(). */
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static const char *
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parse_hi16 (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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unsigned long *valuep;
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{
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if (strncasecmp (*strp, "%hi(", 4) == 0)
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{
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enum cgen_parse_operand_result result_type;
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bfd_vma value;
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const char *errmsg;
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*strp += 4;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
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&result_type, &value);
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if (**strp != ')')
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return _("missing `)'");
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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{
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/* if value has top-bit of %lo on, then it will
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sign-propagate and so we compensate by adding
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1 to the resultant %hi value */
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if (value & 0x8000)
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value += 0x10000;
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value >>= 16;
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}
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*valuep = value;
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return errmsg;
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}
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/* we add %uhi in case a user just wants the high 16-bits or is using
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an insn like ori for %lo which does not sign-propagate */
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if (strncasecmp (*strp, "%uhi(", 5) == 0)
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{
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enum cgen_parse_operand_result result_type;
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bfd_vma value;
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const char *errmsg;
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*strp += 5;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
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&result_type, &value);
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if (**strp != ')')
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return _("missing `)'");
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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{
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value >>= 16;
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}
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*valuep = value;
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return errmsg;
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}
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return parse_imm (cd, strp, opindex, valuep);
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}
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/* Handle %lo in a signed context.
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The signedness of the value doesn't matter to %lo(), but this also
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handles the case where %lo() isn't present. */
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static const char *
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parse_lo16 (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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long *valuep;
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{
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if (strncasecmp (*strp, "%lo(", 4) == 0)
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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bfd_vma value;
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*strp += 4;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
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&result_type, &value);
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if (**strp != ')')
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return _("missing `)'");
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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value &= 0xffff;
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*valuep = value;
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return errmsg;
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}
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return parse_imm (cd, strp, opindex, valuep);
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}
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/* Handle %lo in a negated signed context.
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The signedness of the value doesn't matter to %lo(), but this also
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handles the case where %lo() isn't present. */
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static const char *
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parse_mlo16 (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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long *valuep;
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{
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if (strncasecmp (*strp, "%lo(", 4) == 0)
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{
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const char *errmsg;
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enum cgen_parse_operand_result result_type;
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bfd_vma value;
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*strp += 4;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
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&result_type, &value);
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if (**strp != ')')
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return _("missing `)'");
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++*strp;
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if (errmsg == NULL
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&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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value = (-value) & 0xffff;
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*valuep = value;
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return errmsg;
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}
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return parse_mimm (cd, strp, opindex, valuep);
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}
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/* -- */
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