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62 lines
958 B
ArmAsm
62 lines
958 B
ArmAsm
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//Original:/testcases/core/c_dsp32alu_awx/c_dsp32alu_awx.dsp
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// Spec Reference: dsp32alu awx
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x15678911;
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imm32 r1, 0x2789ab1d;
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imm32 r2, 0x34445515;
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imm32 r3, 0x46667717;
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imm32 r4, 0x5567891b;
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imm32 r5, 0x6789ab1d;
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imm32 r6, 0x74445515;
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imm32 r7, 0x86667777;
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// A0 & A1 types
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A0 = 0;
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A1 = 0;
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A0.L = R0.L;
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A0.H = R0.H;
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A0.x = R2.L;
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R3 = A0.w;
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R4 = A1.w;
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R5.L = A0.x;
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//rl6 = a1x;
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CHECKREG r3, 0x15678911;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x67890015;
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//CHECKREG r6, 0x74440000;
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R5 = ( A0 += A1 );
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R6.L = ( A0 += A1 );
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R7.H = ( A0 += A1 );
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CHECKREG r5, 0x7FFFFFFF;
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CHECKREG r6, 0x74447FFF;
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CHECKREG r7, 0x7FFF7777;
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A0 += A1;
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R0 = A0.w;
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CHECKREG r0, 0x15678911;
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A0 -= A1;
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R1 = A0.w;
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CHECKREG r1, 0x15678911;
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R2 = A1.L + A1.H, R3 = A0.L + A0.H; /* 0x */
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0xFFFF9E78;
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A0 = A1;
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R4 = A0.w;
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R5 = A1.w;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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pass
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