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binutils-gdb/sim/riscv/sim-main.c

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sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* RISC-V simulator.
Update copyright year range in header of all files managed by GDB This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
2023-01-01 20:49:04 +08:00
Copyright (C) 2005-2023 Free Software Foundation, Inc.
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
Contributed by Mike Frysinger.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file contains the main simulator decoding logic. i.e. everything that
is architecture specific. */
sim: switch config.h usage to defs.h The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
2021-05-02 06:05:23 +08:00
/* This must come before any other includes. */
#include "defs.h"
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
#include <inttypes.h>
#include <time.h>
#include "sim-main.h"
sim: split sim-signal.h include out The sim-basics.h is too big and includes too many things. This leads to some arch's sim-main.h having circular loop issues with defs, and makes it hard to separate out common objects from arch-specific defs. By splitting up sim-basics.h and killing off sim-main.h, it'll make it easier to separate out the two.
2021-06-14 11:16:32 +08:00
#include "sim-signal.h"
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
#include "sim-syscall.h"
#include "opcode/riscv.h"
sim: move register headers into sim/ namespace [PR sim/29869] These headers define the register numbers for each port to implement the sim_fetch_register & sim_store_register interfaces. While gdb uses these, the APIs are part of the sim, not gdb. Move the headers out of the gdb/ include namespace and into sim/ instead.
2022-12-10 19:33:58 +08:00
#include "sim/sim-riscv.h"
sim: riscv: move arch-specific settings to internal header There's no need for these settings to be in sim-main.h which is shared with common/ sim code, so move it all out to a new header which only this port will include. We can also move the machs.h include out since the model logic was all generalized from compile-time to runtime last year.
2022-12-23 12:10:38 +08:00
#include "riscv-sim.h"
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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#define TRACE_REG(cpu, reg) \
TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \
sim: riscv: invert sim_cpu storage
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RISCV_SIM_CPU (cpu)->regs[reg])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : 0x7f))
#define RISCV_ASSERT_RV32(cpu, fmt, args...) \
do { \
if (RISCV_XLEN (cpu) != 32) \
{ \
SIM_DESC sd = CPU_STATE (cpu); \
TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \
sim: riscv: invert sim_cpu storage
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sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \
SIM_SIGILL); \
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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} \
} while (0)
#define RISCV_ASSERT_RV64(cpu, fmt, args...) \
do { \
if (RISCV_XLEN (cpu) != 64) \
{ \
SIM_DESC sd = CPU_STATE (cpu); \
TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \
sim: riscv: invert sim_cpu storage
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sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \
SIM_SIGILL); \
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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} \
} while (0)
static INLINE void
store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
{
sim: riscv: invert sim_cpu storage
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struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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if (rd)
{
sim: riscv: invert sim_cpu storage
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riscv_cpu->regs[rd] = val;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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TRACE_REG (cpu, rd);
}
}
static INLINE unsigned_word
fetch_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg)
{
/* Handle pseudo registers. */
switch (csr)
{
/* Allow certain registers only in respective modes. */
case CSR_CYCLEH:
case CSR_INSTRETH:
case CSR_TIMEH:
RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
break;
}
return *reg;
}
static INLINE void
store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
unsigned_word val)
{
sim: riscv: invert sim_cpu storage
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struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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switch (csr)
{
/* These are pseudo registers that modify sub-fields of fcsr. */
case CSR_FRM:
val &= 0x7;
*reg = val;
sim: riscv: invert sim_cpu storage
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riscv_cpu->csr.fcsr = (riscv_cpu->csr.fcsr & ~0xe0) | (val << 5);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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break;
case CSR_FFLAGS:
val &= 0x1f;
*reg = val;
sim: riscv: invert sim_cpu storage
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riscv_cpu->csr.fcsr = (riscv_cpu->csr.fcsr & ~0x1f) | val;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
/* Keep the sub-fields in sync. */
case CSR_FCSR:
*reg = val;
sim: riscv: invert sim_cpu storage
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riscv_cpu->csr.frm = (val >> 5) & 0x7;
riscv_cpu->csr.fflags = val & 0x1f;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
/* Allow certain registers only in respective modes. */
case CSR_CYCLEH:
case CSR_INSTRETH:
case CSR_TIMEH:
RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
/* All the rest are immutable. */
default:
val = *reg;
break;
}
TRACE_REGISTER (cpu, "wrote CSR %s = %#" PRIxTW, name, val);
}
static inline unsigned_word
ashiftrt (unsigned_word val, unsigned_word shift)
{
sim: riscv: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2021-12-06 15:10:27 +08:00
uint32_t sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
return (val >> shift) | sign;
}
static inline unsigned_word
ashiftrt64 (unsigned_word val, unsigned_word shift)
{
sim: riscv: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2021-12-06 15:10:27 +08:00
uint64_t sign =
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
(val & 0x8000000000000000ull) ? ~(0xffffffffffffffffull >> shift) : 0;
return (val >> shift) | sign;
}
static sim_cia
execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
SIM_DESC sd = CPU_STATE (cpu);
sim: riscv: invert sim_cpu storage
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struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_name = riscv_gpr_names_abi[rs1];
const char *rs2_name = riscv_gpr_names_abi[rs2];
unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
sim: riscv: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2021-12-06 15:10:27 +08:00
unsigned_word u_imm = EXTRACT_UTYPE_IMM ((uint64_t) iw);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-01-26 18:02:38 +08:00
unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
unsigned_word tmp;
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_cia pc = riscv_cpu->pc + 4;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_EXTRACT (cpu,
"rd:%-2i:%-4s "
"rs1:%-2i:%-4s %0*" PRIxTW " "
"rs2:%-2i:%-4s %0*" PRIxTW " "
"match:%#x mask:%#x",
rd, rd_name,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
rs1, rs1_name, (int) sizeof (unsigned_word) * 2,
riscv_cpu->regs[rs1],
rs2, rs2_name, (int) sizeof (unsigned_word) * 2,
riscv_cpu->regs[rs2],
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
(unsigned) op->match, (unsigned) op->mask);
switch (op->match)
{
case MATCH_ADD:
TRACE_INSN (cpu, "add %s, %s, %s; // %s = %s + %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_ADDW:
TRACE_INSN (cpu, "addw %s, %s, %s; // %s = %s + %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_ADDI:
TRACE_INSN (cpu, "addi %s, %s, %#" PRIxTW "; // %s = %s + %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_ADDIW:
TRACE_INSN (cpu, "addiw %s, %s, %#" PRIxTW "; // %s = %s + %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AND:
TRACE_INSN (cpu, "and %s, %s, %s; // %s = %s & %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_ANDI:
TRACE_INSN (cpu, "andi %s, %s, %" PRIiTW "; // %s = %s & %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] & i_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_OR:
TRACE_INSN (cpu, "or %s, %s, %s; // %s = %s | %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] | riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_ORI:
TRACE_INSN (cpu, "ori %s, %s, %" PRIiTW "; // %s = %s | %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] | i_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_XOR:
TRACE_INSN (cpu, "xor %s, %s, %s; // %s = %s ^ %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_XORI:
TRACE_INSN (cpu, "xori %s, %s, %" PRIiTW "; // %s = %s ^ %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ i_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SUB:
TRACE_INSN (cpu, "sub %s, %s, %s; // %s = %s - %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SUBW:
TRACE_INSN (cpu, "subw %s, %s, %s; // %s = %s - %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
EXTEND32 (riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LUI:
TRACE_INSN (cpu, "lui %s, %#" PRIxTW ";", rd_name, u_imm);
store_rd (cpu, rd, u_imm);
break;
case MATCH_SLL:
TRACE_INSN (cpu, "sll %s, %s, %s; // %s = %s << %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
u_imm = RISCV_XLEN (cpu) == 32 ? 0x1f : 0x3f;
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & u_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SLLW:
TRACE_INSN (cpu, "sllw %s, %s, %s; // %s = %s << %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
(uint32_t) riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & 0x1f)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SLLI:
TRACE_INSN (cpu, "slli %s, %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
store_rd (cpu, rd, riscv_cpu->regs[rs1] << shamt_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SLLIW:
TRACE_INSN (cpu, "slliw %s, %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] << shamt_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SRL:
TRACE_INSN (cpu, "srl %s, %s, %s; // %s = %s >> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
u_imm = RISCV_XLEN (cpu) == 32 ? 0x1f : 0x3f;
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & u_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SRLW:
TRACE_INSN (cpu, "srlw %s, %s, %s; // %s = %s >> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
(uint32_t) riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & 0x1f)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SRLI:
TRACE_INSN (cpu, "srli %s, %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
store_rd (cpu, rd, riscv_cpu->regs[rs1] >> shamt_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SRLIW:
TRACE_INSN (cpu, "srliw %s, %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] >> shamt_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SRA:
TRACE_INSN (cpu, "sra %s, %s, %s; // %s = %s >>> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = ashiftrt (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x1f);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = ashiftrt64 (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x3f);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, tmp);
break;
case MATCH_SRAW:
TRACE_INSN (cpu, "sraw %s, %s, %s; // %s = %s >>> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
ashiftrt ((int32_t) riscv_cpu->regs[rs1],
riscv_cpu->regs[rs2] & 0x1f)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SRAI:
TRACE_INSN (cpu, "srai %s, %s, %" PRIiTW "; // %s = %s >>> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
if (RISCV_XLEN (cpu) == 32)
{
if (shamt_imm > 0x1f)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
tmp = ashiftrt (riscv_cpu->regs[rs1], shamt_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
else
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = ashiftrt64 (riscv_cpu->regs[rs1], shamt_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, tmp);
break;
case MATCH_SRAIW:
TRACE_INSN (cpu, "sraiw %s, %s, %" PRIiTW "; // %s = %s >>> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
ashiftrt ((int32_t) riscv_cpu->regs[rs1], shamt_imm)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SLT:
TRACE_INSN (cpu, "slt");
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
!!((signed_word) riscv_cpu->regs[rs1] <
(signed_word) riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SLTU:
TRACE_INSN (cpu, "sltu");
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
(unsigned_word) riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SLTI:
TRACE_INSN (cpu, "slti");
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, !!((signed_word) riscv_cpu->regs[rs1] <
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
(signed_word) i_imm));
break;
case MATCH_SLTIU:
TRACE_INSN (cpu, "sltiu");
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
(unsigned_word) i_imm));
break;
case MATCH_AUIPC:
TRACE_INSN (cpu, "auipc %s, %" PRIiTW "; // %s = pc + %" PRIiTW,
rd_name, u_imm, rd_name, u_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->pc + u_imm);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_BEQ:
TRACE_INSN (cpu, "beq %s, %s, %#" PRIxTW "; "
"// if (%s == %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if (riscv_cpu->regs[rs1] == riscv_cpu->regs[rs2])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
pc = riscv_cpu->pc + sb_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BLT:
TRACE_INSN (cpu, "blt %s, %s, %#" PRIxTW "; "
"// if (%s < %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if ((signed_word) riscv_cpu->regs[rs1] <
(signed_word) riscv_cpu->regs[rs2])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
pc = riscv_cpu->pc + sb_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BLTU:
TRACE_INSN (cpu, "bltu %s, %s, %#" PRIxTW "; "
"// if (%s < %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if ((unsigned_word) riscv_cpu->regs[rs1] <
(unsigned_word) riscv_cpu->regs[rs2])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
pc = riscv_cpu->pc + sb_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BGE:
TRACE_INSN (cpu, "bge %s, %s, %#" PRIxTW "; "
"// if (%s >= %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if ((signed_word) riscv_cpu->regs[rs1] >=
(signed_word) riscv_cpu->regs[rs2])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
pc = riscv_cpu->pc + sb_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BGEU:
TRACE_INSN (cpu, "bgeu %s, %s, %#" PRIxTW "; "
"// if (%s >= %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if ((unsigned_word) riscv_cpu->regs[rs1] >=
(unsigned_word) riscv_cpu->regs[rs2])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
pc = riscv_cpu->pc + sb_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BNE:
TRACE_INSN (cpu, "bne %s, %s, %#" PRIxTW "; "
"// if (%s != %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if (riscv_cpu->regs[rs1] != riscv_cpu->regs[rs2])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
pc = riscv_cpu->pc + sb_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_JAL:
TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name,
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-01-26 18:02:38 +08:00
EXTRACT_JTYPE_IMM (iw));
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->pc + 4);
pc = riscv_cpu->pc + EXTRACT_JTYPE_IMM (iw);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
break;
case MATCH_JALR:
TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->pc + 4);
pc = riscv_cpu->regs[rs1] + i_imm;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
break;
case MATCH_LD:
TRACE_INSN (cpu, "ld %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LW:
TRACE_INSN (cpu, "lw %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd, EXTEND32 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LWU:
TRACE_INSN (cpu, "lwu %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LH:
TRACE_INSN (cpu, "lh %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd, EXTEND16 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_2 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LHU:
TRACE_INSN (cpu, "lbu %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_2 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LB:
TRACE_INSN (cpu, "lb %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd, EXTEND8 (
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_1 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm)));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_LBU:
TRACE_INSN (cpu, "lbu %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_1 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SD:
TRACE_INSN (cpu, "sd %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SW:
TRACE_INSN (cpu, "sw %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SH:
TRACE_INSN (cpu, "sh %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_write_unaligned_2 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_SB:
TRACE_INSN (cpu, "sb %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_write_unaligned_1 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_CSRRC:
TRACE_INSN (cpu, "csrrc");
switch (csr)
{
#define DECLARE_CSR(name, num, ...) \
case num: \
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, \
fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
riscv_cpu->csr.name & !riscv_cpu->regs[rs1]); \
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
case MATCH_CSRRS:
TRACE_INSN (cpu, "csrrs");
switch (csr)
{
#define DECLARE_CSR(name, num, ...) \
case num: \
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, \
fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
riscv_cpu->csr.name | riscv_cpu->regs[rs1]); \
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
case MATCH_CSRRW:
TRACE_INSN (cpu, "csrrw");
switch (csr)
{
#define DECLARE_CSR(name, num, ...) \
case num: \
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, \
fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
riscv_cpu->regs[rs1]); \
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
case MATCH_RDCYCLE:
TRACE_INSN (cpu, "rdcycle %s;", rd_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
fetch_csr (cpu, "cycle", CSR_CYCLE, &riscv_cpu->csr.cycle));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_RDCYCLEH:
TRACE_INSN (cpu, "rdcycleh %s;", rd_name);
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
fetch_csr (cpu, "cycleh", CSR_CYCLEH, &riscv_cpu->csr.cycleh));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_RDINSTRET:
TRACE_INSN (cpu, "rdinstret %s;", rd_name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
fetch_csr (cpu, "instret", CSR_INSTRET,
&riscv_cpu->csr.instret));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_RDINSTRETH:
TRACE_INSN (cpu, "rdinstreth %s;", rd_name);
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
fetch_csr (cpu, "instreth", CSR_INSTRETH,
&riscv_cpu->csr.instreth));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_RDTIME:
TRACE_INSN (cpu, "rdtime %s;", rd_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
fetch_csr (cpu, "time", CSR_TIME, &riscv_cpu->csr.time));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_RDTIMEH:
TRACE_INSN (cpu, "rdtimeh %s;", rd_name);
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd,
fetch_csr (cpu, "timeh", CSR_TIMEH, &riscv_cpu->csr.timeh));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_FENCE:
TRACE_INSN (cpu, "fence;");
break;
case MATCH_FENCE_I:
TRACE_INSN (cpu, "fence.i;");
break;
sim/riscv: Complete tidying up with SBREAK This commit removes SBREAK-related references on the simulator as it's renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1). sim/ChangeLog: * riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
2022-09-04 15:45:06 +08:00
case MATCH_EBREAK:
TRACE_INSN (cpu, "ebreak;");
/* GDB expects us to step over EBREAK. */
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc + 4, sim_stopped,
SIM_SIGTRAP);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_ECALL:
TRACE_INSN (cpu, "ecall;");
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
return pc;
}
sim: riscv: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2021-12-06 15:10:27 +08:00
static uint64_t
mulhu (uint64_t a, uint64_t b)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
sim: riscv: move __int128 check to configure
2021-05-16 11:50:33 +08:00
#ifdef HAVE___INT128
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
return ((__int128)a * b) >> 64;
#else
uint64_t t;
uint32_t y1, y2, y3;
uint64_t a0 = (uint32_t)a, a1 = a >> 32;
uint64_t b0 = (uint32_t)b, b1 = b >> 32;
t = a1*b0 + ((a0*b0) >> 32);
y1 = t;
y2 = t >> 32;
t = a0*b1 + y1;
y1 = t;
t = a1*b1 + y2 + (t >> 32);
y2 = t;
y3 = t >> 32;
return ((uint64_t)y3 << 32) | y2;
#endif
}
sim: riscv: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2021-12-06 15:10:27 +08:00
static uint64_t
mulh (int64_t a, int64_t b)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
int negate = (a < 0) != (b < 0);
uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
return negate ? ~res + (a * b == 0) : res;
}
sim: riscv: migrate to standard uintXX_t types Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2021-12-06 15:10:27 +08:00
static uint64_t
mulhsu (int64_t a, uint64_t b)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
int negate = a < 0;
uint64_t res = mulhu (a < 0 ? -a : a, b);
return negate ? ~res + (a * b == 0) : res;
}
static sim_cia
execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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SIM_DESC sd = CPU_STATE (cpu);
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_name = riscv_gpr_names_abi[rs1];
const char *rs2_name = riscv_gpr_names_abi[rs2];
unsigned_word tmp, dividend_max;
sim: riscv: invert sim_cpu storage
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sim_cia pc = riscv_cpu->pc + 4;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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dividend_max = -((unsigned_word) 1 << (WITH_TARGET_WORD_BITSIZE - 1));
switch (op->match)
{
case MATCH_DIV:
TRACE_INSN (cpu, "div %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
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if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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tmp = dividend_max;
sim: riscv: invert sim_cpu storage
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else if (riscv_cpu->regs[rs2])
tmp = (signed_word) riscv_cpu->regs[rs1] /
(signed_word) riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
tmp = -1;
store_rd (cpu, rd, tmp);
break;
case MATCH_DIVW:
TRACE_INSN (cpu, "divw %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
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if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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tmp = 1 << 31;
sim: riscv: invert sim_cpu storage
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else if (EXTEND32 (riscv_cpu->regs[rs2]))
tmp = EXTEND32 (riscv_cpu->regs[rs1]) / EXTEND32 (riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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else
tmp = -1;
store_rd (cpu, rd, EXTEND32 (tmp));
break;
case MATCH_DIVU:
TRACE_INSN (cpu, "divu %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
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if (riscv_cpu->regs[rs2])
store_rd (cpu, rd, (unsigned_word) riscv_cpu->regs[rs1]
/ (unsigned_word) riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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else
store_rd (cpu, rd, -1);
break;
case MATCH_DIVUW:
TRACE_INSN (cpu, "divuw %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
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if ((uint32_t) riscv_cpu->regs[rs2])
tmp = (uint32_t) riscv_cpu->regs[rs1] / (uint32_t) riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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else
tmp = -1;
store_rd (cpu, rd, EXTEND32 (tmp));
break;
case MATCH_MUL:
TRACE_INSN (cpu, "mul %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, riscv_cpu->regs[rs1] * riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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break;
case MATCH_MULW:
TRACE_INSN (cpu, "mulw %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, EXTEND32 ((int32_t) riscv_cpu->regs[rs1]
* (int32_t) riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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break;
case MATCH_MULH:
TRACE_INSN (cpu, "mulh %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd,
((int64_t)(signed_word) riscv_cpu->regs[rs1]
* (int64_t)(signed_word) riscv_cpu->regs[rs2]) >> 32);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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else
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, mulh (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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break;
case MATCH_MULHU:
TRACE_INSN (cpu, "mulhu %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, ((uint64_t)riscv_cpu->regs[rs1]
* (uint64_t)riscv_cpu->regs[rs2]) >> 32);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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else
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, mulhu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_MULHSU:
TRACE_INSN (cpu, "mulhsu %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, ((int64_t)(signed_word) riscv_cpu->regs[rs1]
* (uint64_t)riscv_cpu->regs[rs2]) >> 32);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
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store_rd (cpu, rd, mulhsu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_REM:
TRACE_INSN (cpu, "rem %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
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if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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tmp = 0;
sim: riscv: invert sim_cpu storage
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else if (riscv_cpu->regs[rs2])
tmp = (signed_word) riscv_cpu->regs[rs1]
% (signed_word) riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
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tmp = riscv_cpu->regs[rs1];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, tmp);
break;
case MATCH_REMW:
TRACE_INSN (cpu, "remw %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
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if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
tmp = 0;
sim: riscv: invert sim_cpu storage
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else if (EXTEND32 (riscv_cpu->regs[rs2]))
tmp = EXTEND32 (riscv_cpu->regs[rs1]) % EXTEND32 (riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
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tmp = riscv_cpu->regs[rs1];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, EXTEND32 (tmp));
break;
case MATCH_REMU:
TRACE_INSN (cpu, "remu %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if (riscv_cpu->regs[rs2])
store_rd (cpu, rd, riscv_cpu->regs[rs1] % riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
store_rd (cpu, rd, riscv_cpu->regs[rs1]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_REMUW:
TRACE_INSN (cpu, "remuw %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if ((uint32_t) riscv_cpu->regs[rs2])
tmp = (uint32_t) riscv_cpu->regs[rs1] % (uint32_t) riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
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tmp = riscv_cpu->regs[rs1];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, EXTEND32 (tmp));
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
return pc;
}
static sim_cia
execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
sim: riscv: invert sim_cpu storage
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struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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SIM_DESC sd = CPU_STATE (cpu);
sim: riscv: invert sim_state storage
2021-05-13 17:44:02 +08:00
struct riscv_sim_state *state = RISCV_SIM_STATE (sd);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_name = riscv_gpr_names_abi[rs1];
const char *rs2_name = riscv_gpr_names_abi[rs2];
struct atomic_mem_reserved_list *amo_prev, *amo_curr;
unsigned_word tmp;
sim: riscv: invert sim_cpu storage
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sim_cia pc = riscv_cpu->pc + 4;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* Handle these two load/store operations specifically. */
switch (op->match)
{
case MATCH_LR_W:
TRACE_INSN (cpu, "%s %s, (%s);", op->name, rd_name, rs1_name);
store_rd (cpu, rd,
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* Walk the reservation list to find an existing match. */
sim: riscv: invert sim_state storage
2021-05-13 17:44:02 +08:00
amo_curr = state->amo_reserved_list;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
while (amo_curr)
{
sim: riscv: invert sim_cpu storage
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if (amo_curr->addr == riscv_cpu->regs[rs1])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
goto done;
amo_curr = amo_curr->next;
}
/* No reservation exists, so add one. */
amo_curr = xmalloc (sizeof (*amo_curr));
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
amo_curr->addr = riscv_cpu->regs[rs1];
sim: riscv: invert sim_state storage
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amo_curr->next = state->amo_reserved_list;
state->amo_reserved_list = amo_curr;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
goto done;
case MATCH_SC_W:
TRACE_INSN (cpu, "%s %s, %s, (%s);", op->name, rd_name, rs2_name,
rs1_name);
/* Walk the reservation list to find a match. */
sim: riscv: invert sim_state storage
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amo_curr = amo_prev = state->amo_reserved_list;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
while (amo_curr)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
if (amo_curr->addr == riscv_cpu->regs[rs1])
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
/* We found a reservation, so operate it. */
sim: riscv: invert sim_cpu storage
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sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1],
riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, 0);
sim: riscv: invert sim_state storage
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if (amo_curr == state->amo_reserved_list)
state->amo_reserved_list = amo_curr->next;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
amo_prev->next = amo_curr->next;
free (amo_curr);
goto done;
}
amo_prev = amo_curr;
amo_curr = amo_curr->next;
}
/* If we're still here, then no reservation exists, so mark as failed. */
store_rd (cpu, rd, 1);
goto done;
}
/* Handle the rest of the atomic insns with common code paths. */
TRACE_INSN (cpu, "%s %s, %s, (%s);",
op->name, rd_name, rs2_name, rs1_name);
if (op->xlen_requirement == 64)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = EXTEND32 (sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1]));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
store_rd (cpu, rd, tmp);
switch (op->match)
{
case MATCH_AMOADD_D:
case MATCH_AMOADD_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = riscv_cpu->regs[rd] + riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOAND_D:
case MATCH_AMOAND_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = riscv_cpu->regs[rd] & riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOMAX_D:
case MATCH_AMOMAX_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = max ((signed_word) riscv_cpu->regs[rd],
(signed_word) riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOMAXU_D:
case MATCH_AMOMAXU_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = max ((unsigned_word) riscv_cpu->regs[rd],
(unsigned_word) riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOMIN_D:
case MATCH_AMOMIN_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = min ((signed_word) riscv_cpu->regs[rd],
(signed_word) riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOMINU_D:
case MATCH_AMOMINU_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = min ((unsigned_word) riscv_cpu->regs[rd],
(unsigned_word) riscv_cpu->regs[rs2]);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOOR_D:
case MATCH_AMOOR_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = riscv_cpu->regs[rd] | riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOSWAP_D:
case MATCH_AMOSWAP_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
case MATCH_AMOXOR_D:
case MATCH_AMOXOR_W:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
tmp = riscv_cpu->regs[rd] ^ riscv_cpu->regs[rs2];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
if (op->xlen_requirement == 64)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1], tmp);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
else
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1], tmp);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
done:
return pc;
}
static sim_cia
execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
SIM_DESC sd = CPU_STATE (cpu);
if (op->xlen_requirement == 32)
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
else if (op->xlen_requirement == 64)
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
switch (op->insn_class)
{
case INSN_CLASS_A:
return execute_a (cpu, iw, op);
case INSN_CLASS_I:
return execute_i (cpu, iw, op);
case INSN_CLASS_M:
sim/riscv: fix multiply instructions on simulator After this commit: commit 0938b032daa52129b4215d8e0eedb6c9804f5280 Date: Wed Feb 2 10:06:15 2022 +0900 RISC-V: Add 'Zmmul' extension in assembler. some instructions in the RISC-V simulator stopped working as a new instruction class 'INSN_CLASS_ZMMUL' was added, and some existing instructions were moved into this class. The simulator doesn't currently handle this instruction class, and so the instructions will now cause an illegal instruction trap. This commit adds support for INSN_CLASS_ZMMUL, and adds a test that ensures the affected instructions can be executed by the simulator. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Andrew Burgess <aburgess@redhat.com>
2022-08-31 09:46:08 +08:00
case INSN_CLASS_ZMMUL:
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
return execute_m (cpu, iw, op);
default:
TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
return riscv_cpu->pc + riscv_insn_length (iw);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
/* Decode & execute a single instruction. */
void step_once (SIM_CPU *cpu)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
SIM_DESC sd = CPU_STATE (cpu);
unsigned_word iw;
unsigned int len;
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
sim_cia pc = riscv_cpu->pc;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
const struct riscv_opcode *op;
int xlen = RISCV_XLEN (cpu);
if (TRACE_ANY_P (cpu))
trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
NULL, 0, " "); /* Use a space for gcc warnings. */
iw = sim_core_read_aligned_2 (cpu, pc, exec_map, pc);
/* Reject non-32-bit opcodes first. */
len = riscv_insn_length (iw);
if (len != 4)
{
sim_io_printf (sd, "sim: bad insn len %#x @ %#" PRIxTA ": %#" PRIxTW "\n",
len, pc, iw);
sim_engine_halt (sd, cpu, NULL, pc, sim_signalled, SIM_SIGILL);
}
iw |= ((unsigned_word) sim_core_read_aligned_2 (
cpu, pc, exec_map, pc + 2) << 16);
TRACE_CORE (cpu, "0x%08" PRIxTW, iw);
op = riscv_hash[OP_HASH_IDX (iw)];
if (!op)
sim_engine_halt (sd, cpu, NULL, pc, sim_signalled, SIM_SIGILL);
/* NB: Same loop logic as riscv_disassemble_insn. */
for (; op->name; op++)
{
/* Does the opcode match? */
if (! op->match_func (op, iw))
continue;
/* Is this a pseudo-instruction and may we print it as such? */
if (op->pinfo & INSN_ALIAS)
continue;
/* Is this instruction restricted to a certain value of XLEN? */
if (op->xlen_requirement != 0 && op->xlen_requirement != xlen)
continue;
/* It's a match. */
pc = execute_one (cpu, iw, op);
break;
}
/* TODO: Handle overflow into high 32 bits. */
/* TODO: Try to use a common counter and only update on demand (reads). */
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
++riscv_cpu->csr.cycle;
++riscv_cpu->csr.instret;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
riscv_cpu->pc = pc;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
/* Return the program counter for this cpu. */
static sim_cia
pc_get (sim_cpu *cpu)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
return riscv_cpu->pc;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
/* Set the program counter for this cpu to the new pc value. */
static void
pc_set (sim_cpu *cpu, sim_cia pc)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
riscv_cpu->pc = pc;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
}
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
static int
sim: common: change sim_{fetch,store}_register helpers to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31 23:58:10 +08:00
reg_fetch (sim_cpu *cpu, int rn, void *buf, int len)
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
if (len <= 0 || len > sizeof (unsigned_word))
return -1;
switch (rn)
{
case SIM_RISCV_ZERO_REGNUM:
memset (buf, 0, len);
return len;
case SIM_RISCV_RA_REGNUM ... SIM_RISCV_T6_REGNUM:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (buf, &riscv_cpu->regs[rn], len);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
case SIM_RISCV_FIRST_FP_REGNUM ... SIM_RISCV_LAST_FP_REGNUM:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (buf, &riscv_cpu->fpregs[rn - SIM_RISCV_FIRST_FP_REGNUM], len);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
case SIM_RISCV_PC_REGNUM:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (buf, &riscv_cpu->pc, len);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
#define DECLARE_CSR(name, num, ...) \
case SIM_RISCV_ ## num ## _REGNUM: \
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (buf, &riscv_cpu->csr.name, len); \
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
default:
return -1;
}
}
static int
sim: common: change sim_{fetch,store}_register helpers to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31 23:58:10 +08:00
reg_store (sim_cpu *cpu, int rn, const void *buf, int len)
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
if (len <= 0 || len > sizeof (unsigned_word))
return -1;
switch (rn)
{
case SIM_RISCV_ZERO_REGNUM:
/* Ignore writes. */
return len;
case SIM_RISCV_RA_REGNUM ... SIM_RISCV_T6_REGNUM:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (&riscv_cpu->regs[rn], buf, len);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
case SIM_RISCV_FIRST_FP_REGNUM ... SIM_RISCV_LAST_FP_REGNUM:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (&riscv_cpu->fpregs[rn - SIM_RISCV_FIRST_FP_REGNUM], buf, len);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
case SIM_RISCV_PC_REGNUM:
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (&riscv_cpu->pc, buf, len);
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
#define DECLARE_CSR(name, num, ...) \
case SIM_RISCV_ ## num ## _REGNUM: \
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memcpy (&riscv_cpu->csr.name, buf, len); \
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
return len;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
default:
return -1;
}
}
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* Initialize the state for a single cpu. Usuaully this involves clearing all
registers back to their reset state. Should also hook up the fetch/store
helper functions too. */
void
initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
{
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
const char *extensions;
int i;
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
memset (riscv_cpu->regs, 0, sizeof (riscv_cpu->regs));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
CPU_PC_FETCH (cpu) = pc_get;
CPU_PC_STORE (cpu) = pc_set;
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim".
2015-06-16 23:44:48 +08:00
CPU_REG_FETCH (cpu) = reg_fetch;
CPU_REG_STORE (cpu) = reg_store;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
if (!riscv_hash[0])
{
const struct riscv_opcode *op;
for (op = riscv_opcodes; op->name; op++)
if (!riscv_hash[OP_HASH_IDX (op->match)])
riscv_hash[OP_HASH_IDX (op->match)] = op;
}
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
riscv_cpu->csr.misa = 0;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* RV32 sets this field to 0, and we don't really support RV128 yet. */
if (RISCV_XLEN (cpu) == 64)
sim: riscv: invert sim_cpu storage
2022-11-01 14:15:34 +08:00
riscv_cpu->csr.misa |= (uint64_t)2 << 62;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* Skip the leading "rv" prefix and the two numbers. */
extensions = MODEL_NAME (CPU_MODEL (cpu)) + 4;
for (i = 0; i < 26; ++i)
{
char ext = 'A' + i;
if (ext == 'X')
continue;
else if (strchr (extensions, ext) != NULL)
{
if (ext == 'G')
sim: riscv: invert sim_cpu storage
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riscv_cpu->csr.misa |= 0x1129; /* G = IMAFD. */
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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else
sim: riscv: invert sim_cpu storage
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riscv_cpu->csr.misa |= (1 << i);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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}
}
sim: riscv: invert sim_cpu storage
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riscv_cpu->csr.mimpid = 0x8000;
riscv_cpu->csr.mhartid = mhartid;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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}
/* Some utils don't like having a NULL environ. */
static const char * const simple_env[] = { "HOME=/", "PATH=/bin", NULL };
/* Count the number of arguments in an argv. */
static int
count_argv (const char * const *argv)
{
int i;
if (!argv)
return -1;
for (i = 0; argv[i] != NULL; ++i)
continue;
return i;
}
void
initialize_env (SIM_DESC sd, const char * const *argv, const char * const *env)
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
sim: riscv: invert sim_cpu storage
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struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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int i;
int argc, argv_flat;
int envc, env_flat;
address_word sp, sp_flat;
unsigned char null[8] = { 0, 0, 0, 0, 0, 0, 0, 0, };
/* Figure out how many bytes the argv strings take up. */
argc = count_argv (argv);
if (argc == -1)
argc = 0;
argv_flat = argc; /* NUL bytes. */
for (i = 0; i < argc; ++i)
argv_flat += strlen (argv[i]);
/* Figure out how many bytes the environ strings take up. */
if (!env)
env = simple_env;
envc = count_argv (env);
env_flat = envc; /* NUL bytes. */
for (i = 0; i < envc; ++i)
env_flat += strlen (env[i]);
/* Make space for the strings themselves. */
sp_flat = (DEFAULT_MEM_SIZE - argv_flat - env_flat) & -sizeof (address_word);
/* Then the pointers to the strings. */
sp = sp_flat - ((argc + 1 + envc + 1) * sizeof (address_word));
/* Then the argc. */
sp -= sizeof (unsigned_word);
/* Set up the regs the libgloss crt0 expects. */
sim: riscv: invert sim_cpu storage
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riscv_cpu->a0 = argc;
riscv_cpu->sp = sp;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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/* First push the argc value. */
sim: common: change sim_read & sim_write to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
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sim_write (sd, sp, &argc, sizeof (unsigned_word));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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sp += sizeof (unsigned_word);
/* Then the actual argv strings so we know where to point argv[]. */
for (i = 0; i < argc; ++i)
{
unsigned len = strlen (argv[i]) + 1;
sim: common: change sim_read & sim_write to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
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sim_write (sd, sp_flat, argv[i], len);
sim_write (sd, sp, &sp_flat, sizeof (address_word));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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sp_flat += len;
sp += sizeof (address_word);
}
sim_write (sd, sp, null, sizeof (address_word));
sp += sizeof (address_word);
/* Then the actual env strings so we know where to point env[]. */
for (i = 0; i < envc; ++i)
{
unsigned len = strlen (env[i]) + 1;
sim: common: change sim_read & sim_write to use void* buffers When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
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sim_write (sd, sp_flat, env[i], len);
sim_write (sd, sp, &sp_flat, sizeof (address_word));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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sp_flat += len;
sp += sizeof (address_word);
}
}
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