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binutils-gdb/sim/aarch64/ChangeLog

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Add ldn/stn single support, fix ldnr support. sim/aarch64/ * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. (do_vec_LDn_single, do_vec_STn_single): New. (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with loop over nregs using new var n. Add n times size to address in loop. Add n to vd in loop. (do_vec_load_store): Add comment for instruction bit 24. New var single to hold instruction bit 24. Add new code to use single. Move ldnr support inside single if statements. Fix ldnr register counts inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. sim/testsuite/sim/aarch64/ * ldn_single.s: New. * ldnr.s: New. * stn_single.s: New.
2017-02-15 06:31:03 +08:00
2017-02-14 Jim Wilson <jim.wilson@linaro.org>
Add self to aarch64 maintainers. Fix mla instruction. sim/ * MAINTAINTERS (aarch64): Add myself. sim/aarch64/ * simulator.c (do_vec_MLA): Rewrite switch body. sim/testsuite/sim/aarch64/ * mla.s: New.
2017-02-15 07:23:12 +08:00
* simulator.c (do_vec_MLA): Rewrite switch body.
Fix bit/bif instructions. sim/aarch64/ * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. sim/testsuite/sim/aarch64 * bit.s: New.
2017-02-15 06:35:57 +08:00
* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
2. Move test_false if inside loop. Fix logic for computing result
stored to vd.
Add ldn/stn single support, fix ldnr support. sim/aarch64/ * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. (do_vec_LDn_single, do_vec_STn_single): New. (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with loop over nregs using new var n. Add n times size to address in loop. Add n to vd in loop. (do_vec_load_store): Add comment for instruction bit 24. New var single to hold instruction bit 24. Add new code to use single. Move ldnr support inside single if statements. Fix ldnr register counts inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. sim/testsuite/sim/aarch64/ * ldn_single.s: New. * ldnr.s: New. * stn_single.s: New.
2017-02-15 06:31:03 +08:00
* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
(do_vec_LDn_single, do_vec_STn_single): New.
(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
loop over nregs using new var n. Add n times size to address in loop.
Add n to vd in loop.
(do_vec_load_store): Add comment for instruction bit 24. New var
single to hold instruction bit 24. Add new code to use single. Move
ldnr support inside single if statements. Fix ldnr register counts
inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
Add support for cmtst. sim/aarch64/ * simulator.c (do_vec_compare): Add case 0x23 for CMTST. sim/testsuite/sim/aarch64/ * cmtst.s: New.
2017-01-24 09:26:53 +08:00
2017-01-23 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (do_vec_compare): Add case 0x23 for CMTST.
Fixes for addv and xtn2 instructions. sim/aarch64/ * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In case 3, call HALT_UNALLOC unconditionally. (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to i + 2. Delete if on bias, change index to i + bias * X. sim/testsuite/sim/aarch64/ * addv.s: New. * xtn.s: New.
2017-01-18 08:01:40 +08:00
2017-01-17 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
Fix problems with the implementation of the uzp1 and uzp2 instructions. sim/aarch64/ * simulator.c (do_vec_UZP): Rewrite. sim/testsuite/sim/aarch64/ * uzp.s: New.
2017-01-10 07:44:57 +08:00
2017-01-09 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (do_vec_UZP): Rewrite.
Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul. sim/aarch64/ * cpustate.c: Include math.h. (aarch64_set_FP_float): Use signbit to check for signed zero. (aarch64_set_FP_double): Likewise. * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. (fmaxnm): Use isnan instead of fpclassify. (fminnm, dmaxnm, dminnm): Likewise. (do_vec_MLS): Reverse order of subtraction operands. (dexSimpleFPCondSelect): Call aarch64_get_FP_double or aarch64_get_FP_float to get source register contents. (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in raise_exception calls. sim/testsuite/sim/aarch64/ * fcsel.s: New. * fcvtz.s: New. * fminnm.s: New. * mls.s: New. * mul.s: New.
2017-01-05 08:05:27 +08:00
2017-01-04 Jim Wilson <jim.wilson@linaro.org>
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
Fix bugs with float compare and Inf operands. sim/aarch64/ * simulator.c (set_flags_for_float_compare): Add code to handle Inf. Add comment to document NaN issue. (set_flags_for_double_compare): Likewise. sim/testsuite/sim/aarch64/ * fcmp.s: New.
2016-12-22 04:33:12 +08:00
2016-12-21 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
Add comment to document NaN issue.
(set_flags_for_double_compare): Likewise.
Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes. sim/aarch64 * simulator.c (NEG, POS): Move before set_flags_for_add64. (set_flags_for_add64): Replace with a modified copy of set_flags_for_sub64. sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass to start. (fail): Move .Lfail to start. Return 1 instead of 0. (start): Moved .Lpass and .Lfail to here. * adds.s: New. * fstur.s: New. * tbnz.s: New.
2016-12-14 00:35:31 +08:00
2016-12-13 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (NEG, POS): Move before set_flags_for_add64.
(set_flags_for_add64): Replace with a modified copy of
set_flags_for_sub64.
Fix bugs with tbnz/tbz instructions. sim/aarch64 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
2016-12-04 09:29:44 +08:00
2016-12-03 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
Fix bug with FP stur instructions. sim/aarch64 * simulator.c (fsturs): Switch use of rn and st variables. (fsturd, fsturq): Likewise
2016-12-02 01:06:07 +08:00
2016-12-01 Jim Wilson <jim.wilson@linaro.org>
Fix typo in ChangeLog entry.
2016-12-02 01:07:55 +08:00
* simulator.c (fsturs): Switch use of rn and st variables.
Fix bug with FP stur instructions. sim/aarch64 * simulator.c (fsturs): Switch use of rn and st variables. (fsturd, fsturq): Likewise
2016-12-02 01:06:07 +08:00
(fsturd, fsturq): Likewise
sim: unify symbol table handling The common sim tracing code already handles loading and tracking of symbols from the target program so that it can show symbol info in trace/disassembly calls. Once we touch up the trace code and add a few API callbacks, ports don't need to do loading and searching of symbol tables themselves anymore.
2016-01-22 11:17:59 +08:00
2016-08-15 Mike Frysinger <vapier@gentoo.org>
* interp.c: Include bfd.h.
(symcount, symtab, aarch64_get_sym_value): Delete.
(remove_useless_symbols): Change count type to long.
(aarch64_get_func): Add SIM_DESC to arg list. Add symcount
and symtab local variables.
(sim_create_inferior): Delete storage. Replace symbol code
with a call to trace_load_symbols.
* memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
includes.
(aarch64_get_heap_start): Change aarch64_get_sym_value to
trace_sym_value.
* memory.h: Delete bfd.h include.
(mem_add_blk): Delete unused prototype.
* simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
* simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
(aarch64_get_sym_value): Delete.
Undo the previous change to the aarch64 sim - exporting aarch64_step() - and instead make aarch64_run correctly process sim events. * simulator.c (aarch64_step): Revert pervious delta. (aarch64_run): Call sim_events_tick after each instruction is simulated, and if necessary call sim_events_process. * simulator.h: Revert previous delta.
2016-08-12 18:35:32 +08:00
2016-08-12 Nick Clifton <nickc@redhat.com>
* simulator.c (aarch64_step): Revert pervious delta.
(aarch64_run): Call sim_events_tick after each
instruction is simulated, and if necessary call
sim_events_process.
* simulator.h: Revert previous delta.
Export the single step function from the AArch64 simulator. * interp.c (sim_create_inferior): Allow for being called with a NULL abfd parameter. If a bfd is provided, initialise the sim with that start address. * simulator.c (HALT_NYI): Just print out the numeric value of the instruction when not tracing. (aarch64_step): Change from static to global. * simulator.h: Add a prototype for aarch64_step().
2016-08-11 22:04:40 +08:00
2016-08-11 Nick Clifton <nickc@redhat.com>
* interp.c (sim_create_inferior): Allow for being called with a
NULL abfd parameter. If a bfd is provided, initialise the sim
with that start address.
* simulator.c (HALT_NYI): Just print out the numeric value of the
instruction when not tracing.
Undo the previous change to the aarch64 sim - exporting aarch64_step() - and instead make aarch64_run correctly process sim events. * simulator.c (aarch64_step): Revert pervious delta. (aarch64_run): Call sim_events_tick after each instruction is simulated, and if necessary call sim_events_process. * simulator.h: Revert previous delta.
2016-08-12 18:35:32 +08:00
(aarch64_step): Change from static to global.
* simulator.h: Add a prototype for aarch64_step().
Export the single step function from the AArch64 simulator. * interp.c (sim_create_inferior): Allow for being called with a NULL abfd parameter. If a bfd is provided, initialise the sim with that start address. * simulator.c (HALT_NYI): Just print out the numeric value of the instruction when not tracing. (aarch64_step): Change from static to global. * simulator.h: Add a prototype for aarch64_step().
2016-08-11 22:04:40 +08:00
Wean gdb and sim off private libbfd.h header The major reason this header was needed, bfd_default_set_arch_mach, has now moved to bfd.h. gdb/ * amd64-darwin-tdep.c: Don't include libbfd.h. * i386-darwin-tdep.c: Likewise. * rs6000-nat.c: Likewise. * rs6000-tdep.c: Likewise. sim/aarch64/ * memory.c: Don't include libbfd.h. sim/rl78/ * load.c: Don't include libbfd.h. (rl78_load): Don't use private iovec seek or read. sim/rx/ * load.c: Don't include libbfd.h. (rx_load): Don't use private iovec seek or read.
2016-07-27 07:30:03 +08:00
2016-07-27 Alan Modra <amodra@gmail.com>
* memory.c: Don't include libbfd.h.
Use fsqrt() to calculate float (rather than double) square root. * simulator.c (fsqrts): Use fsqrt rather than sqrt.
2016-07-21 16:17:54 +08:00
2016-07-21 Nick Clifton <nickc@redhat.com>
Fix typo fsqrt -> sqrtf.
2016-07-21 16:23:16 +08:00
* simulator.c (fsqrts): Use sqrtf rather than sqrt.
Use fsqrt() to calculate float (rather than double) square root. * simulator.c (fsqrts): Use fsqrt rather than sqrt.
2016-07-21 16:17:54 +08:00
Add support for simulating big-endian AArch64 binaries. * cpustate.h: Include config.h. (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code use anonymous structs to align members. * simulator.c (aarch64_step): Use sim_core_read_buffer and endian_le2h_4 to read instruction from pc.
2016-06-30 16:10:41 +08:00
2016-06-30 Jim Wilson <jim.wilson@linaro.org>
* cpustate.h: Include config.h.
(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
use anonymous structs to align members.
* simulator.c (aarch64_step): Use sim_core_read_buffer and
endian_le2h_4 to read instruction from pc.
Add support for FMLA (by element) to AArch64 sim. * simulator.c (do_FMLA_by_element): New function. (do_vec_op2): Call it.
2016-05-06 17:35:33 +08:00
2016-05-06 Nick Clifton <nickc@redhat.com>
* simulator.c (do_FMLA_by_element): New function.
(do_vec_op2): Call it.
Add support for the --trace-decode option to the AArch64 simulator. * simulator.c: Add TRACE_DECODE statements to all emulation functions.
2016-04-27 18:39:14 +08:00
2016-04-27 Nick Clifton <nickc@redhat.com>
* simulator.c: Add TRACE_DECODE statements to all emulation
functions.
Fix more bugs in AArch64 simulator. * cpustate.c (aarch64_set_reg_s32): New function. (aarch64_set_reg_u32): New function. (aarch64_get_FP_half): Place half precision value into the correct slot of the union. (aarch64_set_FP_half): Likewise. * cpustate.h: Add prototypes for aarch64_set_reg_s32 and aarch64_set_reg_u32. * memory.c (FETCH_FUNC): Cast the read value to the access type before converting it to the return type. Rename to FETCH_FUNC64. (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit accesses. Use for 32-bit memory access functions. * simulator.c (ldrsb_wb): Use sign extension not zero extension. (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. (ldrsh_scale_ext, ldrsw_abs): Likewise. (ldrh32_abs): Store 32 bit value not 64-bits. (ldrh32_wb, ldrh32_scale_ext): Likewise. (do_vec_MOV_immediate): Fix computation of val. (do_vec_MVNI): Likewise. (DO_VEC_WIDENING_MUL): New macro. (do_vec_mull): Use new macro. (do_vec_mul): Use new macro. (do_vec_MLA): Read values before writing. (do_vec_xtl): Likewise. (do_vec_SSHL): Select correct shift value. (do_vec_USHL): Likewise. (do_scalar_UCVTF): New function. (do_scalar_vec): Call new function. (store_pair_u64): Treat reads of SP as reads of XZR.
2016-03-30 17:27:21 +08:00
2016-03-30 Nick Clifton <nickc@redhat.com>
* cpustate.c (aarch64_set_reg_s32): New function.
(aarch64_set_reg_u32): New function.
(aarch64_get_FP_half): Place half precision value into the correct
slot of the union.
(aarch64_set_FP_half): Likewise.
* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
aarch64_set_reg_u32.
* memory.c (FETCH_FUNC): Cast the read value to the access type
before converting it to the return type. Rename to FETCH_FUNC64.
(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
accesses. Use for 32-bit memory access functions.
* simulator.c (ldrsb_wb): Use sign extension not zero extension.
(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
(ldrsh_scale_ext, ldrsw_abs): Likewise.
(ldrh32_abs): Store 32 bit value not 64-bits.
(ldrh32_wb, ldrh32_scale_ext): Likewise.
(do_vec_MOV_immediate): Fix computation of val.
(do_vec_MVNI): Likewise.
(DO_VEC_WIDENING_MUL): New macro.
(do_vec_mull): Use new macro.
(do_vec_mul): Use new macro.
(do_vec_MLA): Read values before writing.
(do_vec_xtl): Likewise.
(do_vec_SSHL): Select correct shift value.
(do_vec_USHL): Likewise.
(do_scalar_UCVTF): New function.
(do_scalar_vec): Call new function.
(store_pair_u64): Treat reads of SP as reads of XZR.
Tidy up AArch64 simulator code. * cpustate.c: Remove space after asterisk in function parameters. * decode.h (greg): Delete unused function. (vreg, shift, extension, scaling, writeback, condcode): Likewise. * simulator.c: Use INSTR macro in more places. (HALT_NYI): Use sim_io_eprintf in place of fprintf. Remove extraneous whitespace.
2016-03-29 18:34:22 +08:00
2016-03-29 Nick Clifton <nickc@redhat.com>
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
More AArch64 simulator improvements. * cpustate.c (aarch64_get_FP_half): New function. Read a vector register as a half precision floating point number. (aarch64_set_FP_half): New function. Similar, but for setting a half precision register. (aarch64_get_thread_id): New function. Returns the value of the CPU's TPIDR register. (aarch64_get_FPCR): New function. Returns the value of the CPU's floating point control register. (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR register. * cpustate.h: Add prototypes for new functions. * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. * memory.c: Use unaligned core access functions for all memory reads and writes. * simulator.c (HALT_NYI): Generate an error message if tracing will not tell the user why the simulator is halting. (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. (INSTR): New time-saver macro. (fldrb_abs): New function. Loads an 8-bit value using a scaled offset. (fldrh_abs): New function. Likewise for 16-bit values. (do_vec_SSHL): Allow for negative shift values. (do_vec_USHL): Likewise. (do_vec_SHL): Correct computation of shift amount. (do_vec_SSHR_USHR): Correct decision of signed vs unsigned shifts and computation of shift value. (clz): New function. Counts leading zero bits. (do_vec_CLZ): New function. Implements CLZ (vector). (do_vec_MOV_element): Call do_vec_CLZ. (dexSimpleFPCondCompare): Implement. (do_FCVT_half_to_single): New function. Implements one of the FCVT operations. (do_FCVT_half_to_double): New function. Likewise. (do_FCVT_single_to_half): New function. Likewise. (do_FCVT_double_to_half): New function. Likewise. (dexSimpleFPDataProc1Source): Call new FCVT functions. (do_scalar_SHL): Handle negative shifts. (do_scalar_shift): Handle SSHR. (do_scalar_USHL): New function. (do_double_add): Simplify to just performing a double precision add operation. Move remaining code into... (do_scalar_vec): ... New function. (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs functions. (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR registers. (system_set): New function. (do_MSR_immediate): New function. Stub for now. (do_MSR_reg): New function. Likewise. Partially implements MSR instruction. (do_SYS): New function. Stub for now, (dexSystem): Call new functions.
2016-03-24 01:37:30 +08:00
2016-03-23 Nick Clifton <nickc@redhat.com>
* cpustate.c (aarch64_get_FP_half): New function. Read a vector
register as a half precision floating point number.
(aarch64_set_FP_half): New function. Similar, but for setting
a half precision register.
(aarch64_get_thread_id): New function. Returns the value of the
CPU's TPIDR register.
(aarch64_get_FPCR): New function. Returns the value of the CPU's
floating point control register.
(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
register.
* cpustate.h: Add prototypes for new functions.
* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
* memory.c: Use unaligned core access functions for all memory
reads and writes.
* simulator.c (HALT_NYI): Generate an error message if tracing
will not tell the user why the simulator is halting.
(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
(INSTR): New time-saver macro.
(fldrb_abs): New function. Loads an 8-bit value using a scaled
offset.
(fldrh_abs): New function. Likewise for 16-bit values.
(do_vec_SSHL): Allow for negative shift values.
(do_vec_USHL): Likewise.
(do_vec_SHL): Correct computation of shift amount.
(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
shifts and computation of shift value.
(clz): New function. Counts leading zero bits.
(do_vec_CLZ): New function. Implements CLZ (vector).
(do_vec_MOV_element): Call do_vec_CLZ.
(dexSimpleFPCondCompare): Implement.
(do_FCVT_half_to_single): New function. Implements one of the
FCVT operations.
(do_FCVT_half_to_double): New function. Likewise.
(do_FCVT_single_to_half): New function. Likewise.
(do_FCVT_double_to_half): New function. Likewise.
(dexSimpleFPDataProc1Source): Call new FCVT functions.
(do_scalar_SHL): Handle negative shifts.
(do_scalar_shift): Handle SSHR.
(do_scalar_USHL): New function.
(do_double_add): Simplify to just performing a double precision
add operation. Move remaining code into...
(do_scalar_vec): ... New function.
(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
functions.
(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
registers.
(system_set): New function.
(do_MSR_immediate): New function. Stub for now.
(do_MSR_reg): New function. Likewise. Partially implements MSR
instruction.
(do_SYS): New function. Stub for now,
(dexSystem): Call new functions.
Add simulation of MUL and NEG instructions to AArch64 simulator. * cpustate.c: Remove spurious spaces from TRACE strings. Print hex equivalents of floats and doubles. Check element number against array size when accessing vector registers. * memory.c: Trace memory reads when --trace-memory is enabled. Remove float and double load and store functions. * memory.h (aarch64_get_mem_float): Delete prototype. (aarch64_get_mem_double): Likewise. (aarch64_set_mem_float): Likewise. (aarch64_set_mem_double): Likewise. * simulator (IS_SET): Always return either 0 or 1. (IS_CLEAR): Likewise. (fldrs_pcrel): Load and store floats using 32-bit memory accesses and doubles using 64-bit memory accesses. (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. (store_pair_double, load_pair_float, load_pair_double): Likewise. (do_vec_MUL_by_element): New function. (do_vec_op2): Call do_vec_MUL_by_element. (do_scalar_NEG): New function. (do_double_add): Call do_scalar_NEG.
2016-03-18 17:32:32 +08:00
2016-03-18 Nick Clifton <nickc@redhat.com>
* cpustate.c: Remove spurious spaces from TRACE strings.
Print hex equivalents of floats and doubles.
Check element number against array size when accessing vector
registers.
Fix code to check for illegal element numbers when accessing AArch64 vector registers in AArch64 sim. * cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking for an invalid element index. (SET_VEC_ELEMENT): Likewise.
2016-03-18 22:44:27 +08:00
(GET_VEC_ELEMENT): Fix off by one error checking for an invalid
element index.
(SET_VEC_ELEMENT): Likewise.
Fix thinko in new GET_VEC_ELEMENT macro. * cpustate.c: (GET_VEC_ELEMENT): And fix thinko using macro arguments.
2016-03-19 01:08:27 +08:00
(GET_VEC_ELEMENT): And fix thinko using macro arguments.
Fix code to check for illegal element numbers when accessing AArch64 vector registers in AArch64 sim. * cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking for an invalid element index. (SET_VEC_ELEMENT): Likewise.
2016-03-18 22:44:27 +08:00
Add simulation of MUL and NEG instructions to AArch64 simulator. * cpustate.c: Remove spurious spaces from TRACE strings. Print hex equivalents of floats and doubles. Check element number against array size when accessing vector registers. * memory.c: Trace memory reads when --trace-memory is enabled. Remove float and double load and store functions. * memory.h (aarch64_get_mem_float): Delete prototype. (aarch64_get_mem_double): Likewise. (aarch64_set_mem_float): Likewise. (aarch64_set_mem_double): Likewise. * simulator (IS_SET): Always return either 0 or 1. (IS_CLEAR): Likewise. (fldrs_pcrel): Load and store floats using 32-bit memory accesses and doubles using 64-bit memory accesses. (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. (store_pair_double, load_pair_float, load_pair_double): Likewise. (do_vec_MUL_by_element): New function. (do_vec_op2): Call do_vec_MUL_by_element. (do_scalar_NEG): New function. (do_double_add): Call do_scalar_NEG.
2016-03-18 17:32:32 +08:00
* memory.c: Trace memory reads when --trace-memory is enabled.
Remove float and double load and store functions.
* memory.h (aarch64_get_mem_float): Delete prototype.
(aarch64_get_mem_double): Likewise.
(aarch64_set_mem_float): Likewise.
(aarch64_set_mem_double): Likewise.
* simulator (IS_SET): Always return either 0 or 1.
(IS_CLEAR): Likewise.
(fldrs_pcrel): Load and store floats using 32-bit memory accesses
and doubles using 64-bit memory accesses.
(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
(store_pair_double, load_pair_float, load_pair_double): Likewise.
(do_vec_MUL_by_element): New function.
(do_vec_op2): Call do_vec_MUL_by_element.
(do_scalar_NEG): New function.
(do_double_add): Call do_scalar_NEG.
Fix bugs in the simulation of the AArch64's ADDP, FADDP, LD1, CCMP and CCMP instructions. * simulator.c (set_flags_for_sub32): Correct type of signbit. (CondCompare): Swap interpretation of bit 30. (DO_ADDP): Delete macro. (do_vec_ADDP): Copy source registers before starting to update destination register. (do_vec_FADDP): Likewise. (do_vec_load_store): Fix computation of sizeof_operation. (rbit64): Fix type of constant. (aarch64_step): When displaying insn value, display all 32 bits.
2016-03-03 23:14:35 +08:00
2016-03-03 Nick Clifton <nickc@redhat.com>
* simulator.c (set_flags_for_sub32): Correct type of signbit.
(CondCompare): Swap interpretation of bit 30.
(DO_ADDP): Delete macro.
(do_vec_ADDP): Copy source registers before starting to update
destination register.
(do_vec_FADDP): Likewise.
(do_vec_load_store): Fix computation of sizeof_operation.
(rbit64): Fix type of constant.
(aarch64_step): When displaying insn value, display all 32 bits.
sim: move many common settings from CPPFLAGS to config.h Rather than stuffing the command line with a bunch of -D flags, start moving things to config.h which is managed by autoheader. This makes the makefile a bit simpler and the build output tighter, and it makes the migration to automake easier as there are fewer vars to juggle. We'll want to move the other options out too, but it'll take more work.
2016-01-09 17:09:35 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
sim: drop unused SIM_AC_OPTION_PACKAGES This was imported from the ppc sim, but that was only used to control a single file, and that is already governed by the hw models. There's no need to have a sep configure option here, especially since none of the other sims are using it. Even when the code is enabled, there's no runtime overhead.
2016-01-11 06:49:48 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: allow the environment configure option everywhere Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in order to make the configure flag available. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports too.
2016-01-11 05:52:25 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
* configure: Regenerate.
sim: drop targ-vals.def->nltvals.def indirection We don't have alternative nltvals.def files, so always symlinking the targ-vals.def file to it doesn't gain us anything. It does make the build more complicated though and a pain to convert to something newer (like automake). Drop the symlinking entirely. In the future, we'll want to explode this file anyways into the respective arch dirs so things can be selected dynamically at runtime, so it's not like we'll be bringing this back.
2016-01-10 16:50:08 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: allow the assert configure option everywhere Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order to make the configure flag available, which none of them do. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports.
2016-01-11 04:55:44 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: drop targ-vals.def->nltvals.def indirection We don't have alternative nltvals.def files, so always symlinking the targ-vals.def file to it doesn't gain us anything. It does make the build more complicated though and a pain to convert to something newer (like automake). Drop the symlinking entirely. In the future, we'll want to explode this file anyways into the respective arch dirs so things can be selected dynamically at runtime, so it's not like we'll be bringing this back.
2016-01-10 16:50:08 +08:00
sim: allow the inline configure option everywhere Currently ports have to call SIM_AC_OPTION_INLINE explicitly in order to make the configure flag available. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports too.
2016-01-09 18:58:01 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_INLINE): Delete call.
* configure: Regenerate.
sim: drop --enable-sim-cflags option No other sub directory provides such a configuration option, so drop it from the sim dir as well. This cleans up a good bit of code in the process. If people want to use custom flags for just the sim, they can still run configure+make by hand in the sim subdir and use the normal CFLAGS settings.
2016-01-09 17:00:53 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: drop --enable-sim-{regparm,stdcall} options These options were never exposed for most sims (just the ppc one), and they are really only useful on 32-bit x86 systems. Considering modern systems tend to be 64-bit x86_64 and how well modern compilers are at optimizing code, these have outlived their usefulness.
2016-01-09 18:13:37 +08:00
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: drop common/cconfig.h in favor of a single config.h The common subdir sets up a cconfig.h file to hold checks for the common code. In practice, most files still end up using config.h instead which just leads to confusion. Merge all the configure checks that went into cconfig.h into SIM_AC_COMMON so we can drop the cconfig.h file altogether. Now there is only a single config.h file like normal.
2016-01-09 09:23:37 +08:00
2016-01-09 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
sim: sim_{create_inferior,open,parse_args}: constify argv/env slightly 2016-01-03 Mike Frysinger <vapier@gentoo.org> * sim-options.c (sim_parse_args): Mark argv array const. * sim-options.h (sim_parse_args): Likewise.
2016-01-03 14:51:44 +08:00
2016-01-06 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_create_inferior): Mark argv and env const.
(sim_open): Mark argv const.
sim: aarch64: switch to common disassembler tracing The output should largely be the same.
2015-12-31 12:26:05 +08:00
2016-01-05 Mike Frysinger <vapier@gentoo.org>
* interp.c: Delete dis-asm.h include.
(info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
(sim_create_inferior): Delete disassemble init logic.
(OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
(sim_open): Delete sim_add_option_table call.
* memory.c (mem_error): Delete disas check.
* simulator.c: Delete dis-asm.h include.
(disas): Delete.
(HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
(HALT_NYI): Likewise.
(handle_halt): Delete disas call.
(aarch64_step): Replace disas logic with TRACE_DISASM.
* simulator.h: Delete dis-asm.h include.
(aarch64_print_insn): Delete.
sim: unify min/max macros Import defines from gdb/defs.h to the sim core so we can delete the various copies that already exist.
2016-01-05 11:24:03 +08:00
2016-01-04 Mike Frysinger <vapier@gentoo.org>
* simulator.c (MAX, MIN): Delete.
(do_vec_maxv): Change MAX to max and MIN to min.
(do_vec_fminmaxV): Likewise.
sim: aarch64: drop syscall.h include to fix build The simulator is including syscall.h which is not standard and apparently not required (builds correctly without it on my machine).
2015-12-09 19:34:45 +08:00
2016-01-04 Tristan Gingold <gingold@adacore.com>
* simulator.c: Remove syscall.h include.
sim: punt x86-specific bswap logic The compiler/C library should produce reasonable code for htonl/ntohl, and at least glibc tries pretty hard to always produce good code for them. This logic only had support for 32-bit x86 systems anymore, and it's unlikely people were even opting into this, so drop it all.
2016-01-04 17:06:01 +08:00
2016-01-04 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: drop host endian configure option The --enable-sim-hostendian flag was purely so people had an escape route for when cross-compiling. This is because historically, AC_C_BIGENDIAN did not work in those cases. That was fixed a while ago though, so we can require that macro everywhere now and simplify a good bit of code.
2016-01-03 13:36:13 +08:00
2016-01-03 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
* configure: Regenerate.
sim: convert to bfd_endian Rather than re-invent endian defines, as well as maintain our own list of OS & arch-specific includes, punt all that logic in favor of the bfd ones already set up and maintained elsewhere. We already rely on the bfd library, so leveraging the endian aspect should be fine.
2016-01-03 06:46:16 +08:00
2016-01-02 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
sim: aarch64/msp430: fix disassembler usage The disasm framework reserves the private_data field for the disassemblers themselves, not for people who use the disassembler. Instead, there is an application_data field for callers such as the sim. Switch to it to avoid random corruption/crashes when the disassemblers use private_data.
2015-12-27 14:41:27 +08:00
2015-12-27 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_dis_read): Change private_data to application_data.
(sim_create_inferior): Likewise.
sim: unify sim-hload Pretty much all targets are using this module already, so add it to the common list of objects. The only oddball out here is cris and that's because it supports loading via an offset for all the phdrs. We drop support for that.
2015-04-11 07:40:34 +08:00
2015-12-27 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Delete sim-hload.o.
sim: punt WITH_DEVICES & tconfig.h support No arch is using this anymore, and we want all new ports using the hardware framework instead. Punt WITH_DEVICES and the two callbacks device_io_{read,write}_buffer. We can also punt the tconfig.h file as no port is using it anymore. This fixes in-tree builds that get confused by picking up the wrong one (common/ vs <port>/) caused by commit ae7d0cac8ce971f7108d270c. Any port that needs to set up a global define can use their own sim-main.h file that they must provide regardless.
2015-12-27 09:20:23 +08:00
2015-12-26 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
sim: standardize sim_create_inferior handling of argv a bit more For targets that process argv in sim_create_inferior, improve the code: - provide more details in the comment - make the check for when to re-init more robust - clean out legacy sim_copy_argv code This will be cleaned up more in the future when we have a common inferior creation function, but at least help new ports get it right until then.
2015-12-26 20:05:41 +08:00
2015-12-26 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_create_inferior): Update comment and argv check.
sim: aarch64: move ChangeLog content
2015-12-26 20:12:13 +08:00
2015-12-14 Nick Clifton <nickc@redhat.com>
* simulator.c (system_get): New function. Provides read
access to the dczid system register.
(do_mrs): New function - implements the MRS instruction.
(dexSystem): Call do_mrs for the MRS instruction. Halt on
unimplemented system instructions.
2015-11-24 Nick Clifton <nickc@redhat.com>
* configure.ac: New configure template.
* aclocal.m4: Generate.
* config.in: Generate.
* configure: Generate.
* cpustate.c: New file - functions for accessing AArch64 registers.
* cpustate.h: New header.
* decode.h: New header.
* interp.c: New file - interface between GDB and simulator.
* Makefile.in: New makefile template.
* memory.c: New file - functions for simulating aarch64 memory
accesses.
* memory.h: New header.
* sim-main.h: New header.
* simulator.c: New file - aarch64 simulator functions.
* simulator.h: New header.
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