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x86: move ImmExt processing With abuses of ImmExt gone, all templates using it have operands. Move its main invocation into process_operands(), matching its secondary one for the SSE2AVX case.
2020-06-25 15:30:09 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Move call to process_immext()
...
(process_operands): ... here.
x86: operand sizing prefixes can disambiguate insns Use of an explicit data size or REX.W prefix is sufficient indication of the intended operation when operand size can't be derived from suffix or register operands. Avoid the ambiguity warning and make in particular immediate handling (sizing) cope with explicitly specified prefixes. Extending/reusing the noreg16 test made me notice a few cases of unintentional 32-bit addressing, which gets corrected at the same time.
2020-06-25 15:29:29 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Skip ambiguous operand size
diagnostic when there is a sizing prefix. Switch to word/dword/
qword encoding when there is a sizing prefix and no (explicit or
derived) suffix.
(update_imm): Handle presence of a sizing prefix.
* testsuite/gas/i386/noreg16-data32.d,
testsuite/gas/i386/noreg32-data16.d,
testsuite/gas/i386/noreg32-data16.e,
testsuite/gas/i386/noreg64-data16.d,
testsuite/gas/i386/noreg64-data16.e,
testsuite/gas/i386/noreg64-rex64.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s:
Introduce and use pfx* macros.
* testsuite/gas/i386/noreg16.s: Likewise. Replace 32-bit
addressing.
* testsuite/gas/i386/noreg16.d: Adjust expectations.
x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITE SYSRET can't use the same macro as IRET, since there's no 16-bit operand size form of it. Re-use LQ for it instead. Doing so made obvious that outside of 64-bit mode {,V}CVTSI2S{S,D} and PTWRITE should have an 'l' suffix printed only in suffix-always mode.
2020-06-25 15:27:21 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx-16bit.d,
testsuite/gas/i386/avx-scalar.d, testsuite/gas/i386/avx.d,
testsuite/gas/i386/avx512f-16bit.d,
testsuite/gas/i386/avx512f.d,
testsuite/gas/i386/evex-lig256.d,
testsuite/gas/i386/evex-lig512.d
testsuite/gas/i386/evex-wig1.d, testsuite/gas/i386/katmai.d,
testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d,
testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/simd.d,
testsuite/gas/i386/sse2-16bit.d,
testsuite/gas/i386/sse2.d, testsuite/gas/i386/sse2avx.d: Adjust
expectations.
x86-64: REX prefix is invalid with VEX etc Just like for the data size prefix (see commit 7a8655d2bbdc ["x86: don't abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX prefix is invalid with VEX/XOP/EVEX.
2020-06-25 15:26:28 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Also reject explicit REX
prefixes with VEX and alike encoded insns. Zap consumed bits
from i.rex.
(output_insn): Don't ignore REX prefix for VEX and alike
encodings; abort() instead if encountered.
* testsuite/gas/i386/x86-64-pseudos.s: Move REX-with-VEX cases
...
* testsuite/gas/i386/x86-64-pseudos-bad.s: ... here.
* testsuite/gas/i386/x86-64-pseudos.d,
testsuite/gas/i386/x86-64-pseudos-bad.l: Adjust expectations.
x86-64: honor REX prefixes for SSE2AVX Legacy encoded insns do so, and their automatic conversion to AVX ones ought to produce functionally identical code. Therefore explicit REX prefixes cannot simply be ignored. This is in particular relevant because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in older gas by other than using a REX64 prefix.
2020-06-25 15:25:52 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_operands): Translate explicit REX
prefix into i.rex for SSE2AVX templates.
(set_rex_vrex): New helper.
(build_modrm_byte): Use it.
* testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explict
REX prefixes.
* testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
x86: also refuse data size prefix on SIMD insns The data size prefix alters the meaning of legacy encoded SIMD insns, and hence shouldn't be accepted there. Use of it also leads to inconsistencies in SSE2AVX mode. Don't match insns with data size prefix against SSE2AVX templates.
2020-06-25 15:25:12 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_flags_match): Only match SSE2AVX
templates when there's no data size prefix.
(md_assemble): Reject data size prefix also for legacy encoded
SIMD templates.
* testsuite/gas/i386/prefix32.s, testsuite/gas/i386/prefix64.s:
Uncomment previously not working line.
* testsuite/gas/i386/sse2avx.s: Add ldmxcsr/stmxcsr cases with
data16 prefix.
* testsuite/gas/i386/prefix32.l, testsuite/gas/i386/prefix64.l,
testsuite/gas/i386/sse2avx.d: Adjust expectations.
x86: drop stray assignment from build_evex_prefix() Unlike in build_vex_prefix() this is not needed here.
2020-06-25 15:24:23 +08:00
2020-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (build_evex_prefix): Drop early setting of
vec_length.
RISC-V: Generate ELF priv attributes if priv instruction are explicited used. We should generate the ELF priv attributes only if, 1. The priv attributes are already set in the assembly file. 2. The CSR are explicited used. 3. The privileged instruction are explicited used. * There are four privileged instruction defined in the v1.11 priv spec: `mret`, `sret`, `wfi` and `sfence.vma`. * `sfence.vm` is dropped in the v1.10 priv spec. * `uret` is actually a N-ext instruction. So it is better to regard it as an user instruction rather than the priv instruction. * `hret` is used to return from traps in H-mode. H-mode is removed since the v1.10 priv spec, but probably be added in the new hypervisor spec. Therefore, `hret` should be controlled by the hypervisor spec rather than priv spec in the future. * `dret` is a debug instruction. We should record the debug spec versions once it is explicited used in the future. gas/ * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to explicit_priv_attr. It used to indicate CSR or priv instructions are explictly used. (riscv_is_priv_insn): Return True if it is a privileged instruction. (riscv_ip): Call riscv_is_priv_insn to check whether the instruction is privileged or not. If it is, then set explicit_priv_attr to TRUE. (riscv_write_out_attrs): Clarification of when to generate the elf priv spec attributes. * testsuite/gas/riscv/attribute-11.s: Add comments. * testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol `priv_insn_<n>` to decide which priv instruction is expected to used. (<n> is a to g.) * testsuite/gas/riscv/attribute-14a.d: Likewise. * testsuite/gas/riscv/attribute-14b.d: Likewise. * testsuite/gas/riscv/attribute-14c.d: Likewise. * testsuite/gas/riscv/attribute-14d.d: Likewise. * testsuite/gas/riscv/attribute-14e.d: Likewise.
2020-06-22 16:11:18 +08:00
2020-06-23 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
explicit_priv_attr. It used to indicate CSR or priv instructions are
explictly used.
(riscv_is_priv_insn): Return True if it is a privileged instruction.
(riscv_ip): Call riscv_is_priv_insn to check whether the instruction
is privileged or not. If it is, then set explicit_priv_attr to TRUE.
(riscv_write_out_attrs): Clarification of when to generate the elf
priv spec attributes.
* testsuite/gas/riscv/attribute-11.s: Add comments.
* testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol
`priv_insn_<n>` to decide which priv instruction is expected to used.
(<n> is a to e.)
* testsuite/gas/riscv/attribute-14a.d: Likewise.
* testsuite/gas/riscv/attribute-14b.d: Likewise.
* testsuite/gas/riscv/attribute-14c.d: Likewise.
* testsuite/gas/riscv/attribute-14d.d: Likewise.
* testsuite/gas/riscv/attribute-14e.d: Likewise.
RISC-V: Report warning when linking the objects with different priv specs. We do know some conflicts among different privileged specs. For linker, the safest approach is that don't allow the object linked with others which may cause conflicts. But this may cause inconvenience since not all objects with conflicting priv specs are linked will cause problems. But it is hard to know the detailed conflict cases for linker, so we probably need a option to tell linker that we do know there are no conflicts, or we are willing to take risks to link the objects with conflicted priv specs. But the option is still under discussion. Therefore, we can report warnings rather than errors when linking the objects with conflicted priv specs. This not only makes the linker more flexible, but also warns people that the conflicts may happen. We also need to update the output priv spec version once the input priv spec is newer. bfd/ * elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker. (riscv_get_priv_spec_class): Likewise. (riscv_get_priv_spec_name): Likewise. (riscv_get_priv_spec_class_from_numbers): New function, convert the version numbers into string, then call riscv_get_priv_spec_class to get the priv spec class. * elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration from include/opcode/riscv.h to bfd/elfxx-riscv.h. (riscv_get_priv_spec_name): Likewise. (riscv_get_priv_spec_class_from_numbers): New forward declaration. (opcode/riscv.h): Include it in the header rather than elfxx-riscv.c. * elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes of input and output objects form their priv spec attributes by riscv_get_priv_spec_class_from_numbers. Report warning rather than errors when linking objects with differnet priv spec versions. We do know v1.9.1 may have conflicts to other versions, so report the warning, too. After that, update the output priv spec version to the newest one so far. gas/ * config/tc-riscv.c (buf_size, buf): Remove the unused variables. (riscv_set_default_priv_spec): Get the priv spec version from the priv spec attributes by riscv_get_priv_spec_class_from_numbers. include/ * opcode/riscv.h (riscv_get_priv_spec_class): Move the function forward declarations to bfd/elfxx-riscv.h. (riscv_get_priv_spec_name): Likewise. opcodes/ * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c. * riscv-dis.c: Include elfxx-riscv.h. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
2020-06-12 23:06:49 +08:00
2020-06-22 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
(riscv_set_default_priv_spec): Get the priv spec version from the
priv spec attributes by riscv_get_priv_spec_class_from_numbers.
SH gas configure and ld tests All current SH gas targets use BFD. sh-coff was incorrectly reported as unsupported. gas/ * configure.tgt: Set bfd_gas for all SH targets. ld/ * testsuite/ld-sh/sh.exp: Don't run relax tests for non-ELF. Fail when ld_assemble fails. Use elseif to reduce indentation.
2020-06-20 09:11:40 +08:00
2020-06-20 Alan Modra <amodra@gmail.com>
* configure.tgt: Set bfd_gas for all SH targets.
x86: also test alternative VMGEXIT encoding gas/ * testsuite/gas/i386/arch-13.s: Add alternative VMGEXIT case. * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust expectations. opcodes/ * i386-dis.c (prefix_table): Revert the last vmgexit change.
2020-06-18 15:13:49 +08:00
2020-06-18 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/arch-13.s: Add alternative VMGEXIT case.
* testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
expectations.
x86: Correct noavx512_vp2intersect * config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS. * doc/c-i386.texi: Add avx512_vp2intersect.
2020-06-17 01:07:15 +08:00
2020-06-16 Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect
cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS.
* doc/c-i386.texi: Add avx512_vp2intersect.
x86: drop SSE4a from SSE check again Upon re-consideration in commit 569d50f1c611 ("x86: further refine SSE check (SSE4a, SHA, GFNI)") I went too far: Mixing of SSE and AVX insns doesn't suffer as bad a penalty on AMD CPUs as on Intel ones. SSE4a being an AMD-only extension, it shouldn't be part of the ISA extensions set for which the diagnostic may get issued. Undo that part.
2020-06-16 16:34:55 +08:00
2020-06-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Drop SSE4a from SSE check
conditional.
* testsuite/gas/i386/sse-check.s: Adjust comment.
* testsuite/gas/i386/sse-check-error.l,
testsuite/gas/i386/sse-check-warn.e,
testsuite/gas/i386/x86-64-sse-check-error.l: Adjust
expectations.
Really remove tic30-aout support bfd/ * aout-tic30.c: Delete file. * Makefile.am (BFD32_BACKENDS): Remove aout-tic30.lo. (BFD32_BACKENDS_CFILES): Remove aout-tic30.c. * config.bfd (c30-*-*aout*, tic30-*-*aout*): Remove entry. (xc16x-*-elf): Sort properly. * configure.ac: Remove tic30_aout_vec. * targets.c: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. gas/ * config/tc-tic30.h: Remove OBJ_AOUT support. * configure.tgt: Delete tic30-*-*aout* entry. ld/ * emulparams/tic30aout.sh: Delete file. * scripttempl/tic30aout.sc: Delete file. * Makefile.am: Remove etic30aout.c from ALL_EMULATION_SOURCES and delete dependency. * configure.tgt: Delete tic30-*-*aout* entry. * testsuite/ld-scripts/sane1.d: Delete tic30-*-aout mention. * testsuite/ld-scripts/segment-start.d: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2020-06-16 10:43:05 +08:00
2020-06-16 Alan Modra <amodra@gmail.com>
* config/tc-tic30.h: Remove OBJ_AOUT support.
* configure.tgt: Delete tic30-*-*aout* entry.
xtensa: allow runtime ABI selection 2020-06-15 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED) (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New global variable. (xtensa_abi_choice): New function. (elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of XSHAL_ABI to select PLT code. gas/ * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (option_abi_windowed, option_abi_call0): New enum constants. (md_longopts): Add entries for --abi-windowed and --abi-call0. (md_parse_option): Add handlers for --abi-windowed and --abi-call0. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. * doc/as.texi (Target Xtensa options): Add --abi-windowed and --abi-call0 to the list of options. * doc/c-xtensa.texi: Add description for options --abi-windowed and --abi-call0. * testsuite/gas/xtensa/abi-call0.d: New test definition. * testsuite/gas/xtensa/abi-windowed.d: New test definition. * testsuite/gas/xtensa/abi.s: New test source. include/ * elf/xtensa.h (xtensa_abi_choice): New declaration. ld/ * emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition. (XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros. (elf32xtensa_abi): New declaration. (xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test ABI tag consistency. (xtensa_add_config_info): Use xtensa_abi_choice instead of XSHAL_ABI to format ABI tag. (PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED, OPTION_ABI_CALL0 and declare elf32xtensa_abi. (PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and --abi-call0. (PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and --abi-call0. (PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and --abi-call0. * ld.texi: Add description for options --abi-windowed and --abi-call0.
2020-05-10 23:03:08 +08:00
2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(option_abi_windowed, option_abi_call0): New enum constants.
(md_longopts): Add entries for --abi-windowed and --abi-call0.
(md_parse_option): Add handlers for --abi-windowed and
--abi-call0.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
* doc/as.texi (Target Xtensa options): Add --abi-windowed and
--abi-call0 to the list of options.
* doc/c-xtensa.texi: Add description for options --abi-windowed
and --abi-call0.
* testsuite/gas/xtensa/abi-call0.d: New test definition.
* testsuite/gas/xtensa/abi-windowed.d: New test definition.
* testsuite/gas/xtensa/abi.s: New test source.
x86: Correct xsusldtrk mnemonic The correct mnemonic is xsusldtrk, not xsuspldtrk. gas/ PR gas/26115 * testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with xsusldtrk. * testsuite/gas/i386/tsxldtrk.s: Likewise. * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise. * testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise. opcodes/ PR gas/26115 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
2020-06-14 20:18:35 +08:00
2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26115
* testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with
xsusldtrk.
* testsuite/gas/i386/tsxldtrk.s: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise.
RISC-V: Drop the privileged spec v1.9 support. There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is 0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable, but may also cause risk of compatibility. Binutils already support the -mpriv-spec options and ELF priv attributes, which can used to choose what privileged spec you want, and then give a correponding CSR name and address to use. But Gdb and other tools don't have the simialr mechanism for now. However, there are two things can be confirmed, 1. If we don't have a way to control the priv specs, then the changes, like MISA, will cause risk and hard to maintain. 2. We get the guarantee that the CSR address won't be reused in the future specs, even if it is dropped. I'm not sure if Gdb needs to care about the priv spec versions, it is still discussing. But drop the priv spec v1.9, and make sure that we won't reuse the CSR address is a useful solution for now. Also, we might drop the v1.9.1 in a year or two. After that, specs above v1.10 should be compatible anyway. gas/ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. include/ * opcode/riscv-opc.h: Update the defined versions of CSR from PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9. * opcode/riscv.h (enum riscv_priv_spec_class): Remove PRIV_SPEC_CLASS_1P9. opcodes/ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2020-06-10 14:07:54 +08:00
2020-06-12 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
[PATCH] gas/doc: improve AVR modifiers wording. * doc/c-avr.texi: Improve wording.
2020-06-09 18:13:39 +08:00
2020-06-09 Seth Girvan <snth@snthhacks.com>
* doc/c-avr.texi: Improve wording.
x86: add missing 64-bit tests for "don't ignore mandatory pseudo prefixes" Commit da4977e00b73 added the 32-bit test files, but failed to add the 64-bit ones.
2020-06-09 17:28:15 +08:00
2020-06-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-pseudos-bad.s,
testsuite/gas/i386/x86-64-pseudos-bad.l: New.
x86: consistently print prefixes explicitly which are invalid with VEX etc All of data size, rep, lock, and rex prefixes are invalid with VEX- and alike encoded insns. Make sure they get printed explicitly in all cases, to signal the anomaly. With this, do away with "rex_ignored" - if there is a rex prefix, we want to print it anyway for VEX etc (and there's nothing "ignored" about it in the first place - such an instruction will raise #UD).
2020-06-09 14:59:04 +08:00
2020-06-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/prefix.s: Add bogus prefix-with-VEX/EVEX
encoding tests.
* testsuite/gas/i386/prefix.d: Adjust expectations.
x86: correct decoding of packed-FP-only AVX encodings Various AVX insns utilizing the X macro fail to reject F3/F2 embedded prefix encodings. As the PREFIX_OPCODE attribute wasn't used by any non-legacy-encoded insns so far, re-use it to achieve the intended effect.
2020-06-09 14:56:39 +08:00
2020-06-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/prefix.s: Add bogus REP / EVEX.W prefix
with VEX/EVEX encoding tests.
* testsuite/gas/i386/prefix.d: Adjust expectations.
x86-64: adjust far indirect branch handling An unwanted side effect of 5990e377e5a3 ("x86-64: Intel64 adjustments for insns dealing with far pointers") was that with -mintel64 LCALL and LJMP would now default to 64-bit operand size. Since 64-bit far branches aren't portable, the default operand size should still be 32-bit. However, since the 64-bit variant is permitted, an ambiguous operand warning should be issued. As to the actual code change, please note that the conditional surrounding the switch() that gets adjusted covers several cases which are of no interest to or benign in 64-bit mode, hence the new conditional added can be quite a bit less involved.
2020-06-09 14:47:31 +08:00
2020-06-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Restrict defaulting to 'q'
suffix.
* testsuite/gas/i386/noreg64.s: Add lcall/ljmp cases.
* testsuite/gas/i386/noreg64.d: Adjust expectations.
* testsuite/gas/i386/noreg-intel64.d,
testsuite/gas/i386/noreg-intel64.l,
testsuite/gas/i386/noreg-intel64.s: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: don't ignore mandatory pseudo prefixes {vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not be randomly ignored. Fix this for insns without operands as well as for insns referencing the high 16 [XYZ]MM registers. To achieve the former, re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and moving its only operand check to check_VecOperands(). This involves fixing a testcase relying on {vex2} to get ignored.
2020-06-09 14:46:22 +08:00
2020-06-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (vex_encoding_error): New enumerator.
(VEX_check_operands): Rename to VEX_check_encoding. Check
for vex_encoding_error. Move Imm4 handling ...
(check_VecOperands): ... here.
(match_template): Call VEX_check_encoding when there are no
operands. Split construct calling check_VecOperands and
VEX_check_encoding (when there are operands).
(check_register): Don't blindly set vex_encoding_evex.
* testsuite/gas/i386/pseudos-bad.s,
testsuite/gas/i386/pseudos-bad.l: New.
* testsuite/gas/i386/i386.exp: Run new test.
* testsuite/gas/i386/xmmhi64.s: Drop {vex2}.
[PATCH] arm: Add DFB instruction for ARMv8-R gas/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (insns): Add dfb. * testsuite/gas/arm/dfb.d: New test. * testsuite/gas/arm/dfb.s: Input for test. opcodes/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * arm-dis.c (arm_opcodes): Add dfb. (thumb32_opcodes): Add dfb.
2020-06-08 22:16:29 +08:00
2020-06-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-arm.c (insns): Add dfb.
* testsuite/gas/arm/dfb.d: New test.
* testsuite/gas/arm/dfb.s: Input for test.
Fix a gas testsuite failure for PE based targets which cannot assemble the cfi-i386-2 test. * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets.
2020-06-08 17:25:57 +08:00
2020-06-08 Nick Clifton <nickc@redhat.com>
* testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets.
x86: also handle %k<N> and %bnd<N> in debugging helpers Adjustment of this function was missed when support for the respective registers was added.
2020-06-08 14:40:58 +08:00
2020-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pi): Add checks for RegMask and RegBND.
x86: simplify check_byte_reg() With the introduction of what right now is the very first conditional in the function's loop (commit dc821c5f9ae5 ["x86: replace Reg8, Reg16, Reg32, and Reg64"]), the last if() in the same loop has become pointless - retain just its body.
2020-06-08 14:40:22 +08:00
2020-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_byte_reg): Drop dead conditional
around as_bad().
x86: restrict %tr<N> visibility First of all, these registers have never been available on any 64-bit CPU, and hence should not be recognized in 64-bit mode. But even before that they had already disappeared - also don't recognize them when 586 or 686 architectures were explicitly set.
2020-06-08 14:39:57 +08:00
2020-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_register): Split RegTR handling, to
fail recognition also in 64-bit mode as well as with i586 or
i686 explicitly enabled.
* testsuite/gas/i386/x86_64.s: Add insns referencing tr<N>.
* testsuite/gas/i386/x86_64-intel.d,
testsuite/gas/i386/x86_64.d: Adjust expectations.
ix86: enable 2nd CFI test While putting together the previous patch I noticed that this test, forever since its introduction, was dead. Update it so it will pass, and enable it.
2020-06-08 14:39:23 +08:00
2020-06-08 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/cfi/cfi-i386-2.d: Adjust expectations.
* testsuite/gas/cfi/cfi.exp: Run this test.
x86: also allow %st(N) in CFI directives In 0e0eea782025 ("x86: x87-related adjustments") I screwed up CFI directives with FPU support disabled, by moving the conditional there across a check of "allow_pseudo_reg". Add the missing check.
2020-06-08 14:38:54 +08:00
2020-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (parse_real_register): Add allow_pseudo_reg
check to %st(N) parsing logic.
* testsuite/gas/cfi/cfi-i386.s: Set "generic32" arch.
x86: restrict use of register aliases Register aliases (created e.g. via .set) check their target register at the time of creation of the alias. While this makes sense, it's not enough: The underlying register must also be "visible" at the time of use. Wrong use of such aliases would lead to internal errors in e.g. add_prefix() or build_modrm_byte(). Split the checking part of parse_real_register() into a new helper function and use it also from the latter part of parse_register() (at the same time replacing a minor open coded part of it). Since parse_register() returning NULL already has a meaning, a fake new "bad register" indicator gets added, which all callers need to check for.
2020-06-08 14:37:47 +08:00
2020-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (bad_reg): New.
(check_VecOperations, i386_att_operand, i386_parse_name): Check
for it.
(check_register): New, broken out from ...
(parse_real_register): ... here. Call it.
(parse_register): Call it, and error upon failure.
* testsuite/gas/i386/equ-bad.s, testsuite/gas/i386/equ-bad.l,
testsuite/gas/i386/x86-64-equ-bad.s,
testsuite/gas/i386/x86-64-equ-bad.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
Power10 tidies binutils/ * doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10. gas/ * config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2020-06-06 12:52:37 +08:00
2020-06-06 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10.
* doc/c-ppc.texi: Likewise.
Rename PowerPC64 pcrel GOT TLS relocations These relocations should have had REL in their names, to reflect the fact that they are pc-relative. Fix that now by adding _PCREL. I've added some back-compatibility code to support anyone using .reloc with the old relocations. include/ * elf/ppc64.h (elf_ppc64_reloc_type): Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. bfd/ * reloc.c: Rename BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34, BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34, BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34, BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34. * elf64-ppc.c: Update throughout for reloc renaming. (ppc64_elf_reloc_name_lookup): Handle old reloc names. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c: Update throughout for reloc renaming. elfcpp/ * powerpc.h: Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. gold/ * powerpc.cc: Update throughout for reloc renaming.
2020-06-06 10:26:20 +08:00
2020-06-06 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c: Update throughout for reloc renaming.
gas: avoid GCC 10 warning stringop-overflow in tc-bpf.c The GAS struct frag ends with a field `fr_literal' whose purpose is to mark the begining of the frag's data: struct frag { ... /* Data begins here. */ char fr_literal[1]; }; The code in gas/config/tc-bpf.c recently committed: where = fixP->fx_frag->fr_literal + fixP->fx_where; where[1] = target_big_endian ? 0x01 : 0x10; triggers the stringop-overflow warning in GCC 10+, since the compiler assumes the size of the modified buffer is 1 byte. This patch slightly modifies the code to make tc-bpf.c buildable with GCC 10+. 2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning stringop-overflow.
2020-06-05 22:23:30 +08:00
2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning
stringop-overflow.
RISC-V: Don't generate the ELF privilege attributes when no CSR are used. gas/ * config/tc-riscv.c (explicit_csr): New static boolean. Used to indicate CSR are explictly used. (riscv_ip): Set explicit_csr to TRUE if any CSR is used. (riscv_write_out_attrs): If we already have set elf priv attributes, then generate them. Otherwise, don't generate them when no CSR are used. * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-11.s: New testcase. * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is used, so we should output the ELF priv attributes. * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is used, so output the priv attributes according to the -mpriv-spec. * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't used, so ignore the -mpriv-spec setting. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
2020-05-29 15:31:46 +08:00
2020-06-05 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (explicit_csr): New static boolean.
Used to indicate CSR are explictly used.
(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
(riscv_write_out_attrs): If we already have set elf priv
attributes, then generate them. Otherwise, don't generate
them when no CSR are used.
* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-11.s: New testcase.
* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
used, so we should output the ELF priv attributes.
* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
used, so output the priv attributes according to the -mpriv-spec.
* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
used, so ignore the -mpriv-spec setting.
gas: Fix ip2k-elf and xstormy16-elf build Fix ip2k-elf and xstormy16-elf build due to commit e9bffec9afc45cf7c49308f0b4b8cc6bf68f58f2 Author: Jose E. Marchesi <jose.marchesi@oracle.com> Date: Thu Jun 4 16:15:53 2020 +0200 opcodes: discriminate endianness and insn-endianness in CGEN ports * config/tc-ip2k. (ip2k_apply_fix): Pass endianness to cgen_get_insn_value. * config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass endianness to cgen_get_insn_value and cgen_put_insn_value.
2020-06-05 02:15:06 +08:00
2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
cgen_get_insn_value.
* config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass
endianness to cgen_get_insn_value and cgen_put_insn_value.
gas: simplify code in tc-bpf.c:md_apply_fix 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_apply_fix): Simplify and avoid using cgen_put_insn_value.
2020-06-04 22:33:34 +08:00
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_apply_fix): Simplify and avoid using
cgen_put_insn_value.
cpu,gas,opcodes: remove no longer needed workaround from the BPF port cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
2020-06-04 22:17:07 +08:00
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
bpf_cgen_cpu_open.
(md_assemble): Remove no longer needed hack.
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04 22:15:53 +08:00
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
tcl global directive outside proc body does nothing (gas) * testsuite/config/default.exp: Remove global directive outside proc body. * testsuite/gas/mep/complex-relocs.exp: Likewise. * testsuite/gas/microblaze/relax_size.exp: Likewise. * testsuite/gas/microblaze/reloc_sym.exp: Likewise. * testsuite/gas/mt/relocs.exp: Likewise. * testsuite/gas/rx/rx.exp: Likewise.
2020-06-04 14:30:46 +08:00
2020-06-04 Alan Modra <amodra@gmail.com>
* testsuite/config/default.exp: Remove global directive outside
proc body.
* testsuite/gas/mep/complex-relocs.exp: Likewise.
* testsuite/gas/microblaze/relax_size.exp: Likewise.
* testsuite/gas/microblaze/reloc_sym.exp: Likewise.
* testsuite/gas/mt/relocs.exp: Likewise.
* testsuite/gas/rx/rx.exp: Likewise.
* gas/doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.
2020-06-04 04:42:54 +08:00
2020-06-03 Stephen Casner <casner@acm.org>
* doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.
RISC-V: Fix minor bugs in .insn docs. This fixes some minor bugs in the docs for the .insn directive pointed out by Frédéric Pétrot, and I added a few more cleanups since I was changing the docs. gas/ PR 26051 * doc/c-riscv.texi (RISC-V-Formats): Add missing I format using simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B formats using simm12(rs1). Correct SB and B to use rs1 and rs2. Move B before SB. Move J before UJ.
2020-06-03 09:36:14 +08:00
2020-06-02 Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Jim Wilson <jimw@sifive.com>
PR 26051
* doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B
formats using simm12(rs1). Correct SB and B to use rs1 and rs2.
Move B before SB. Move J before UJ.
gas: Fix checking for backwards .org with negative offset This patch fixes internal errors in (at least) arm and aarch64 GAS when assembling code that attempts a negative .org. The bug appears to be a regression introduced in binutils-2.29 by commit 9875b36538d. * write.c (relax_segment): Fix handling of negative offset when relaxing an rs_org frag. * testsuite/gas/aarch64/org-neg.d: New test. * testsuite/gas/aarch64/org-neg.l: Error output for test. * testsuite/gas/aarch64/org-neg.s: Input for test. * testsuite/gas/arm/org-neg.d: New test. * testsuite/gas/arm/org-neg.l: Error output for test. * testsuite/gas/arm/org-neg.s: Input for test.
2020-05-29 23:04:50 +08:00
2020-06-01 Alex Coplan <alex.coplan@arm.com>
* write.c (relax_segment): Fix handling of negative offset when
relaxing an rs_org frag.
* testsuite/gas/aarch64/org-neg.d: New test.
* testsuite/gas/aarch64/org-neg.l: Error output for test.
* testsuite/gas/aarch64/org-neg.s: Input for test.
* testsuite/gas/arm/org-neg.d: New test.
* testsuite/gas/arm/org-neg.l: Error output for test.
* testsuite/gas/arm/org-neg.s: Input for test.
Fix all unexpected failures in gas testsuite for pdp11-aout. These failures were caused by the PDP11's mix of little-endian octets in shorts but shorts in big endian order for long or quad so regexps did not match. Also tests used addresses as values in .long which required BRD_RELOC_32 that was not implemented. * gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad * gas/testsuite/gas/all/gas.exp: Select alternate test scripts for pdp11, skip octa test completely. * gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s * gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order. * gas/testsuite/gas/all/cond-pdp11.l: Match different octet order. * bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of addreses in .long (used in testsuites) and .stab values.
2020-05-29 01:11:59 +08:00
2020-05-28 Stephen Casner <casner@acm.org>
Fix unexpected failures in gas testsuite for pdp11-aout target.
These are caused by the PDP11's mix of little-endian octets in
shorts but shorts in big endian order for long or quad.
* config/tc-pdp11.c (md_number_to_chars): Implement .quad
* testsuite/gas/all/gas.exp: Select alternate test scripts for
pdp11, skip octa test completely.
* testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
* testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
* testsuite/gas/all/cond-pdp11.l: Match different octet order.
[PATCH] gas: Fix comment on definition of frag_grow() * frags.c (frag_grow): Fix comment.
2020-05-28 21:30:34 +08:00
2020-05-28 Alex Coplan <alex.coplan@arm.com>
* frags.c (frag_grow): Fix comment.
Fix PR gas/26001 (pdp11-*-*) PR gas/26001 * gas/config/tc-pdp11.c (parse_reg): Distinguish register names from symbols that begin with a register name. * gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols. * gas/testsuite/gas/pdp11/pr26001.s: Likewise. * gas/testsuite/gas/pdp11/pr26001.d: Likewise.
2020-05-28 09:40:38 +08:00
2020-05-27 Stephen Casner <casner@acm.org>
PR gas/26001
* config/tc-pdp11.c (parse_reg): Distinguish register names from
symbols that begin with a register name.
* testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
* testsuite/gas/pdp11/pr26001.s: Likewise.
* testsuite/gas/pdp11/pr26001.d: Likewise.
RISC-V: Fix missing initialization of riscv_csr_extra structs The next pointer of struct riscv_csr_extra was not always initilized to NULL or a valid pointer, causing the assembler to attempt to read through an uninitialized pointer on startup. gas/ChangeLog: * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next pointer when creating struct riscv_csr_extra.
2020-05-28 00:34:58 +08:00
2020-05-27 Simon Cook <simon.cook@embecosm.com>
* config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
pointer when creating struct riscv_csr_extra.
gas: Adjust x86 tests for PECOFF * testsuite/gas/i386/align-branch-9.d: Updated for PECOFF. * testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF. * testsuite/gas/i386/inval-avx512f.l: Updated.
2020-05-27 05:17:09 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/align-branch-9.d: Updated for PECOFF.
* testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF.
* testsuite/gas/i386/inval-avx512f.l: Updated.
ChangeLog entries for f687f5f563
2020-05-27 00:34:39 +08:00
2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
load/store instruction variants with alignment hints.
* testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
instruction variants with alignment hints.
tc-xgate.c: Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X to silence GCC 10 warning: gas/config/tc-xgate.c:1339:5: error: implicit conversion from ‘enum elf_xgate_reloc_type’ to ‘bfd_reloc_code_real_type’ {aka ‘enum bfd_reloc_code_real’} [-Werror=enum-conversion] 1339 | R_XGATE_PCREL_9); | ^~~~~~~~~~~~~~~ PR gas/26044 * config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X instead of R_XGATE_PCREL_X. (xgate_parse_operand): Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X.
2020-05-27 00:33:48 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26044
* config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X
instead of R_XGATE_PCREL_X.
(xgate_parse_operand): Replace R_XGATE_PCREL_X with
BFD_RELOC_XGATE_PCREL_X.
gas: Silence GCC 10 warning on tc-visium.c PR gas/26044 * config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26 22:54:05 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26044
* config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal
with &fragP->fr_literal[0].
gas: Silence GCC 10 warning tc-vax.c PR gas/26044 * config/tc-vax.c (md_estimate_size_before_relax): Replace fragP->fr_literal with &fragP->fr_literal[0]. (md_convert_frag): Likewise.
2020-05-26 22:41:07 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26044
* config/tc-vax.c (md_estimate_size_before_relax): Replace
fragP->fr_literal with &fragP->fr_literal[0].
(md_convert_frag): Likewise.
gas: Silence GCC 10 warning on tc-v850.c PR gas/26044 * config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26 21:56:18 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26044
* config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal
with &fragP->fr_literal[0].
gas: Silence GCC 10 warning on tc-crx.c opcode/crx.h has typedef enum { ... MAX_REG } reg; typedef enum { c0 = MAX_REG, } copreg; tc-crx.c has static int getreg_image (reg r) { ... /* Check whether the register is in registers table. */ if (r < MAX_REG) rreg = &crx_regtab[r]; /* Check whether the register is in coprocessor registers table. */ else if (r < (int) MAX_COPREG) rreg = &crx_copregtab[r-MAX_REG]; } Change getreg_image's argument type to int and replace fragP->fr_literal with &fragP->fr_literal[0] to silence GCC 10 warning. PR gas/26044 * config/tc-crx.c (getreg_image): Change argument type to int. (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26 21:46:26 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26044
* config/tc-crx.c (getreg_image): Change argument type to int.
(md_convert_frag): Replace fragP->fr_literal with
&fragP->fr_literal[0].
tc-score.c: Replace overlapping sprintf with memmove Fix GCC 10 warning: gas/config/tc-score.c:4575:6: error: ‘sprintf’ argument 3 may overlap destination object ‘keep_data’ [-Werror=restrict] 4575 | sprintf (append_str, "bne %s", keep_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ PR gas/26044 * onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping sprintf with memmove.
2020-05-26 21:09:54 +08:00
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26044
* onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping
sprintf with memmove.
gas: Silence GCC 10 warning on tc-mcore.c * config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26 10:37:54 +08:00
2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal
with &fragP->fr_literal[0].
tc-cr16.c: Use memmove to concatenate 2 overlapping strings PR gas/26041 * config/tc-cr16.c (md_assemble): Use memmove to concatenate 2 overlapping strings.
2020-05-26 10:29:22 +08:00
2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26041
* config/tc-cr16.c (md_assemble): Use memmove to concatenate
2 overlapping strings.
gas: Silence GCC 10 warning on tc-cr16.c * config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26 07:17:50 +08:00
2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal
with &fragP->fr_literal[0].
gas: Update fr_literal access in frag for GCC 10 When access fr_literal in struct frag { ... /* Data begins here. */ char fr_literal[1]; }; with char *buf = fragp->fr_fix + fragp->fr_literal; GCC 10 gave gas/config/tc-csky.c: In function ‘md_convert_frag’: gas/config/tc-csky.c:4507:9: error: writing 1 byte into a region of size 0 [-Werror=stringop-overflow=] 4507 | buf[1] = BYTE_1 (CSKYV1_INST_SUBI | (7 << 4)); | ^ Change char *buf = fragp->fr_fix + fragp->fr_literal; to char *buf = fragp->fr_fix + &fragp->fr_literal[0]; to silence GCC 10 warning. * config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal with &fragp->fr_literal[0]. * config/tc-microblaze.c (md_apply_fix): Likewise. * config/tc-sh.c (md_convert_frag): Likewise.
2020-05-25 19:50:56 +08:00
2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal
with &fragp->fr_literal[0].
* config/tc-microblaze.c (md_apply_fix): Likewise.
* config/tc-sh.c (md_convert_frag): Likewise.
RISC-V: Gas inserts cfa relocs in wrong section. The frag code makes a distinction between inserting frags before the frag chains are chained together and afterward. After chaining, we need to set now_seg before creating the frag. tc-xtensa.c has a function called fix_new_exp_in_seg that handles this right, but switches segments twice each time it is called. In this case, we can inline it and pull the save and restore out of the loop to get better code. gas/ PR 26025 * config/tc-riscv.c (riscv_pre_output_hook): Change s type from const asection to segT. New locals seg and subseg. Call subseg_set before fix_new_exp. Call subseg_set after loop to restore original values.
2020-05-25 07:42:21 +08:00
2020-05-24 Jim Wilson <jimw@sifive.com>
PR 26025
* config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
asection to segT. New locals seg and subseg. Call subseg_set before
fix_new_exp. Call subseg_set after loop to restore original values.
Replace "if (x) free (x)" with "free (x)", gas * atof-generic.c: Replace "if (x) free (x)" with "free (x)" throughout. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-tic30.c: Likewise. * ecoff.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * testsuite/gas/all/test-gen.c: Likewise.
2020-05-20 21:19:01 +08:00
2020-05-21 Alan Modra <amodra@gmail.com>
* atof-generic.c: Replace "if (x) free (x)" with "free (x)"
throughout.
* config/obj-elf.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-tic30.c: Likewise.
* ecoff.c: Likewise.
* read.c: Likewise.
* stabs.c: Likewise.
* symbols.c: Likewise.
* testsuite/gas/all/test-gen.c: Likewise.
[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options. We can still use -march to choose the version for each extensions, so there is no need to add these. 2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...]. Unlike the architecture string has specified by spec, ther is no need to do the same thing for options. 3. Spilt the patches to reduce the burdens of review. [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions to [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default. [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version. to [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version. [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version. 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c. The behavior is same as comparing the choosen privilege spec. include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean. (enum riscv_isa_spec_class): New enum class. All supported ISA spec belong to one of the class (struct riscv_ext_version): New structure holds version information for the specific ISA. * opcode/riscv-opc.h (DECLARE_CSR): There are two version information, define_version and abort_version. The define_version means which privilege spec is started to define the CSR, and the abort_version means which privilege spec is started to abort the CSR. If the CSR is valid for the newest spec, then the abort_version should be PRIV_SPEC_CLASS_DRAFT. (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR. * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define the current supported privilege spec versions. (struct riscv_csr_extra): Add new fields to store more information about the CSR. We use these information to find the suitable CSR address when user choosing a specific privilege spec. binutils * dwarf.c: Updated since DECLARE_CSR is changed. opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store all information about the supported spec and the corresponding ISA versions. Currently, only Zicsr is supported to verify the correctness of Z sub extension settings. Others will be supported in the future patches. (struct isa_spec_t, isa_specs): List for all supported ISA spec classes and the corresponding strings. (riscv_get_isa_spec_class): New function. Get the corresponding ISA spec class by giving a ISA spec string. * riscv-opc.c (struct priv_spec_t): New structure. (struct priv_spec_t priv_specs): List for all supported privilege spec classes and the corresponding strings. (riscv_get_priv_spec_class): New function. Get the corresponding privilege spec class by giving a spec string. (riscv_get_priv_spec_name): New function. Get the corresponding privilege spec string by giving a CSR version class. * riscv-dis.c: Updated since DECLARE_CSR is changed. * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR according to the chosen version. Build a hash table riscv_csr_hash to store the valid CSR for the chosen pirv verison. Dump the direct CSR address rather than it's name if it is invalid. (parse_riscv_dis_option_without_args): New function. Parse the options without arguments. (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to parse the options without arguments first, and then handle the options with arguments. Add the new option -Mpriv-spec, which has argument. * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated priv attributes according to the -mpriv-spec option. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function get_default_version. It is used to find the default version for the specific extension. * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters default_major_version and default_minor_version. Add new bfd_boolean parameter *use_default_version. Set it to TRUE if we need to call the callback rps->get_default_version to find the default version. (riscv_parse_std_ext): Call rps->get_default_version if we fail to find the default version in riscv_parsing_subset_version, and then call riscv_add_subset to add the subset into subset list. (riscv_parse_prefixed_ext): Likewise. (riscv_std_z_ext_strtab): Support Zicsr extensions. * elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the strings rather than characters. riscv_merge_arch_attr_info): The callback function get_default_version is only needed for assembler, so set it to NULL int the linker. * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): Static variables which are used to set the ISA extensions. You can use -march (or ELF build attributes) and -misa-spec to set them, respectively. (ext_version_hash): The hash table used to handle the extensions with versions. (init_ext_version_hash): Initialize the ext_version_hash according to riscv_ext_version_table. (riscv_get_default_ext_version): The callback function of riscv_parse_subset_t. According to the choosed ISA spec, get the default version for the specific extension. (riscv_set_arch): Set the callback function. (enum options, struct option md_longopts): Add new option -misa-spec. (md_parse_option): Do not call riscv_set_arch for -march. We will call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class to set default_isa_spec class. (riscv_after_parse_args): Call init_ext_version_hash to initialize the ext_version_hash, and then call riscv_set_arch to set the architecture with versions according to default_arch_with_ext. * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for x extensions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we already set it's version to 2p1 by march, so no need to use the default 2p2 version. For m-ext, we do not set the version by -march and ELF arch attribute, so set the default 2p0 to it. For zicsr, it is not defined in ISA spec 2p2, so set 0p0 to it. * testsuite/gas/riscv/attribute-10.d: New testcase. The version of zicsr is 2p0 according to ISA spec 20191213. * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. You can set them by configure options --with-arch and --with-isa-spec, respectively. (riscv_set_default_isa_spec): New function used to set the default ISA spec. (md_parse_option): Call riscv_set_default_isa_spec rather than call riscv_get_isa_spec_class directly. (riscv_after_parse_args): If the -isa-spec is not set, then we set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by calling riscv_set_default_isa_spec. * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since the --with-isa-spec may be set to different ISA spec. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * configure.ac: Add configure options, --with-arch and --with-isa-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (default_priv_spec): Static variable which is used to check if the CSR is valid for the chosen privilege spec. You can use -mpriv-spec to set it. (enum reg_class): We now get the CSR address from csr_extra_hash rather than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. (riscv_init_csr_hashes): Only need to initialize one hash table csr_extra_hash. (riscv_csr_class_check): Change the return type to void. Don't check the ISA dependency if -mcsr-check isn't set. (riscv_csr_version_check): New function. Check and find the CSR address from csr_extra_hash, according to default_priv_spec. Report warning for the invalid CSR if -mcsr-check is set. (reg_csr_lookup_internal): Updated. (reg_lookup_internal): Likewise. (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. (md_parse_option): Call riscv_set_default_priv_version to set default_priv_spec. (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default privilege spec to the newest one. (enum riscv_csr_class, struct riscv_csr_extra): Move them to include/opcode/riscv.h. * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want to check the ISA dependency for CSR, so fix the spec version by adding -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some version warnings for the test case. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. Check whether the CSR is valid when privilege version 1.9 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. Check whether the CSR is valid when privilege version 1.9.1 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. Check whether the CSR is valid when privilege version 1.10 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. Check whether the CSR is valid when privilege version 1.11 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option setting. You can set it by configure option --with-priv-spec. (riscv_set_default_priv_spec): New function used to set the default privilege spec. (md_parse_option): Call riscv_set_default_priv_spec rather than call riscv_get_priv_spec_class directly. (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by calling riscv_set_default_priv_spec. * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since the --with-priv-spec may be set to different privilege spec. * testsuite/gas/riscv/priv-reg.d: Likewise. * configure.ac: Add configure option --with-priv-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg.d: Removed. * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the CSR according to the priv spec 1.9. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the CSR according to the priv spec 1.9.1. * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the CSR according to the priv spec 1.10. * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the CSR according to the priv spec 1.11. * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise.
2020-05-21 00:22:48 +08:00
2020-05-20 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
Power10 dcbf, sync, and wait extensions. opcodes/ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new WC values on POWER10 sync, dcbf and wait instructions. (insert_pl, extract_pl): New functions. (L2OPT, LS, WC): Use insert_ls and extract_ls. (LS3): New , 3-bit L for sync. (LS3, L3OPT): New, 3-bit L for sync and dcbf. (SC2, PL): New, 2-bit SC and PL for sync and wait. (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. (XOPL3, XWCPL, XSYNCLS): New opcode macros. (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. <wait>: Enable PL operand on POWER10. <dcbf>: Enable L3OPT operand on POWER10. <sync>: Enable SC2 operand on POWER10. gas/ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, sync, wait, waitrsv>: Add tests. * testsuite/gas/ppc/power10.d: Likewise.
2020-05-20 07:09:51 +08:00
2020-05-19 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
sync, wait, waitrsv>: Add tests.
* testsuite/gas/ppc/power10.d: Likewise.
Fix the ARM assembler to generate a Realtime profile for armv8-r. PR 25992 gas * config/tc-arm.c : Add arm_ext_v8r feature. (it_fsm_post_encode): Check arm_ext_v8r feature. (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature. include * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-19 19:45:42 +08:00
2020-05-19 Alexander Fedotov <alfedotov@gmail.com>
PR 25992
* config/tc-arm.c : Add arm_ext_v8r feature.
(it_fsm_post_encode): Check arm_ext_v8r feature.
(get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.
Use bfd_get_filename throughout gas * write.c (write_contents): Use bfd_get_filename rather than accessing bfd->filename directly. Use bfd_section_name rather than accessing section->name directly.
2020-05-19 11:25:27 +08:00
2020-05-19 Alan Modra <amodra@gmail.com>
* write.c (write_contents): Use bfd_get_filename rather than
accessing bfd->filename directly. Use bfd_section_name rather
than accessing section->name directly.
Clear all local_symbol.lsy_flags * symbols.c (local_symbol_make): Init all of lsy_flags.
2020-05-18 13:00:06 +08:00
2020-05-19 Alan Modra <amodra@gmail.com>
* symbols.c (local_symbol_make): Init all of lsy_flags.
Re: Fix tight loop on recursively-defined symbols sy_resolving ought to not be set for a struct local_symbol, but it is apparent from local_symbol_make that the field is not initialised. * symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK before looking at add_symbol->sy_flags.sy_resolving.
2020-05-18 12:00:59 +08:00
2020-05-18 Alan Modra <amodra@gmail.com>
* symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK
before looking at add_symbol->sy_flags.
Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they are invalid in SGX enclaves. gas/ChangeLog * gas/config/tc-i386.c: Not handle lret/iret. * gas/testsuite/gas/i386/lfence-ret-a.d: Adjust testcase. * gas/testsuite/gas/i386/lfence-ret-b.d: Ditto. * gas/testsuite/gas/i386/lfence-ret-c.d: Ditto. * gas/testsuite/gas/i386/lfence-ret-d.d: Ditto. * gas/testsuite/gas/i386/lfence-ret.s: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret.s: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
2020-05-09 15:02:50 +08:00
2020-05-18 Hongtao Liu <hongtao.liu@intel.com>
* config/tc-i386.c: Not handle lret/iret.
* testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
* testsuite/gas/i386/lfence-ret-b.d: Ditto.
* testsuite/gas/i386/lfence-ret-c.d: Ditto.
* testsuite/gas/i386/lfence-ret-d.d: Ditto.
* testsuite/gas/i386/lfence-ret.s: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
Fix tight loop on recursively-defined symbols This patch fixes a bug in GAS where the assembler enters a tight loop when attempting to resolve recursively-defined symbols, e.g. when trying to assemble "a=a". This is a regression introduced between binutils 2.32 and 2.33, by commit 1903f1385bff9 * symbols.c (struct local_symbol): Update comment. (resolve_symbol_value): For resolved symbols equated to other symbols, verify that the referenced symbol is not a local_symbol before accessing sy_value. Don't leave symbol loops during finalize_syms resolution. * testsuite/gas/all/assign-bad-recursive.d: New test. * testsuite/gas/all/assign-bad-recursive.l: Error output for test. * testsuite/gas/all/assign-bad-recursive.s: Assembly for test. * testsuite/gas/all/gas.exp: Run it.
2020-05-15 16:36:05 +08:00
2020-05-15 Alan Modra <amodra@gmail.com>
Alex Coplan <alex.coplan@arm.com>
* symbols.c (struct local_symbol): Update comment.
(resolve_symbol_value): For resolved symbols equated to other
symbols, verify that the referenced symbol is not a local_symbol
before accessing sy_value. Don't leave symbol loops during
finalize_syms resolution.
* testsuite/gas/all/assign-bad-recursive.d: New test.
* testsuite/gas/all/assign-bad-recursive.l: Error output for test.
* testsuite/gas/all/assign-bad-recursive.s: Assembly for test.
* testsuite/gas/all/gas.exp: Run it.
Update Swedish translation for the gas sub-directory and a new Serbian translation for the gold sub-directory.
2020-05-14 18:26:26 +08:00
2020-05-14 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Power10 VSX scalar min-max-compare quad precision operations opcodes/ * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, xsmaxcqp, xsmincqp. gas/ * testsuite/gas/ppc/scalarquad.d, * testsuite/gas/ppc/scalarquad.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:19:29 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/scalarquad.d,
* testsuite/gas/ppc/scalarquad.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 VSX load/store rightmost element operations opcodes/ * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, stxvrbx, stxvrhx, stxvrwx, stxvrdx. gas/ * testsuite/gas/ppc/rightmost.d, * testsuite/gas/ppc/rightmost.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:18:29 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/rightmost.d,
* testsuite/gas/ppc/rightmost.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 test lsb by byte operation opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. gas/ * testsuite/gas/ppc/xvtlsbb.d, * testsuite/gas/ppc/xvtlsbb.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:17:38 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/xvtlsbb.d,
* testsuite/gas/ppc/xvtlsbb.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 string operations opcodes/ * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. gas/ * testsuite/gas/ppc/stringop.d, * testsuite/gas/ppc/stringop.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:16:45 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/stringop.d,
* testsuite/gas/ppc/stringop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 Set boolean extension opcodes/ * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New mnemonics. gas/ * testsuite/gas/ppc/set_bool.d, * testsuite/gas/ppc/set_bool.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:15:42 +08:00
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/set_bool.d,
* testsuite/gas/ppc/set_bool.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 bit manipulation operations opcodes/ * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. (prefix_opcodes): Add xxeval. gas/ * testsuite/gas/ppc/bitmanip.d, * testsuite/gas/ppc/bitmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:14:25 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/bitmanip.d,
* testsuite/gas/ppc/bitmanip.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 VSX PCV generate operations opcodes/ * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, xxgenpcvwm, xxgenpcvdm. gas/ * testsuite/gas/ppc/genpcv.d, * testsuite/gas/ppc/genpcv.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:13:15 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/genpcv.d,
* testsuite/gas/ppc/genpcv.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 VSX Mask Manipulation Operations opcodes/ * ppc-opc.c (MP, VXVAM_MASK): Define. (VXVAPS_MASK): Use VXVA_MASK. (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, vcntmbb, vcntmbh, vcntmbw, vcntmbd. gas/ * testsuite/gas/ppc/maskmanip.d, * testsuite/gas/ppc/maskmanip.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:11:57 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/maskmanip.d,
* testsuite/gas/ppc/maskmanip.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 Reduced precision outer product operations include/ * opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): New functions. (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, YMSK2, XA6a, XA6ap, XB6a entries. (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. (PPCVSX4): Define. (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. gas/ * config/tc-ppc.c (pre_defined_registers): Add accumulators. (md_assemble): Check acc specified in correct operand. * testsuite/gas/ppc/outerprod.d, * testsuite/gas/ppc/outerprod.s, * testsuite/gas/ppc/vsx4.d, * testsuite/gas/ppc/vsx4.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11 08:10:42 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
Peter Bergner <bergner@linux.ibm.com>
* config/tc-ppc.c (pre_defined_registers): Add accumulators.
(md_assemble): Check acc specified in correct operand.
* testsuite/gas/ppc/outerprod.d,
* testsuite/gas/ppc/outerprod.s,
* testsuite/gas/ppc/vsx4.d,
* testsuite/gas/ppc/vsx4.s: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
Power10 SIMD permute class operations opcodes/ * ppc-opc.c (insert_imm32, extract_imm32): New functions. (insert_xts, extract_xts): New functions. (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. (VXRC_MASK, VXSH_MASK): Define. (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, xxblendvh, xxblendvw, xxblendvd, xxpermx. gas/ * testsuite/gas/ppc/simd_perm.d, * testsuite/gas/ppc/simd_perm.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:07:14 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/simd_perm.d,
* testsuite/gas/ppc/simd_perm.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 128-bit binary integer operations opcodes/ * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. gas/ * testsuite/gas/ppc/int128.d, * testsuite/gas/ppc/int128.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:06:11 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/int128.d,
* testsuite/gas/ppc/int128.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 VSX 32-byte storage access bfd/ * elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp. opcodes/ * ppc-opc.c (insert_xtp, extract_xtp): New functions. (XTP, DQXP, DQXP_MASK): Define. (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. (prefix_opcodes): Add plxvp and pstxvp. gas/ * testsuite/gas/ppc/vsx_32byte.d, * testsuite/gas/ppc/vsx_32byte.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. ld/ * testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp. * testsuite/ld-powerpc/pcrelopt.d: Update.
2020-05-11 08:04:49 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/vsx_32byte.d,
* testsuite/gas/ppc/vsx_32byte.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 vector integer multiply, divide, modulo insns opcodes/ * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. gas/ * testsuite/gas/ppc/vec_mul.s, * testsuite/gas/ppc/vec_mul.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:02:56 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/vec_mul.s,
* testsuite/gas/ppc/vec_mul.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 byte reverse instructions opcodes/ * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics. gas/ * testsuite/gas/ppc/byte_rev.d, * testsuite/gas/ppc/byte_rev.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 08:01:40 +08:00
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/byte_rev.d,
* testsuite/gas/ppc/byte_rev.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Power10 Copy/Paste Extensions opcodes/ * opcodes/ppc-opc.c (insert_l1opt, extract_l1opt): New functions. (L1OPT): Define. (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10. gas/ * testsuite/gas/ppc/power10.d: Add paste. tests. * testsuite/gas/ppc/power10.s: Likewise.
2020-05-11 08:00:19 +08:00
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/power10.d: Add paste. tests.
* testsuite/gas/ppc/power10.s: Likewise.
Power10 Add new L operand to the slbiag instruction opcodes/ * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand. gas/ * testsuite/gas/ppc/power10.s: New test. * testsuite/gas/ppc/power10.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 07:57:48 +08:00
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/power10.s: New test.
* testsuite/gas/ppc/power10.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
PowerPC Rename powerxx to power10 Now that ISA3.1 is out we can finish with the powerxx silliness. bfd/ * elf64-ppc.c: Rename powerxx to power10 throughout. gas/ * config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10 renaming. * testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/gas/ppc/prefix-pcrel.d: Likewise. * testsuite/gas/ppc/prefix-reloc.d: Likewise. gold/ * powerpc.cc: Rename powerxx to power10 throughout. include/ * elf/ppc64.h: Update comment. * opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX. ld/ * testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Likewise. * testsuite/ld-powerpc/tlsgd.d: Likewise. * testsuite/ld-powerpc/tlsie.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power10" entry. (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2020-05-11 07:54:14 +08:00
2020-05-11 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
Updated Swedish translation for the gas sub-directory
2020-05-06 21:17:36 +08:00
2020-05-06 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Section "3.1 Preprocessing" of the online GAS manual has a wrong reference to "Using GNU CC". This fixes that link. PR 25927 * doc/as.texi (Preprocessing): Replace cross reference to not existant document with a URL to the equivalent page in the GCC manual.
2020-05-06 20:21:02 +08:00
2020-05-06 Nick Clifton <nickc@redhat.com>
PR 25927
* doc/as.texi (Preprocessing): Replace cross reference to not
existant document with a URL to the equivalent page in the GCC
manual.
Restore readelf's warnings that describe real problems with the file being examined. Fix bug displaying empty file name tables. binutils* dwarf.c (do_checks): New global variable. (display_formatted_table): Warn about an unexpected number of columns in the table, if checks are enabled. Do not complain about the lack of data following the number of entries in the table if the table is empty. (display_debug_lines_decoded): Only warn about an unexpected number of columns in a table if checks are enabled. * dwarf.h (do_checks): Add a prototype. * elfcomm.c (error): Remove weak attribute. (warn): Likewise. * readelf.c (do_checks): Delete. (warn): Delete. (process_section_headers): Only warn about empty sections if checks are enabled. gas * dwarf2dbg.c (out_dir_and_file_list): Add comments describing the construction of a DWARF-5 directory name table. * testsuite/gas/elf/pr25917.d: Update expected output.
2020-05-05 23:16:03 +08:00
2020-05-05 Nick Clifton <nickc@redhat.com>
* dwarf2dbg.c (out_dir_and_file_list): Add comments describing the
construction of a DWARF-5 directory name table.
* testsuite/gas/elf/pr25917.d: Update expected output.
[GAS] change of ELF flags initial value in rx-linux * config/tc-rx.c (elf_flags): Initialize for non-linux targets. (md_parse_option): Remove initialization of elf_flags.
2020-05-05 17:19:41 +08:00
2020-05-05 Gunther Nikl <gnikl@justmail.de>
* config/tc-rx.c (elf_flags): Initialize for non-linux targets.
(md_parse_option): Remove initialization of elf_flags.
GAS: Do not create an entry for the default directory if the directory table is empty. Improve readelf's decoding of empty directory and file name tables. PR 25917 * dwarf.c (display_debug_lines_decoded): Warn if encountering a supicious number of entries for DWARF-5 format directory and file name tables. Do not display file name table header if the table is empty. Do not allocate space for empty tables.
2020-05-04 20:50:05 +08:00
gas: PR 25863: Fix scalar vmul inside it block when assembling for MVE This fixes PR 25863 by fixing the condition in the parsing of vmul in do_mve_vmull. It also simplifies the code in there fixing latent issues that would lead to NEON code being accepted when it shouldn't. gas/ChangeLog: 2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com> PR gas/25863 * config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul. * testsuite/gas/arm/mve-scalar-vmult-it.d: New test. * testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
2020-05-04 20:05:42 +08:00
2020-05-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25863
* config/tc-arm.c (do_mve_vmull): Fix scalar and NEON parsing of vmul.
* testsuite/gas/arm/mve-scalar-vmult-it.d: New test.
* testsuite/gas/arm/mve-scalar-vmult-it.s: New test.
Fix an illegal memory access in the assembler when generating a DWARF5 file/directory table with no entries. PR 25917 * dwarf2dbg.c (out_dir_and_file_list): Check for the directory table's existence before looking at its entries. * testsuite/gas/elf/pr25917.s: New test source file. * testsuite/gas/elf/pr25917.d: New test driver. * testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
2020-05-04 17:19:38 +08:00
2020-05-04 Nick Clifton <nickc@redhat.com>
PR 25917
* dwarf2dbg.c (out_dir_and_file_list): Check for the directory
table's existence before looking at its entries.
GAS: Do not create an entry for the default directory if the directory table is empty. Improve readelf's decoding of empty directory and file name tables. PR 25917 * dwarf.c (display_debug_lines_decoded): Warn if encountering a supicious number of entries for DWARF-5 format directory and file name tables. Do not display file name table header if the table is empty. Do not allocate space for empty tables.
2020-05-04 20:50:05 +08:00
Also do not emit a default directory entry if there are no
directories in use.
Fix an illegal memory access in the assembler when generating a DWARF5 file/directory table with no entries. PR 25917 * dwarf2dbg.c (out_dir_and_file_list): Check for the directory table's existence before looking at its entries. * testsuite/gas/elf/pr25917.s: New test source file. * testsuite/gas/elf/pr25917.d: New test driver. * testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
2020-05-04 17:19:38 +08:00
* testsuite/gas/elf/pr25917.s: New test source file.
* testsuite/gas/elf/pr25917.d: New test driver.
* testsuite/gas/elf/elf.exp (run_elf_list_test): Run the new test.
AArch64: add GAS support for UDF instruction binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new disassembly. * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise. ld/ * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly. * testsuite/ld-aarch64/farcall-b-section.d: Likewise. * testsuite/ld-aarch64/farcall-back.d: Likewise. * testsuite/ld-aarch64/farcall-bl-section.d: Likewise. gas/ * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED. (parse_operands): Implement for AARCH64_OPND_UNDEFINED. * testsuite/gas/aarch64/udf.s: New. * testsuite/gas/aarch64/udf.d: New. * testsuite/gas/aarch64/udf-invalid.s: New. * testsuite/gas/aarch64/udf-invalid.l: New. * testsuite/gas/aarch64/udf-invalid.d: New. include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED. opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. * aarch64-opc.c (fields): Add entry for FLD_imm16_2. (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED. * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for FLD_imm16_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-04-30 22:47:30 +08:00
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (fix_insn): Implement for
AARCH64_OPND_UNDEFINED.
(parse_operands): Implement for AARCH64_OPND_UNDEFINED.
* testsuite/gas/aarch64/udf.s: New.
* testsuite/gas/aarch64/udf.d: New.
* testsuite/gas/aarch64/udf-invalid.s: New.
* testsuite/gas/aarch64/udf-invalid.l: New.
* testsuite/gas/aarch64/udf-invalid.d: New.
ld: Add rx-linux emulation. gas: Change ELF flags initial value in rx-linux ld * emulparams/elf32rx_linux.sh: New rx-linux emulation. * emultempl/rxlinux.em: New. * configure.tgt: Add rx-linux. * Makefile.am: Add eelf32rx_linux.c * Makefile.in: Regenerate. gas * config/tc-rx.c (elf_flags): Reset default value. (md_parse_option): For rx-elf Initialize elf_flags with RX_ABI.
2020-04-30 20:35:37 +08:00
2020-04-30 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/tc-rx.c (elf_flags): Reset default value.
(md_parse_option): For rx-elf Initialize elf_flags with RX_ABI.
xtensa: gas: support optional immediate simcall parameter Starting with RH.0 release Xtensa ISA adds immediate parameter to simcall opcode. For assembly source compatibility treat "simcall" instruction without parameter as "simcall 0" when parameter is required. 2020-04-29 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0 if it's not defined. (microarch_earliest): New static variable. (xg_translate_idioms): Translate "simcall" to "simcall 0" when simcall opcode has mandatory parameter. (xg_init_global_config): Initialize microarch_earliest.
2020-04-28 19:15:05 +08:00
2020-04-29 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (XTENSA_MARCH_EARLIEST): Define macro as 0
if it's not defined.
(microarch_earliest): New static variable.
(xg_translate_idioms): Translate "simcall" to "simcall 0" when
simcall opcode has mandatory parameter.
(xg_init_global_config): Initialize microarch_earliest.
Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand. PR 22699 opcodes * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use IMM0_8S for arithmetic insns and IMM0_8U for logical insns. * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add IMM0_8U case. gas * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to IMM0_8S and add support for IMM0_8U. * testsuite/gas/sh/sh4a.s: Add test of a logical insn using an unsigned 8-bit immediate. * testsuite/gas/sh/sh4a.d: Extended expected disassembly.
2020-04-29 20:13:55 +08:00
2020-04-29 Nick Clifton <nickc@redhat.com>
PR 22699
* config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
IMM0_8S and add support for IMM0_8U.
* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
unsigned 8-bit immediate.
* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
Update expected disassembly after recent update. PR 22699 * testsuite/gas/sh/sh4al-dsp.d: Update expected disassembly.
2020-04-30 00:18:56 +08:00
* testsuite/gas/sh/sh4al-dsp.d: Update expected disassembly.
Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand. PR 22699 opcodes * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use IMM0_8S for arithmetic insns and IMM0_8U for logical insns. * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add IMM0_8U case. gas * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to IMM0_8S and add support for IMM0_8U. * testsuite/gas/sh/sh4a.s: Add test of a logical insn using an unsigned 8-bit immediate. * testsuite/gas/sh/sh4a.d: Extended expected disassembly.
2020-04-29 20:13:55 +08:00
x86: Add i386 PE big-object support The 64-bit version of binutils got support for the PE COFF BIG OBJ format a couple of years ago. The BIG OBJ format is a slightly different COFF format which extends the size of the number of section field in the header from a uint16_t to a uint32_t and so greatly increases the number of sections allowed. However the 32-bit version of bfd never got support for this. The GHC Haskell compiler generates a great deal of symbols due to it's use of -ffunction-sections and -fdata-sections. This meant that we could not build the 32-bit version of the GHC Compiler for many releases now as binutils didn't have this support. This patch adds the support to the 32-bit port of binutils as well and also does come cleanup in the code. bfd/ChangeLog: * coff-i386.c (COFF_WITH_PE_BIGOBJ): New. * coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New. * config.bfd (targ_selvecs): Rename x86_64_pe_be_vec to x86_64_pe_big_vec as it not a big-endian format. (vec i386_pe_big_vec): New. * configure.ac: Likewise. * targets.c: Likewise. * configure: Regenerate. * pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG, COFF_WITH_PE_BIGOBJ): New. * pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG): New. (x86_64_pe_be_vec): Moved. gas/ChangeLog: * NEWS: Add news entry for big-obj. * config/tc-i386.c (i386_target_format): Support new format. * doc/c-i386.texi: Add i386 support. * testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific. * testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well. ld/ChangeLog: * pe-dll.c (pe_detail_list): Add pe-bigobj-i386.
2020-04-28 00:39:31 +08:00
2020-04-27 Tamar Christina <tamar.christina@arm.com>
* NEWS: Add news entry for big-obj.
* config/tc-i386.c (i386_target_format): Support new format.
* doc/c-i386.texi: Add i386 support.
* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.
GAS: Allow automatically assigned entries in the file table to be reassigned if the source file specifically requests to use the assigned slot. PR 25878 * dwarf2dbg.c (struct file_entry): Add auto_assigned field. (assign_file_to_slot): New function. Fills in an entry in the files table. (allocate_filenum): Use new function. (allocate_filename_to_slot): Use new function. If the specified slot entry is already in use, but was chosen automatically then reassign the automatic entry.
2020-04-27 18:35:25 +08:00
2020-04-27 Nick Clifton <nickc@redhat.com>
PR 25878
* dwarf2dbg.c (struct file_entry): Add auto_assigned field.
(assign_file_to_slot): New function. Fills in an entry in the
files table.
(allocate_filenum): Use new function.
(allocate_filename_to_slot): Use new function. If the specified
slot entry is already in use, but was chosen automatically then
reassign the automatic entry.
Improve -mlfence-after-load 1.Implict load for POP/POPF/POPA/XLATB, no load for Anysize insns 2. Add -mlfence-before-ret=shl/yes, adjust operand size of or/not/shl according to ret's. 3. Issue warning for REP CMPS/SCAS since they would affect control flow behavior. 4. Adjust testcases and documents. gas/Changelog: * config/tc-i386.c (lfence_before_ret_shl): New member. (load_insn_p): implict load for POP/POPA/POPF/XLATB, no load for Anysize insns. (insert_after_load): Issue warning for REP CMPS/SCAS. (insert_before_before): Handle iret, Handle -mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's, (md_parse_option): Change -mlfence-before-ret=[none|not|or] to -mlfence-before-ret=[none/not/or/shl/yes]. Enable -mlfence-before-ret=shl when -mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option. (md_show_usage): Ditto. * doc/c-i386.texi: Ditto. * testsuite/gas/i386/i386.exp: Add new testcases. * testsuite/gas/i386/lfence-load-b.d: New. * testsuite/gas/i386/lfence-load-b.e: New. * testsuite/gas/i386/lfence-load.d: Modified. * testsuite/gas/i386/lfence-load.e: New. * testsuite/gas/i386/lfence-load.s: Modified. * testsuite/gas/i386/lfence-ret-a.d: Modified. * testsuite/gas/i386/lfence-ret-b.d: Modified. * testsuite/gas/i386/lfence-ret-c.d: New. * testsuite/gas/i386/lfence-ret-d.d: New. * testsuite/gas/i386/lfence-ret.s: Modified. * testsuite/gas/i386/x86-64-lfence-load-b.d: New. * testsuite/gas/i386/x86-64-lfence-load.d: Modified. * testsuite/gas/i386/x86-64-lfence-load.s: Modified. * testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified. * testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified. * testsuite/gas/i386/x86-64-lfence-ret-c.d: New. * testsuite/gas/i386/x86-64-lfence-ret-d.d: New * testsuite/gas/i386/x86-64-lfence-ret-e.d: New. * testsuite/gas/i386/x86-64-lfence-ret.e: New. * testsuite/gas/i386/x86-64-lfence-ret.s: New.
2020-03-16 11:03:12 +08:00
2020-04-26 Hongtao Liu <hongtao.liu@intel.com
* config/tc-i386.c (lfence_before_ret_shl): New member.
(load_insn_p): implict load for POP/POPA/POPF/XLATB, no load
for Anysize insns.
(insert_after_load): Issue warning for REP CMPS/SCAS.
(insert_before_before): Handle iret, Handle
-mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's,
(md_parse_option): Change -mlfence-before-ret=[none|not|or] to
-mlfence-before-ret=[none/not/or/shl/yes].
Enable -mlfence-before-ret=shl when
-mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option.
(md_show_usage): Ditto.
* doc/c-i386.texi: Ditto.
* testsuite/gas/i386/i386.exp: Add new testcases.
* testsuite/gas/i386/lfence-load-b.d: New.
* testsuite/gas/i386/lfence-load-b.e: New.
* testsuite/gas/i386/lfence-load.d: Modified.
* testsuite/gas/i386/lfence-load.e: New.
* testsuite/gas/i386/lfence-load.s: Modified.
* testsuite/gas/i386/lfence-ret-a.d: Modified.
* testsuite/gas/i386/lfence-ret-b.d: Modified.
* testsuite/gas/i386/lfence-ret-c.d: New.
* testsuite/gas/i386/lfence-ret-d.d: New.
* testsuite/gas/i386/lfence-ret.s: Modified.
* testsuite/gas/i386/x86-64-lfence-load-b.d: New.
* testsuite/gas/i386/x86-64-lfence-load.d: Modified.
* testsuite/gas/i386/x86-64-lfence-load.s: Modified.
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified.
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified.
* testsuite/gas/i386/x86-64-lfence-ret-c.d: New.
* testsuite/gas/i386/x86-64-lfence-ret-d.d: New
* testsuite/gas/i386/x86-64-lfence-ret-e.d: New.
* testsuite/gas/i386/x86-64-lfence-ret.e: New.
* testsuite/gas/i386/x86-64-lfence-ret.s: New.
xtensa: fix PR ld/25861 Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences (subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32} for negative differences (subtracted symbol follows diminished symbol). Don't generate XTENSA_DIFF relocations in the assembler, generate XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position. Handle XTENSA_DIFF in BFD for compatibility with old object files. Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value as unsigned. 2020-04-22 Max Filippov <jcmvbkbc@gmail.com> bfd/ * bfd-in2.h: Regenerated. * elf32-xtensa.c (elf_howto_table): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. (elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc) (relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. * libbfd.h (bfd_reloc_code_real_names): Add names for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. * reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. binutils/ * readelf.c (is_none_reloc): Recognize BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. gas/ * config/tc-xtensa.c (md_apply_fix): Replace BFD_RELOC_XTENSA_DIFF{8,16,32} generation with BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32} generation. * testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16 with BFD_RELOC_XTENSA_PDIFF16 in the expected output. include/ * elf/xtensa.h (elf_xtensa_reloc_type): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. ld/ * testsuite/ld-xtensa/relax-loc.d: New test definition. * testsuite/ld-xtensa/relax-loc.s: New test source. * testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-04-20 10:04:41 +08:00
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
PR ld/25861
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
.symver fixes * config/obj-elf.c (elf_frob_symbol): Unconditionally remove symbol for ".symver .. remove". * doc/as.texi (.symver): Update. * testsuite/gas/symver/symver11.s: Make foo weak. * testsuite/gas/symver/symver11.d: Expect an error. * testsuite/gas/symver/symver7.d: Allow other random symbols.
2020-04-22 10:22:13 +08:00
2020-04-22 Alan Modra <amodra@gmail.com>
* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
symbol for ".symver .. remove".
* doc/as.texi (.symver): Update.
* testsuite/gas/symver/symver11.s: Make foo weak.
* testsuite/gas/symver/symver11.d: Expect an error.
* testsuite/gas/symver/symver7.d: Allow other random symbols.
symver11.s: Add ".balign 8" Add ".balign 8" to avoid symver11.s:9: Error: misaligned data for sh targets. * testsuite/gas/symver/symver11.s: Add ".balign 8".
2020-04-22 09:21:56 +08:00
2020-04-21 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/symver/symver11.s: Add ".balign 8".
Disallow PC relative for CMPI on MC68000/10 The MC68000/10 decodes the second operand of CMPI strictly as destination operand, which disallows PC relative addressing, even though the insn doesn't write to the operand. This restriction has only been lifted for the MC68020+ and CPU32. opcodes: PR 25848 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of cmpi only on m68020up and cpu32. gas: PR 25848 * testsuite/gas/m68k/operands.s: Add tests for cmpi. * testsuite/gas/m68k/operands.d: Update. * testsuite/gas/m68k/op68000.d: Update for new error messages.
2020-04-18 20:32:39 +08:00
2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
PR 25848
* testsuite/gas/m68k/operands.s: Add tests for cmpi.
* testsuite/gas/m68k/operands.d: Update.
* testsuite/gas/m68k/op68000.d: Update for new error messages.
BFD: Exclude sections with no content from compress check. The check in bfd_get_full_section_contents is trying to check that we don't allocate more space for a section than the size of the section is on disk. Previously we excluded linker created sections since they didn't have a size on disk. However we also need to exclude sections with no content as well such as the BSS section. Space for these would not have been allocated by the assembler and so the check would incorrectly fail. bfd/ChangeLog: PR binutils/24753 * compress.c (bfd_get_full_section_contents): Exclude sections with no content. gas/ChangeLog: PR binutils/24753 * testsuite/gas/arm/pr24753.d: New test. * testsuite/gas/arm/pr24753.s: New test.
2020-04-21 22:16:21 +08:00
2020-04-21 Tamar Christina <tamar.christina@arm.com>
PR binutils/24753
* testsuite/gas/arm/pr24753.d: New test.
* testsuite/gas/arm/pr24753.s: New test.
gas: Extend .symver directive Extend .symver directive to update visibility of the original symbol and assign one original symbol to different versioned symbols: .symver foo, foo@VERS_1, local # Change foo to a local symbol. .symver foo, foo@VERS_2, hidden # Change foo to a hidden symbol. .symver foo, foo@@VERS_3, remove # Remove foo from symbol table. .symver foo, bar@V1 # Assign foo to bar@V1 and baz@V2. .symver foo, baz@V2 PR gas/23840 PR gas/25295 * NEWS: Mention .symver extension. * config/obj-elf.c (obj_elf_find_and_add_versioned_name): New function. (obj_elf_symver): Call obj_elf_find_and_add_versioned_name to add a version name. Add local, hidden and remove visibility support. (elf_frob_symbol): Handle the list of version names. Update the original symbol to local, hidden or remove it from the symbol table. (elf_frob_file_before_adjust): Handle the list of version names. * config/obj-elf.h (elf_visibility): New. (elf_versioned_name_list): Likewise. (elf_obj_sy): Change local to bitfield. Add rename, bad_version and visibility. Change versioned_name pointer to struct elf_versioned_name_list. * doc/as.texi: Update .symver directive. * testsuite/gas/symver/symver.exp: Run all *.d tests. Add more error checking tests. * testsuite/gas/symver/symver6.d: New file. * testsuite/gas/symver/symver7.d: Likewise. * testsuite/gas/symver/symver7.s: Likewise. * testsuite/gas/symver/symver8.d: Likewise. * testsuite/gas/symver/symver8.s: Likewise. * testsuite/gas/symver/symver9.s: Likewise. * testsuite/gas/symver/symver9a.d: Likewise. * testsuite/gas/symver/symver9b.d: Likewise. * testsuite/gas/symver/symver10.s: Likewise. * testsuite/gas/symver/symver10a.d: Likewise. * testsuite/gas/symver/symver10b.d: Likewise. * testsuite/gas/symver/symver11.d: Likewise. * testsuite/gas/symver/symver11.s: Likewise. * testsuite/gas/symver/symver12.d: Likewise. * testsuite/gas/symver/symver12.s: Likewise. * testsuite/gas/symver/symver13.d: Likewise. * testsuite/gas/symver/symver13.s: Likewise. * testsuite/gas/symver/symver14.d: Likewise. * testsuite/gas/symver/symver14.l: Likewise. * testsuite/gas/symver/symver15.d: Likewise. * testsuite/gas/symver/symver15.l: Likewise. * testsuite/gas/symver/symver6.l: Removed. * testsuite/gas/symver/symver6.s: Updated.
2020-04-21 20:33:04 +08:00
2020-04-21 H.J. Lu <hongjiu.lu@intel.com>
PR gas/23840
PR gas/25295
* NEWS: Mention .symver extension.
* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
function.
(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
add a version name. Add local, hidden and remove visibility
support.
(elf_frob_symbol): Handle the list of version names. Update the
original symbol to local, hidden or remove it from the symbol
table.
(elf_frob_file_before_adjust): Handle the list of version names.
* config/obj-elf.h (elf_visibility): New.
(elf_versioned_name_list): Likewise.
(elf_obj_sy): Change local to bitfield. Add rename, bad_version
and visibility. Change versioned_name pointer to struct
elf_versioned_name_list.
* doc/as.texi: Update .symver directive.
* testsuite/gas/symver/symver.exp: Run all *.d tests. Add more
error checking tests.
* testsuite/gas/symver/symver6.d: New file.
* testsuite/gas/symver/symver7.d: Likewise.
* testsuite/gas/symver/symver7.s: Likewise.
* testsuite/gas/symver/symver8.d: Likewise.
* testsuite/gas/symver/symver8.s: Likewise.
* testsuite/gas/symver/symver9.s: Likewise.
* testsuite/gas/symver/symver9a.d: Likewise.
* testsuite/gas/symver/symver9b.d: Likewise.
* testsuite/gas/symver/symver10.s: Likewise.
* testsuite/gas/symver/symver10a.d: Likewise.
* testsuite/gas/symver/symver10b.d: Likewise.
* testsuite/gas/symver/symver11.d: Likewise.
* testsuite/gas/symver/symver11.s: Likewise.
* testsuite/gas/symver/symver12.d: Likewise.
* testsuite/gas/symver/symver12.s: Likewise.
* testsuite/gas/symver/symver13.d: Likewise.
* testsuite/gas/symver/symver13.s: Likewise.
* testsuite/gas/symver/symver14.d: Likewise.
* testsuite/gas/symver/symver14.l: Likewise.
* testsuite/gas/symver/symver15.d: Likewise.
* testsuite/gas/symver/symver15.l: Likewise.
* testsuite/gas/symver/symver6.l: Removed.
* testsuite/gas/symver/symver6.s: Updated.
[AArch64, Binutils] Add missing TSB instruction This patch implements the TSB instructions: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ tsb-csync-trace-synchronization-barrier Since TSB and PSB both use the same (and only) argument "CSYNC", this patch reuses it for TSB. However, the same argument would imply different value for CRm:Op2 which are anyway fixed values, so I have diverted the inserter/extracter function to dummy versions instead of the "hint" version. The operand checker part still uses the existing infratructure for AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly. gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_barrier_psb): Update error messages to include TSB. * testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests. * testsuite/gas/aarch64/system-2.s: Add new tsb tests. * testsuite/gas/aarch64/system.d: Update. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_none): New. * aarch64-asm.h (ins_none): New declaration. * aarch64-dis.c (aarch64_ext_none): New. * aarch64-dis.h (ext_none): New declaration. * aarch64-opc.c (aarch64_print_operand): Update case for AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_opcode_table): Add tsb. (AARCH64_OPERANDS): Update inserter/extracter for AARCH64_OPND_BARRIER_PSB to use new dummy functions. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-04-20 17:58:16 +08:00
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_barrier_psb): Update error messages
to include TSB.
* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
* testsuite/gas/aarch64/system.d: Update.
[AArch64, Binutils] Make hint space instructions valid for Armv8-a There are a few instruction in AArch64 that are in the HINT space. Any of these instructions should be accepted by the assembler/disassembler at any architecture version. This patch fixes the existing instructions that are not behaving accordingly. I have used all of the instructions mentioned in the following to make the changes: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ hint-hint-instruction gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/bti.d: Update -march option. * testsuite/gas/aarch64/illegal-bti.d: Remove. * testsuite/gas/aarch64/illegal-bti.l: Remove. * testsuite/gas/aarch64/illegal-ras-1.l: Remove esb. * testsuite/gas/aarch64/illegal-ras-1.s: Remove esb. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. (aarch64_feature_ras, RAS): Likewise. (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz, autibsp to be CORE_INSN. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-04-20 17:50:52 +08:00
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/bti.d: Update -march option.
* testsuite/gas/aarch64/illegal-bti.d: Remove.
* testsuite/gas/aarch64/illegal-bti.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.
bfin: allow ".=.+delta" BFIN has lots of instructions that contain "=", so "sym = expression" is disabled for that target. This makes an exception for assignment to dot, fixing the recent regression of ld-scripts/pr18963. * config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
2020-04-17 11:08:19 +08:00
2020-04-17 Alan Modra <amodra@gmail.com>
* config/tc-bfin.h (TC_EQUAL_IN_INSN): Allow assignment to dot.
Stop the MIPS assembler from accepting ifunc symbols. PR 25803 gas * config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS targets. * testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip for the type-2 test. * testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS targets running this test. bfd * elfxx-mips.c (_bfd_mips_elf_adjust_dynamic_symbol): Replace an abort with a more helpful error message.
2020-04-17 01:02:10 +08:00
2020-04-16 Gagan Singh Sidhu <broly@mac.com>
Nick Clifton <nickc@redhat.com>
PR 25803
* config/obj-elf.c (obj_elf_type): Reject ifunc symbols on MIPS
targets.
* testsuite/gas/elf/elf.exp: Add MIPS targets to the list to skip
for the type-2 test.
* testsuite/gas/elf/type-noifunc.e: Update to allow for MIPS
targets running this test.
cpu,gas,opcodes: support for eBPF JMP32 instruction class Add support for the JMP32 class of eBPF instructions. cpu/ChangeLog * bpf.cpu (define-cond-jump-insn): Renamed from djci. (dcji) New version with support for JMP32 gas/ChangeLog * testsuite/gas/bpf/bpf.exp: Run jump32 tests. * testsuite/gas/bpf/jump32.s: New file. * testsuite/gas/bpf/jump32.d: Likewise. opcodes/ChangeLog * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Regenerate. * bpf-opc.h: Likewise.
2020-04-16 15:52:57 +08:00
2020-02-16 David Faust <david.faust@oracle.com>
* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
* testsuite/gas/bpf/jump32.s: New file.
* testsuite/gas/bpf/jump32.d: Likewise.
x86: Correct -mlfence-before-indirect-branch= documentation Replace "after indirect near branch" with "before indirect near branch". * doc/c-i386.texi: Correct -mlfence-before-indirect-branch= documentation.
2020-04-09 10:31:45 +08:00
2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
* doc/c-i386.texi: Correct -mlfence-before-indirect-branch=
documentation.
[PATCH 2/4]: moxie: use generic pcrel support The moxie target header uses md_pcrel_from, thus the local prototype and the macro definition for MD_PCREL_FROM_SECTION are not needed. * config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define. (md_pcrel_from): Remove prototytpe.
2020-04-08 18:11:43 +08:00
2020-04-08 Gunther Nikl <gnikl@justmail.de>
* config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define.
(md_pcrel_from): Remove prototytpe.
[PATCH 3/4]: m32c: remove duplicate define and prototype The m32c target header has a duplicate entry for MD_PCREL_FROM_SECTION. The duplication was present since the initial commit of the port. * config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate define. (md_pcrel_from_section): Remove duplicate prototype.
2020-04-08 18:15:28 +08:00
* config/tc-m32c.h (MD_PCREL_FROM_SECTION): Delete duplicate
define.
(md_pcrel_from_section): Remove duplicate prototype.
[PATCH 4/4]: Add generic prototype for md_pcrel_from_section This patch removes the need for target headers to provide a custom prototype for md_pcrel_from_section. * tc.h (md_pcrel_from_section): Add prototype. * config/tc-aarch64.h (md_pcrel_from_section): Remove prototype. * config/tc-arc.h (md_pcrel_from_section): Likewise. * config/tc-arm.h (md_pcrel_from_section): Likewise. * config/tc-avr.h (md_pcrel_from_section): Likewise. * config/tc-bfin.h (md_pcrel_from_section): Likewise. * config/tc-bpf.h (md_pcrel_from_section): Likewise. * config/tc-csky.h (md_pcrel_from_section): Likewise. * config/tc-d10v.h (md_pcrel_from_section): Likewise. * config/tc-d30v.h (md_pcrel_from_section): Likewise. * config/tc-epiphany.h (md_pcrel_from_section): Likewise. * config/tc-fr30.h (md_pcrel_from_section): Likewise. * config/tc-frv.h (md_pcrel_from_section): Likewise. * config/tc-iq2000.h (md_pcrel_from_section): Likewise. * config/tc-lm32.h (md_pcrel_from_section): Likewise. * config/tc-m32c.h (md_pcrel_from_section): Likewise. * config/tc-m32r.h (md_pcrel_from_section): Likewise. * config/tc-mcore.h (md_pcrel_from_section): Likewise. * config/tc-mep.h (md_pcrel_from_section): Likewise. * config/tc-metag.h (md_pcrel_from_section): Likewise. * config/tc-microblaze.h (md_pcrel_from_section): Likewise. * config/tc-mmix.h (md_pcrel_from_section): Likewise. * config/tc-moxie.h (md_pcrel_from_section): Likewise. * config/tc-msp430.h (md_pcrel_from_section): Likewise. * config/tc-mt.h (md_pcrel_from_section): Likewise. * config/tc-or1k.h (md_pcrel_from_section): Likewise. * config/tc-ppc.h (md_pcrel_from_section): Likewise. * config/tc-rl78.h (md_pcrel_from_section): Likewise. * config/tc-rx.h (md_pcrel_from_section): Likewise. * config/tc-s390.h (md_pcrel_from_section): Likewise. * config/tc-sh.h (md_pcrel_from_section): Likewise. * config/tc-xc16x.h (md_pcrel_from_section): Likewise. * config/tc-xstormy16.h (md_pcrel_from_section): Likewise.
2020-04-08 19:28:10 +08:00
* tc.h (md_pcrel_from_section): Add prototype.
* config/tc-aarch64.h (md_pcrel_from_section): Remove prototype.
* config/tc-arc.h (md_pcrel_from_section): Likewise.
* config/tc-arm.h (md_pcrel_from_section): Likewise.
* config/tc-avr.h (md_pcrel_from_section): Likewise.
* config/tc-bfin.h (md_pcrel_from_section): Likewise.
* config/tc-bpf.h (md_pcrel_from_section): Likewise.
* config/tc-csky.h (md_pcrel_from_section): Likewise.
* config/tc-d10v.h (md_pcrel_from_section): Likewise.
* config/tc-d30v.h (md_pcrel_from_section): Likewise.
* config/tc-epiphany.h (md_pcrel_from_section): Likewise.
* config/tc-fr30.h (md_pcrel_from_section): Likewise.
* config/tc-frv.h (md_pcrel_from_section): Likewise.
* config/tc-iq2000.h (md_pcrel_from_section): Likewise.
* config/tc-lm32.h (md_pcrel_from_section): Likewise.
* config/tc-m32c.h (md_pcrel_from_section): Likewise.
* config/tc-m32r.h (md_pcrel_from_section): Likewise.
* config/tc-mcore.h (md_pcrel_from_section): Likewise.
* config/tc-mep.h (md_pcrel_from_section): Likewise.
* config/tc-metag.h (md_pcrel_from_section): Likewise.
* config/tc-microblaze.h (md_pcrel_from_section): Likewise.
* config/tc-mmix.h (md_pcrel_from_section): Likewise.
* config/tc-moxie.h (md_pcrel_from_section): Likewise.
* config/tc-msp430.h (md_pcrel_from_section): Likewise.
* config/tc-mt.h (md_pcrel_from_section): Likewise.
* config/tc-or1k.h (md_pcrel_from_section): Likewise.
* config/tc-ppc.h (md_pcrel_from_section): Likewise.
* config/tc-rl78.h (md_pcrel_from_section): Likewise.
* config/tc-rx.h (md_pcrel_from_section): Likewise.
* config/tc-s390.h (md_pcrel_from_section): Likewise.
* config/tc-sh.h (md_pcrel_from_section): Likewise.
* config/tc-xc16x.h (md_pcrel_from_section): Likewise.
* config/tc-xstormy16.h (md_pcrel_from_section): Likewise.
[PATCH 1/4]: microblaze: remove duplicate prototypes The microblaze target header duplicates prototypes already provided by tc.h. * config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol, md_show_usage, md_convert_frag, md_operand, md_number_to_chars, md_estimate_size_before_relax, md_section_align, tc_gen_reloc, md_apply_fix3): Delete prototypes.
2020-04-08 19:33:16 +08:00
* config/tc-microblaze.h (md_begin, md_assemble, md_undefined_symbol,
md_show_usage, md_convert_frag, md_operand, md_number_to_chars,
md_estimate_size_before_relax, md_section_align, tc_gen_reloc,
md_apply_fix3): Delete prototypes.
[PATCH 2/4]: moxie: use generic pcrel support The moxie target header uses md_pcrel_from, thus the local prototype and the macro definition for MD_PCREL_FROM_SECTION are not needed. * config/tc-moxie.h (MD_PCREL_FROM_SECTION): Delete define. (md_pcrel_from): Remove prototytpe.
2020-04-08 18:11:43 +08:00
gas: Mention support for Intel SERIALIZE and TSXLDTRK * NEWS: Mention support for Intel SERIALIZE and TSXLDTRK instructions.
2020-04-07 19:43:49 +08:00
2020-04-07 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention support for Intel SERIALIZE and TSXLDTRK
instructions.
gas/doc/c-z80.texi: Fix @xref warnings Fix gas/doc/c-z80.texi:244: warning: `.' or `,' must follow @xref, not ) gas/doc/c-z80.texi:278: warning: `.' or `,' must follow @xref, not ) gas/doc/c-z80.texi:284: warning: `.' or `,' must follow @xref, not ) gas/doc/c-z80.texi:291: warning: `.' or `,' must follow @xref, not ) gas/doc/c-z80.texi:295: warning: `.' or `,' must follow @xref, not ) * doc/c-z80.texi: Fix @xref warnings.
2020-04-07 19:17:01 +08:00
2020-04-07 H.J. Lu <hongjiu.lu@intel.com>
* doc/c-z80.texi: Fix @xref warnings.
Add support for intel TSXLDTRK instructions$ gas/ * config/tc-i386.c (cpu_arch): Add .TSXLDTRK. (cpu_noarch): Likewise. * doc/c-i386.texi: Document TSXLDTRK. * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests. * testsuite/gas/i386/tsxldtrk.d: Likewise. * testsuite/gas/i386/tsxldtrk.s: Likewise. * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, (prefix_table): New instructions (see prefixes above). (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, CPU_ANY_TSXLDTRK_FLAGS. (cpu_flags): Add CpuTSXLDTRK. * i386-opc.h (enum): Add CpuTSXLDTRK. (i386_cpu_flags): Add cputsxldtrk. * i386-opc.tbl: Add XSUSPLDTRK insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-04-07 13:59:50 +08:00
2020-04-07 Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document TSXLDTRK.
* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
* testsuite/gas/i386/tsxldtrk.d: Likewise.
* testsuite/gas/i386/tsxldtrk.s: Likewise.
* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
Add support for intel SERIALIZE instruction gas/ * config/tc-i386.c (cpu_arch): Add .serialize. (cpu_noarch): Likewise. * doc/c-i386.texi: Document serialize. * testsuite/gas/i386/i386.exp: Run serialize tests * testsuite/gas/i386/serialize.d: Likewise. * testsuite/gas/i386/x86-64-serialize.d: Likewise. * testsuite/gas/i386/serialize.s: Likewise. opcodes/ * i386-dis.c (prefix_table): New instructions serialize. * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS, CPU_ANY_SERIALIZE_FLAGS. (cpu_flags): Add CpuSERIALIZE. * i386-opc.h (enum): Add CpuSERIALIZE. (i386_cpu_flags): Add cpuserialize. * i386-opc.tbl: Add SERIALIZE insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-03-06 14:38:15 +08:00
2020-04-02 Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .serialize.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document serialize.
* testsuite/gas/i386/i386.exp: Run serialize tests
* testsuite/gas/i386/serialize.d: Likewise.
* testsuite/gas/i386/x86-64-serialize.d: Likewise.
* testsuite/gas/i386/serialize.s: Likewise.
ld: Disable ifunc tests on Solaris A couple of ld ifunc tests currently FAIL on 64-bit Solaris/x86: FAIL: ld-ifunc/ifunc-10-x86-64 FAIL: ld-ifunc/ifunc-11-x86-64 FAIL: ld-ifunc/ifunc-12-x86-64 FAIL: ld-ifunc/ifunc-13-x86-64 FAIL: ld-ifunc/ifunc-14a-x86-64 FAIL: ld-ifunc/ifunc-14b-x86-64 FAIL: ld-ifunc/ifunc-14c-x86-64 FAIL: ld-ifunc/ifunc-14d-x86-64 FAIL: ld-ifunc/ifunc-14e-x86-64 FAIL: ld-ifunc/ifunc-14f-x86-64 FAIL: ld-ifunc/ifunc-15-x86-64 FAIL: ld-ifunc/ifunc-17a-x86-64 FAIL: ld-ifunc/ifunc-17b-x86-64 FAIL: ld-ifunc/ifunc-2-local-x86-64-now FAIL: ld-ifunc/ifunc-2-local-x86-64 FAIL: ld-ifunc/ifunc-2-x86-64-now FAIL: ld-ifunc/ifunc-2-x86-64 FAIL: ld-ifunc/ifunc-20-x86-64 FAIL: ld-ifunc/pr17154-x86-64-now FAIL: ld-ifunc/pr17154-x86-64 For one, the actual error is weird: ./ld-new: target elf64-x86-64 not found failed with: <./ld-new: target elf64-x86-64 not found>, no expected output FAIL: ld-ifunc/ifunc-10-x86-64 although ld -V does report the elf_x86_64 emulation as supported: $ ./ld/ld-new -V GNU ld (GNU Binutils) 2.34.50.20200328 Supported emulations: elf_x86_64_sol2 elf_x86_64 [...] When using ld -m elf_x86_64_sol2 instead, one of the testcases links successfully. However, there's no point in pursuing this: Solaris does not support ifunc, as can be seen in <sys/elf.h>: /* * GNU/Linux specific symbol type not used by Solaris */ #define STT_GNU_IFUNC 10 and never will, given that it has symbol capabilities as solution to effectively the same problem: http://www.linker-aliens.org/blogs/rie/entry/symbol_capabilitie/ Therefore this patch disables ifunc testing on Solaris completely by removing Solaris from binutils/testsuite/lib/binutils-common.exp (supports_gnu_osabi). The ifunc part is justified above. SHF_GNU_MBIND is in the OS-specific range and conflicts with #define SHF_SUNW_REALLOC 0x01000000 /* internal: krtld realloc */ While the comment suggests this might be relocatable without too much problems, the description of mbind (no formal spec AFAICS, just the comment in the binutils patch submission) strongly suggests that this isn't relevant to Solaris at all. Indirectly, clearing supports_gnu_osabi on Solaris disables supports_gnu_unique. Again, Solaris <sys/elf.h> has /* * GNU/Linux specific binding not used by Solaris */ #define STB_GNU_UNIQUE 10 so this seems the right thing to do. Afterwards, one can remove the explicit mentions of *-*-solaris2* in quite a number of (but not all) the ld-ifunc dump file notarget lists. There's one fallout, though: two gas tests now XPASS because they are xfail'ed for !supports_gnu_osabi: XPASS: mbind sections 12 XPASS: mbind section contents 16 XPASS: mbind sections 16 XPASS: mbind section contents 16 To fix that, I've changed #xfail: ![supports_gnu_osabi] to notarget. Tested on x86_64-pc-solaris2.11, i386-pc-solaris2.11, x86_64-pc-linux-gnu, and i686-pc-linux-gnu. ld: * testsuite/ld-ifunc/ifunc-10-i386.d: Remove *-*-solaris2* from notarget. * ifunc-11-i386.d: Likewise. * ifunc-12-i386.d: Likewise. * ifunc-13-i386.d: Likewise. * ifunc-14a-i386.d: Likewise. * ifunc-14b-i386.d: Likewise. * ifunc-14c-i386.d: Likewise. * ifunc-14d-i386.d: Likewise. * ifunc-14e-i386.d: Likewise. * ifunc-14f-i386.d: Likewise. * ifunc-15-i386.d: Likewise. * ifunc-16-i386-now.d: Likewise. * ifunc-16-i386.d: Likewise. * ifunc-17a-i386.d: Likewise. * ifunc-17b-i386.d: Likewise. * ifunc-18a-i386.d: Likewise. * ifunc-18b-i386.d: Likewise. * ifunc-19a-i386.d: Likewise. * ifunc-19b-i386.d: Likewise. * ifunc-2-i386-now.d: Likewise. * ifunc-2-i386.d: Likewise. * ifunc-2-local-i386-now.d: Likewise. * ifunc-2-local-i386.d: Likewise. * ifunc-20-i386.d: Likewise. * ifunc-21-i386.d: Likewise. * ifunc-22-i386.d: Likewise. * ifunc-5a-i386.d: Likewise. * ifunc-5a-local-i386.d: Likewise. * ifunc-5b-i386.d: Likewise. * ifunc-5b-local-i386.d: Likewise. * ifunc-5r-local-i386.d: Likewise. * ifunc-6a-i386.d: Likewise. * ifunc-6b-i386.d: Likewise. * ifunc-7a-i386.d: Likewise. * ifunc-7b-i386.d: Likewise. * ifunc-8-i386.d: Likewise. * ifunc-9-i386.d: Likewise. * pr17154-i386-now.d: Likewise. * pr17154-i386.d: Likewise. * ifunc-23a-x86.d: Remove notarget. * ifunc-24a-x86.d: Likewise. * ifunc-25a-x86.d: Likewise. gas: * testsuite/gas/elf/section12a.d: Use notarget instead of xfail. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. binutils: * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Don't enable on *-*-solaris*.
2020-04-02 16:52:57 +08:00
2020-04-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* testsuite/gas/elf/section12a.d: Use notarget instead of xfail.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
[PATCH gas/m68k] Fix a register range check * config/tc-m68k.c (m68k_ip): Fix range check for index register with a suppressed address register.
2020-04-02 15:57:45 +08:00
2020-04-02 Gunther Nikl <gnikl@justmail.de>
* config/tc-m68k.c (m68k_ip): Fix range check for index register
with a suppressed address register.
x86: Force relocation against local absolute symbol Define TC_FORCE_RELOCATION_ABS to force relocation against local absolute symbol. PR gas/25756 * config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New. * testsuite/gas/i386/localpic.s: Add a test for relocation against local absolute symbol. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/localpic.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
2020-04-01 20:40:45 +08:00
2020-04-01 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25756
* config/tc-i386.h (TC_FORCE_RELOCATION_ABS): New.
* testsuite/gas/i386/localpic.s: Add a test for relocation
against local absolute symbol.
* testsuite/gas/i386/x86-64-localpic.s: Likewise.
* testsuite/gas/i386/localpic.d: Updated.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
gas: Fix some x86_64 testcases for Solaris not using R_X86_64_PLT32 [PR25732] As reported in PR gas/25732, some testcases currently FAIL on Solaris/x86: FAIL: x86-64 branch 2 FAIL: x86-64 branch 3 FAIL: x86-64 MPX branch FAIL: x86-64 branch with BND prefix FAIL: x86-64 jump Since https://sourceware.org/ml/binutils/2019-03/msg00163.html, gas doesn't emit R_X86_64_PLT32 as branch marker on Solaris. Since the testsuite lacks a way to preprocess dump files, adjusted copies of the affected dumps are now used on Solaris. Unfortunately, those dumps weren't adapted when the original testcases were changed or other testcases started to differ between non-Solaris and Solaris targets. The following patch fixes that, re-syncing the affected dump files or creating new Solaris-specific ones. Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11, x86_64-pc-linux-gnu, and i686-pc-linux-gnu. PR gas/25732 * testsuite/gas/i386/solaris/x86-64-branch-2.d: New file. * testsuite/gas/i386/solaris/x86-64-branch-3.d: New file. * testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to testsuite/gas/i386/x86-64-jump.d. * gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d: Incorporate changes to gas/testsuite/gas/i386/x86-64-mpx-branch-1.d. * testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate changes to testsuite/gas/i386/x86-64-mpx-branch-2.d. * testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*. * testsuite/gas/i386/x86-64-branch-3.d: Likewise.
2020-04-01 20:10:34 +08:00
2020-04-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR gas/25732
* testsuite/gas/i386/solaris/x86-64-branch-2.d: New file.
* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
testsuite/gas/i386/x86-64-jump.d.
* gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
Incorporate changes to
gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
changes to testsuite/gas/i386/x86-64-mpx-branch-2.d.
* testsuite/gas/i386/x86-64-branch-2.d: Skip on *-*-solaris*.
* testsuite/gas/i386/x86-64-branch-3.d: Likewise.
PR 25611, PR 25614: GAS: Remove a double inclusion of "bignum.h" Correct an issue with commit 5496f3c635dc ("Add support for generating DWARF-5 format directory and file name tables from the assembler.") and remove a duplicate direct inclusion of "bignum.h" from dwarf2dbg.c that causes a GAS compilation error: In file included from .../gas/dwarf2dbg.c:33: .../gas/bignum.h:42: error: redefinition of typedef 'LITTLENUM_TYPE' .../gas/bignum.h:42: error: previous declaration of 'LITTLENUM_TYPE' was here make[4]: *** [dwarf2dbg.o] Error 1 with some GCC versions, as this header has been already included via "as.h" and then "flonum.h". gas/ PR 25611 PR 25614 * dwarf2dbg.c: Do not include "bignum.h".
2020-04-01 06:01:36 +08:00
2020-03-31 Maciej W. Rozycki <macro@linux-mips.org>
PR 25611
PR 25614
* dwarf2dbg.c: Do not include "bignum.h".
RISC-V: Update CSR to privileged spec 1.11. gas/ * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo. * testsuite/gas/riscv/alias-csr.s: Likewise. * testsuite/gas/riscv/no-aliases-csr.d: Move this to priv-reg-pseudo-noalias. * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent. * testsuite/gas/riscv/bad-csr.l: Likewise. * testsuite/gas/riscv/bad-csr.s: Likewise. * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg. * testsuite/gas/riscv/satp.s: Likewise. * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo csr instruction, including alias-csr testcase. * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise. * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all pseudo instruction with objdump -Mno-aliases. * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase. * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise. * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11. * testsuite/gas/riscv/priv-reg.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. include/ * opcode/riscv-opc.h: Update CSR to 1.11. gdb/ * features/riscv/32bit-csr.xml: Regenerated. * features/riscv/64bit-csr.xml: Regenerated.
2020-03-12 17:48:39 +08:00
2020-03-30 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
* testsuite/gas/riscv/alias-csr.s: Likewise.
* testsuite/gas/riscv/no-aliases-csr.d: Move this
to priv-reg-pseudo-noalias.
* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
* testsuite/gas/riscv/bad-csr.l: Likewise.
* testsuite/gas/riscv/bad-csr.s: Likewise.
* testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
* testsuite/gas/riscv/satp.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
csr instruction, including alias-csr testcase.
* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
pseudo instruction with objdump -Mno-aliases.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
* testsuite/gas/riscv/priv-reg.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
The "b" flag for COFF sections only unsets the LOAD attribute. It should also clear the CONTENTS attribute so that named bss sections don't take up space in an object file. This can be achieved by setting the 'bss' flag in seg_info. * config/obj-coff.c (obj_coff_section): Set the bss flag on sections with the "b" attribute.
2020-03-25 19:52:07 +08:00
2020-03-25 J.W. Jagersma <jwjagersma@gmail.com>
* config/obj-coff.c (obj_coff_section): Set the bss flag on
sections with the "b" attribute.
s12z disassembler tidy Don't ignore buffer memory read failure, or malloc failure. Lots of functions get a return status to pass these failures up the chain in this patch. opcodes/ * s12z-dis.c (abstract_read_memory): Don't print error on EOI. * s12z-opc.c: Formatting. (operands_f): Return an int. (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), (exg_sex_discrim): Likewise. (create_immediate_operand, create_bitfield_operand), (create_register_operand_with_size, create_register_all_operand), (create_register_all16_operand, create_simple_memory_operand), (create_memory_operand, create_memory_auto_operand): Don't segfault on malloc failure. (z_ext24_decode): Return an int status, negative on fail, zero on success. (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), (mov_imm_opr, ld_18bit_decode, exg_sex_decode), (loop_primitive_decode, shift_decode, psh_pul_decode), (bit_field_decode): Similarly. (z_decode_signed_value, decode_signed_value): Similarly. Add arg to return value, update callers. (x_opr_decode_with_size): Check all reads, returning NULL on fail. Don't segfault on NULL operand. (decode_operation): Return OP_INVALID on first fail. (decode_s12z): Check all reads, returning -1 on fail. gas/ * testsuite/gas/s12z/truncated.d: Update expected output.
2020-03-22 12:32:27 +08:00
2020-03-22 Alan Modra <amodra@gmail.com>
* testsuite/gas/s12z/truncated.d: Update expected output.
Add support for the xdef and xref pseudo-ops to the Z80 assembler. PR 25690 * config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops. * doc/c-z80.texi: Update documentation.
2020-03-20 21:53:02 +08:00
2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25690
* config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops.
* doc/c-z80.texi: Update documentation.
Replace a couple of assertions in the BFD library that can be triggered by attempts to parse corrupt input files. PR 25633 * elf.c (_bfd_elf_copy_special_section_fields): Replace assertions with error messages.
2020-03-18 01:02:15 +08:00
2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25641
PR 25668
PR 25633
Fix disassembling ED+A4/AC/B4/BC opcodes.
Fix assembling lines containing colonless label and instruction
with first operand inside parentheses.
Fix registration of unsupported by target CPU registers.
* config/tc-z80.c: See above.
* config/tc-z80.h: See above.
* testsuite/gas/z80/colonless.d: Update test.
* testsuite/gas/z80/colonless.s: Likewise.
* testsuite/gas/z80/ez80_adl_all.d: Likewise.
* testsuite/gas/z80/ez80_unsup_regs.d: Likewise.
* testsuite/gas/z80/ez80_z80_all.d: Likewise.
* testsuite/gas/z80/gbz80_unsup_regs.d: Likewise.
* testsuite/gas/z80/r800_unsup_regs.d: Likewise.
* testsuite/gas/z80/unsup_regs.s: Likewise.
* testsuite/gas/z80/z180_unsup_regs.d: Likewise.
* testsuite/gas/z80/z80.exp: Likewise.
* testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise.
* testsuite/gas/z80/z80_unsup_regs.d: Likewise.
* testsuite/gas/z80/z80n_unsup_regs.d: Likewise.
gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVE As explained in the PR, the addition of MVE makes the parser strip 't' and 'e' as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with lt and le conditions to be initially parsed as vaddl and vsubl. This means the operand parsing for these must allow for the same operands as the scalar vadd and vsub. I had forgotten to do this and this patch remedies that oversight. gas/ChangeLog: 2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25660 * config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ. (parse_operands): Handle new operand codes. (do_neon_dyadic_long): Make shape check accept the scalar variants. (asm_opcode_insns): Fix operand codes for vaddl and vsubl. * testsuite/gas/arm/mve-vaddsub-it.s: New test. * testsuite/gas/arm/mve-vaddsub-it.d: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.s: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.l: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.d: New test. * testsuite/gas/arm/nomve-vaddsub-it.d: New test.
2020-03-13 21:31:56 +08:00
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25660
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
(parse_operands): Handle new operand codes.
(do_neon_dyadic_long): Make shape check accept the scalar variants.
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
NEWS: Mention x86 assembler options for CVE-2020-0551 * NEWS: Mention x86 assembler options for CVE-2020-0551.
2020-03-12 00:56:17 +08:00
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention x86 assembler options for CVE-2020-0551.
i386: Add tests for lfence with load/indirect branch/ret Add tests for -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. * testsuite/gas/i386/i386.exp: Run new tests. * testsuite/gas/i386/lfence-byte.d: New file. * testsuite/gas/i386/lfence-byte.e: Likewise. * testsuite/gas/i386/lfence-byte.s: Likewise. * testsuite/gas/i386/lfence-indbr-a.d: Likewise. * testsuite/gas/i386/lfence-indbr-b.d: Likewise. * testsuite/gas/i386/lfence-indbr-c.d: Likewise. * testsuite/gas/i386/lfence-indbr.e: Likewise. * testsuite/gas/i386/lfence-indbr.s: Likewise. * testsuite/gas/i386/lfence-load.d: Likewise. * testsuite/gas/i386/lfence-load.s: Likewise. * testsuite/gas/i386/lfence-ret-a.d: Likewise. * testsuite/gas/i386/lfence-ret-b.d: Likewise. * testsuite/gas/i386/lfence-ret.s: Likewise. * testsuite/gas/i386/x86-64-lfence-byte.d: Likewise. * testsuite/gas/i386/x86-64-lfence-byte.e: Likewise. * testsuite/gas/i386/x86-64-lfence-byte.s: Likewise. * testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise. * testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise. * testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise. * testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise. * testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise. * testsuite/gas/i386/x86-64-lfence-load.d: Likewise. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise. * testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise.
2020-03-12 00:46:19 +08:00
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/lfence-byte.d: New file.
* testsuite/gas/i386/lfence-byte.e: Likewise.
* testsuite/gas/i386/lfence-byte.s: Likewise.
* testsuite/gas/i386/lfence-indbr-a.d: Likewise.
* testsuite/gas/i386/lfence-indbr-b.d: Likewise.
* testsuite/gas/i386/lfence-indbr-c.d: Likewise.
* testsuite/gas/i386/lfence-indbr.e: Likewise.
* testsuite/gas/i386/lfence-indbr.s: Likewise.
* testsuite/gas/i386/lfence-load.d: Likewise.
* testsuite/gas/i386/lfence-load.s: Likewise.
* testsuite/gas/i386/lfence-ret-a.d: Likewise.
* testsuite/gas/i386/lfence-ret-b.d: Likewise.
* testsuite/gas/i386/lfence-ret.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-byte.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-byte.e: Likewise.
* testsuite/gas/i386/x86-64-lfence-byte.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr-a.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr-b.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr-c.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr.e: Likewise.
* testsuite/gas/i386/x86-64-lfence-indbr.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-load.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Likewise.
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Likewise.
i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551] Add 3 command-line options to generate lfence for load, indirect near branch and ret to help mitigate: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551 1. -mlfence-after-load=[no|yes]: -mlfence-after-load=yes generates lfence after load instructions. 2. -mlfence-before-indirect-branch=[none|all|memory|register]: a. -mlfence-before-indirect-branch=all generates lfence before indirect near branches via register and a warning before indirect near branches via memory. b. -mlfence-before-indirect-branch=memory issue a warning before indirect near branches via memory. c. -mlfence-before-indirect-branch=register generates lfence before indirect near branches via register. Note that lfence won't be generated before indirect near branches via register with -mlfence-after-load=yes since lfence will be generated after loading branch target register. 3. -mlfence-before-ret=[none|or|not] a. -mlfence-before-ret=or generates or with lfence before ret. b. -mlfence-before-ret=not generates not with lfence before ret. A warning will be issued and lfence won't be generated before indirect near branch and ret if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. * config/tc-i386.c (lfence_after_load): New. (lfence_before_indirect_branch_kind): New. (lfence_before_indirect_branch): New. (lfence_before_ret_kind): New. (lfence_before_ret): New. (last_insn): New. (load_insn_p): New. (insert_lfence_after): New. (insert_lfence_before): New. (md_assemble): Call insert_lfence_before and insert_lfence_after. Set last_insn. (OPTION_MLFENCE_AFTER_LOAD): New. (OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New. (OPTION_MLFENCE_BEFORE_RET): New. (md_longopts): Add -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. (md_parse_option): Handle -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. (md_show_usage): Display -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. * doc/c-i386.texi: Document -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=.
2020-03-12 00:46:19 +08:00
2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (lfence_after_load): New.
(lfence_before_indirect_branch_kind): New.
(lfence_before_indirect_branch): New.
(lfence_before_ret_kind): New.
(lfence_before_ret): New.
(last_insn): New.
(load_insn_p): New.
(insert_lfence_after): New.
(insert_lfence_before): New.
(md_assemble): Call insert_lfence_before and insert_lfence_after.
Set last_insn.
(OPTION_MLFENCE_AFTER_LOAD): New.
(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
(OPTION_MLFENCE_BEFORE_RET): New.
(md_longopts): Add -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_parse_option): Handle -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_show_usage): Display -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
* doc/c-i386.texi: Document -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
Add support for generating DWARF-5 format directory and file name tables from the assembler. PR 25611 PR 25614 * dwarf.h (DWARF2_Internal_LineInfo): Add li_address_size and li_segment_size fields. * dwarf.c (read_debug_line_header): Record the address size and segment selector size values (if present) in the lineinfo structure. (display_formatted_table): Warn if the format count is empty but the table itself is not empty. Display the format count and entry count at the start of the table dump. (display_debug_lines_raw): Display the address size and segement selector size fields, if present. * testsuite/binutils-all/dw5.W: Update expected output. gas * dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1. (DWARF2_FILE_SIZE_NAME): Default to -1. (DWARF2_LINE_VERSION): Default to the current dwarf level or 3, whichever is higher. (DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1. (NUM_MD5_BYTES): Define. (struct file entry): Add md5 field. (get_filenum): Delete and replace with... (get_basename): New function. (get_directory_table_entry): New function. (allocate_filenum): New function. (allocate_filename_to_slot): New function. (dwarf2_where): Use new functions. (dwarf2_directive_filename): Add support for extended .file pseudo-op. (dwarf2_directive_loc): Allow the use of file number zero with DWARF 5 or higher. (out_file_list): Rename to... (out_dir_and_file_list): Add DWARF 5 support. (out_debug_line): Emit extra values into the section header for DWARF 5. (out_debug_str): Allow for file 0 to be used with DWARF 5. * doc/as.texi (.file): Update the description of this pseudo-op. * testsuite/gas/elf-dwarf-5-file0.s: Add more lines. * testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output. * testsuite/gas/lns/lns-diag-1.l: Update expected error message. * NEWS: Mention the new feature.
2020-03-11 18:17:14 +08:00
2020-03-11 Nick Clifton <nickc@redhat.com>
PR 25611
PR 25614
* dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1.
(DWARF2_FILE_SIZE_NAME): Default to -1.
(DWARF2_LINE_VERSION): Default to the current dwarf level or 3,
whichever is higher.
(DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1.
(NUM_MD5_BYTES): Define.
(struct file entry): Add md5 field.
(get_filenum): Delete and replace with...
(get_basename): New function.
(get_directory_table_entry): New function.
(allocate_filenum): New function.
(allocate_filename_to_slot): New function.
(dwarf2_where): Use new functions.
(dwarf2_directive_filename): Add support for extended .file
pseudo-op.
(dwarf2_directive_loc): Allow the use of file number zero with
DWARF 5 or higher.
(out_file_list): Rename to...
(out_dir_and_file_list): Add DWARF 5 support.
(out_debug_line): Emit extra values into the section header for
DWARF 5.
(out_debug_str): Allow for file 0 to be used with DWARF 5.
* doc/as.texi (.file): Update the description of this pseudo-op.
* testsuite/gas/elf-dwarf-5-file0.s: Add more lines.
* testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output.
* testsuite/gas/lns/lns-diag-1.l: Update expected error message.
* NEWS: Mention the new feature.
More 1 << 31 signed overflows * config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions to avoid signed overflow. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise. * config/tc-nds32.c (SET_ADDEND): Likewise. * config/tc-nios2.c (nios2_assemble_arg_R): Likewise.
2020-03-10 19:22:50 +08:00
2020-03-10 Alan Modra <amodra@gmail.com>
* config/tc-csky.c (get_operand_value): Rewrite 1 << 31 expressions
to avoid signed overflow.
* config/tc-mcore.c (md_assemble): Likewise.
* config/tc-mips.c (gpr_read_mask, gpr_write_mask): Likewise.
* config/tc-nds32.c (SET_ADDEND): Likewise.
* config/tc-nios2.c (nios2_assemble_arg_R): Likewise.
x86: use template for AVX/AVX512 floating point comparison insns These all follow an almost common pattern, again with the exception of being commutative, which can be easily taken care of. Note that, as an intended side effect (and in fact one of the reason to introduce templates), AVX long-form pseudo-ops get introduced alongside the already existing AVX512 ones.
2020-03-09 17:13:43 +08:00
2020-03-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx.s: Add long-form VCMP[PS][SD] pseudos.
* testsuite/gas/i386/avx.d, testsuite/gas/i386/avx-16bit.d,
testsuite/gas/i386/avx-intel.d: Adjust expectations.
Re: Add support for a ".file 0" directive if supporting DWARF 5 or higher. Fixes a fail on hppa64-hp-hpux, where anything in the first column is a label. * testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in first column.
2020-03-07 17:39:57 +08:00
2020-03-07 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in
first column.
Add support for a ".file 0" directive if supporting DWARF 5 or higher. PR 25614 * dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of 0 if the dwarf_level is 5 or more. Complain if a filename follows a file 0. * testsuite/gas/elf/dwarf-5-file0.s: New test. * testsuite/gas/elf/dwarf-5-file0.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. PR 25612 * config/tc-ia64.h (DWARF2_VERISION): Fix typo. * doc/as.texi: Fix another typo.
2020-03-07 01:13:22 +08:00
2020-03-06 Nick Clifton <nickc@redhat.com>
PR 25614
* dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of
0 if the dwarf_level is 5 or more. Complain if a filename follows
a file 0.
* testsuite/gas/elf/dwarf-5-file0.s: New test.
* testsuite/gas/elf/dwarf-5-file0.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
PR 25612
* config/tc-ia64.h (DWARF2_VERISION): Fix typo.
* doc/as.texi: Fix another typo.
Add support for --dwarf-[3|4|5] to assembler command line. PR 25612 * as.c (dwarf_level): Define. (show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5. (parse_args): Add support for the new options. as.h (dwarf_level): Prototype. * dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version value. * config/tc-ia64.h (DWARF2_VERISION): Update definition. (DWARF2_LINE_VERSION): Remove definition. * doc/as.texi: Document the new options.
2020-03-06 22:52:14 +08:00
2020-03-06 Nick Clifton <nickc@redhat.com>
PR 25612
* as.c (dwarf_level): Define.
(show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5.
(parse_args): Add support for the new options.
as.h (dwarf_level): Prototype.
* dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version
value.
* config/tc-ia64.h (DWARF2_VERISION): Update definition.
(DWARF2_LINE_VERSION): Remove definition.
* doc/as.texi: Document the new options.
Stop the assembler from complaining that the input and output files are the same, if neither of them are regular files. PR 25572 * as.c (main): Allow matching input and outputs when they are not regular files.
2020-03-06 18:44:12 +08:00
2020-03-06 Nick Clifton <nickc@redhat.com>
PR 25572
* as.c (main): Allow matching input and outputs when they are
not regular files.
x86: reduce amount of various VCVT* templates Presumably as a result of various changes over the last several months, and - for some of them - with a generalization of logic in match_mem_size() plus mirroring of this generalization into the broadcast handling logic of check_VecOperands(), various register-only templates can be foled into their respective memory forms. This in particular then also allows dropping a few more instances of IgnoreSize.
2020-03-06 15:56:47 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size): Generalize broadcast special
casing.
(check_VecOperands): Zap xmmword/ymmword/zmmword when more than
one of byte/word/dword/qword is set alongside a SIMD register in
a template's operand.
x86: drop/replace IgnoreSize Even after commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), by which many of its uses have become unnecessary (some were unnecessary even before), IgnoreSize is still used for various slightly different purposes: - to suppress emission of an operand size prefix, - in Intel syntax mode to zap "derived" suffixes in certain cases and to skip certain checks of remaining "derived" suffixes, - to suppress ambiguous operand size / missing suffix diagnostics, - for prefixes to suppress the "stand-alone ... prefix" warning. Drop entirely unnecessary ones and where possible also replace instances by the more focused (because of having just a single purpose) NoRex64. To further restrict when IgnoreSize is needed, also generalize the logic when to skip a template because of a present or derived L or Q suffix, by skipping immediate operands. Additionally consider mask registers and VecSIB there. Note that for the time being the attribute needs to be kept in place on MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand template of them allows for only non-SIMD-register actuals) allowing for Dword operands - the logic when to emit a data size prefix would need further adjustment first. Note also that the memory forms of {,v}pinsrw get their permission for an L or Q suffix dropped. I can only assume that it being this way was a cut-and-paste mistake from the register forms, as the latter specifically have NoRex64 set, and the {,v}pextrw counterparts don't allow these suffixes either. Convert VexW= again to their respective VexW* on lines touched anyway.
2020-03-06 15:55:52 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Extend code in logic
rejecting certain suffixes in certain modes to also cover mask
register use and VecSIB. Drop special casing of broadcast. Skip
immediates in the check.
x86: fold (supposed to be) identical code The Q and L suffix exclusion checks in match_template() ought to be (kept) in sync as far as their FPU and SIMD aspects go. This was already violated by only the Q one checking for active broadcast. Convert the code such that there'll be only one instance of the logic, the more that subsequently the logic is liable to need further refinement / extension. (The alternative would be to drop all SIMD-ness from the L part, but it is in principle possible to enable all sorts of SIMD support with just a pre-386 CPU, via suitable .arch directives.)
2020-03-06 15:55:03 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Fold duplicate code in
logic rejecting certain suffixes in certain modes. Drop
pointless "else".
x86: replace NoRex64 on VEX-encoded insns When the template specifies any of the possible VexW settings, we can use this instead of a separate NoRex64 to suppress the setting of REX_W. Note that this ends up addressing an inconsistency between VEX- and EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a 64-bit GPR operand. Adjust the testcase to cover both cases. Convert VexW= to their respective VexW* on lines touched anyway.
2020-03-06 15:53:18 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Exlucde !vexw insns
alongside !norex64 ones.
* testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR*
with both 32- and 64-bit GPR operands.
* testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both
32- and 64-bit GPR operands.
* testsuite/gas/i386/x86-64-avx512bw-intel.d,
testsuite/gas/i386/x86-64-avx512bw.d,
testsuite/gas/i386/x86-64-avx512f-intel.d,
testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations.
x86: drop Rex64 attribute It is almost entirely redundant with Size64, and the sole case (CRC32) where direct replacement isn't possible can easily be taken care of in another way.
2020-03-06 15:52:12 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Drop use of rex64.
(process_suffix): For REX.W for 64-bit CRC32.
x86: correct MPX insn w/o base or index encoding in 16-bit mode Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16 fails to match the templates. The SDM leaves open whether BNDC[LNU] with a GPR operand require an operand size override; this aspect is therefore left untouched here.
2020-03-06 15:50:56 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_addressing_mode): For 32-bit
addressing for MPX insns without base/index.
* testsuite/gas/i386/mpx-16bit.s,
* testsuite/gas/i386/mpx-16bit.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: add missing IgnoreSize For proper code generation in 16-bit mode (or to avoid the "same type of prefix used twice" diagnostic there), IgnoreSize is needed on certain templates allowing for just 32-(and maybe 64-)bit operands. Beyond adding tests for the previously broken cases, also add ones for the previously working cases where IgnoreSize is needed for the same reason (leaving out MPX for now, as that'll require an assembler change first). Some minor adjustments to tests get done such that re-use of the same code for 16-bit code generation testing becomes easier.
2020-03-06 15:49:45 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
* testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
as well as a BSWAP one.
* testsuite/gas/i386/rdpid.s: Add 16-bit case.
* testsuite/gas/i386/sse2-16bit.s: Cover more insns.
* testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
testsuite/gas/i386/vmx.d: Adjust expectations.
x86: refine TPAUSE and UMWAIT Allowing 64-bit registers is misleading here: Elsewhere these get allowed when there's no difference between either variant, because of 32-bit destination registers having their upper halves zeroed in 64-bit mode. Here, however, they're source registers, and hence specifying 64-bit registers would lead to the ambiguity of whether the upper 32 bits actually matter. Additionally, for proper code generation in 16-bit mode, IgnoreSize is needed on both. And finally, just like for e.g. MONITOR/MWAIT, add variants with all input registers explicitly specified.
2020-03-06 15:48:48 +08:00
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Also exclude tpause and umwait
from having their operands swapped.
* testsuite/gas/i386/waitpkg.s,
testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
3-operand cases as well as testing of 16-bit code generation.
* testsuite/gas/i386/waitpkg.d,
testsuite/gas/i386/waitpkg-intel.d,
testsuite/gas/i386/x86-64-waitpkg.d,
testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
RISC-V: Add description for RISC-V Modifiers to as doc. gas/ * doc/c-riscv.texi (relocation modifiers): Add documentation. (RISC-V-Formats): Update the section name from "Instruction Formats" to "RISC-V Instruction Formats".
2020-03-04 13:08:04 +08:00
2020-03-04 Nelson Chu <nelson.chu@sifive.com>
RISC-V: Support assembler modifier %got_pcrel_hi. gas/ * config/tc-riscv.c: Support the modifier %got_pcrel_hi. * doc/c-riscv.texi: Add documentation. * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new modifier %got_pcrel_hi. * testsuite/gas/riscv/no-relax-reloc.s: Likewise. * testsuite/gas/riscv/relax-reloc.d: Likewise. * testsuite/gas/riscv/relax-reloc.s: Likewise.
2020-03-04 13:08:05 +08:00
* config/tc-riscv.c (percent_op_utype): Support the modifier
%got_pcrel_hi.
* doc/c-riscv.texi: Add documentation.
* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
modifier %got_pcrel_hi.
* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
* testsuite/gas/riscv/relax-reloc.s: Likewise.
RISC-V: Add description for RISC-V Modifiers to as doc. gas/ * doc/c-riscv.texi (relocation modifiers): Add documentation. (RISC-V-Formats): Update the section name from "Instruction Formats" to "RISC-V Instruction Formats".
2020-03-04 13:08:04 +08:00
* doc/c-riscv.texi (relocation modifiers): Add documentation.
(RISC-V-Formats): Update the section name from "Instruction Formats"
to "RISC-V Instruction Formats".
Generate a warning in the ARM assembler if a PC-relative thumb load instruction is detected in a section with insufficient alignment. * config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is detected in a section which does not have at least 4 byte alignment. * testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive. * testsuite/gas/arm/ldr-t.s: Likewise. * testsuite/gas/arm/sp-pc-usage-t.s: Likewise. * testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of disassembly, ignoring any NOPs that may have been inserted because of section alignment. * testsuite/gas/arm/ldr-t.d: Likewise.
2020-03-05 01:28:46 +08:00
2020-03-04 Alexandre Oliva <oliva@adacore.com>
* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
detected in a section which does not have at least 4 byte
alignment.
* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
* testsuite/gas/arm/ldr-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
disassembly, ignoring any NOPs that may have been inserted because
of section alignment.
* testsuite/gas/arm/ldr-t.d: Likewise.
x86: support VMGEXIT It has been publicly documented for quite some time, albeit not in the "General-Purpose and System Instructions" volume: https://www.amd.com/system/files/TechDocs/24593.pdf.
2020-03-04 15:58:13 +08:00
2020-03-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_arch): Add .sev_es entry.
* doc/c-i386.texi: Mention sev_es.
* testsuite/gas/i386/arch-13.s: Add SEV-ES case.
* testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
expectations.
* testsuite/gas/i386/arch-13-znver1.d,
testsuite/gas/i386/arch-13-znver2.d: Extend -march=.
x86: Replace IgnoreSize/DefaultSize with MnemonicSize Since an instruction template can't have both IgnoreSize and DefaultSize, this patch replaces IgnoreSize and DefaultSize with MnemonicSize. gas/ * config/tc-i386.c (match_template): Replace ignoresize and defaultsize with mnemonicsize. (process_suffix): Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize with MnemonicSize. * i386-opc.h (IGNORESIZE): New. (DEFAULTSIZE): Likewise. (IgnoreSize): Removed. (DefaultSize): Likewise. (MnemonicSize): New. (i386_opcode_modifier): Replace ignoresize/defaultsize with mnemonicsize. * i386-opc.tbl (IgnoreSize): New. (DefaultSize): Likewise. * i386-tbl.h: Regenerated.
2020-03-04 03:24:16 +08:00
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Replace ignoresize and
defaultsize with mnemonicsize.
(process_suffix): Likewise.
The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble of this and LD (HL),IX instruction. Also it update testsuit. PR 25627 opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX instructions. gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of instruction LD IY,(HL). * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
2020-03-04 00:31:42 +08:00
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25627
* config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
instruction LD IY,(HL).
* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
x86: Allow integer conversion without suffix in AT&T syntax According to gas manual, suffix in instruction mnemonics isn't always required: When there is no sizing suffix and no (suitable) register operands to deduce the size of memory operands, with a few exceptions and where long operand size is possible in the first place, operand size will default to long in 32- and 64-bit modes. This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they must be allowed without suffix in AT&T syntax. gas/ PR gas/25622 * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and x86-64-default-suffix-avx. * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries. * testsuite/gas/i386/noreg64.d: Updated. * testsuite/gas/i386/noreg64.l: Likewise. * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file. * testsuite/gas/i386/x86-64-default-suffix.d: Likewise. * testsuite/gas/i386/x86-64-default-suffix.s: Likewise. opcodes/ PR gas/25622 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. * i386-tbl.h: Regenerated.
2020-03-03 23:39:18 +08:00
2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25622
* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
x86-64-default-suffix-avx.
* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
* testsuite/gas/i386/noreg64.d: Updated.
* testsuite/gas/i386/noreg64.l: Likewise.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.
Fix a potential illegal memory access in the Z80 assembler. PR 25604 * config/tc-z80.c (contains_register): Prevent an illegal memory access when checking an expression for a register name.
2020-03-03 21:09:19 +08:00
2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25604
* config/tc-z80.c (contains_register): Prevent an illegal memory
access when checking an expression for a register name.
Tidy obj-coff.h * config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips support.
2020-03-03 06:14:26 +08:00
2020-03-03 Alan Modra <amodra@gmail.com>
* config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips
support.
miscellaneous SEC_SMALL_DATA This patch arranges for symbols defined in .sdata and .sbss to be reported by nm with 'g' and 's' flags, for coff targets that support .sdata and .sbss. The assembler changes regarding SEC_SMALL_DATA are really just documentation. As far as I'm aware, this won't change any assembler output. bfd/ * coff-alpha.c (alpha_ecoff_le_vec): Add SEC_SMALL_DATA to applicable section flags. * coff-mips.c (mips_ecoff_le_vec, mips_ecoff_be_vec): Likewise. (mips_ecoff_bele_vec): Likewise. * coffcode.h (sec_to_styp_flags): Set SEC_SMALL_DATA for .sdata and .sbss sections. * ecoff.c (_bfd_ecoff_new_section_hook): Likewise. (_bfd_ecoff_styp_to_sec_flags): Likewise. gas/ * config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section. * config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata and .sbss sections. * config/tc-score.c: Delete !BFD_ASSEMBLER code throughout. (s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section. (s3_s_score_lcomm): Likewise. * config/tc-score7.c: Similarly. * read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
2020-03-02 07:47:18 +08:00
2020-03-02 Alan Modra <amodra@gmail.com>
* config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section.
* config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata
and .sbss sections.
* config/tc-score.c: Delete !BFD_ASSEMBLER code throughout.
(s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section.
(s3_s_score_lcomm): Likewise.
* config/tc-score7.c: Similarly.
* read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
MIPS/fix_loongson3_llsc: fix when target has multi labels When there is multi-labels on the same insn, the current code will take care about the last one. it may cause that no sync is added at the target. Here we scan all labels with same value of S_GET_VALUE(label_list->label) by label_list->next. 2020-02-28 YunQiang Su <syq@debian.org> PR gas/25539 * config/tc-mips.c (fix_loongson3_llsc): Compare label value to handle multi-labels. (has_label_name): New.
2020-02-28 15:58:13 +08:00
2020-02-28 YunQiang Su <syq@debian.org>
PR gas/25539
* config/tc-mips.c (fix_loongson3_llsc): Compare label value
to handle multi-labels.
(has_label_name): New.
[binutils][arm] Arm CDE CX*A instructions allow condition code The implementation of the Arm CDE CX*A instructions doesn't allow a condition code on the instructions but does allow the instruction in an ITBlock. The specification has been recently updated, though this is yet to be published. The instructions now should allow a suffix, and should behave in the standard way around ITBlocks. This patch removes the custom pred_instruction_type and handling for these instructions, and uses the standard INSIDE_IT_INSN predication type to describe the new instructions. gas/ChangeLog: 2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (enum pred_instruction_type): Remove NEUTRAL_IT_NO_VPT_INSN predication type. (cxn_handle_predication): Modify to require condition suffixes. (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases. * testsuite/gas/arm/cde-scalar.s: Update test. * testsuite/gas/arm/cde-warnings.l: Update test. * testsuite/gas/arm/cde-warnings.s: Update test.
2020-02-26 22:23:11 +08:00
2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (enum pred_instruction_type): Remove
NEUTRAL_IT_NO_VPT_INSN predication type.
(cxn_handle_predication): Modify to require condition suffixes.
(handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
* testsuite/gas/arm/cde-scalar.s: Update test.
* testsuite/gas/arm/cde-warnings.l: Update test.
* testsuite/gas/arm/cde-warnings.s: Update test.
gas gettext warning gettext("") returns the header entry with meta information, not the empty string. * config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use N_() on empty string.
2020-02-26 10:27:19 +08:00
2020-02-26 Alan Modra <amodra@gmail.com>
* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
N_() on empty string.
gas strncpy warning Avoid a warning that the buffer may not be zero terminated. * read.c (read_a_source_file): Call strncpy with length one less than size of original_case_string.
2020-02-26 10:08:11 +08:00
2020-02-26 Alan Modra <amodra@gmail.com>
* read.c (read_a_source_file): Call strncpy with length one
less than size of original_case_string.
Indent labels Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-02-25 13:04:46 +08:00
2020-02-26 Alan Modra <amodra@gmail.com>
* config/obj-elf.c: Indent labels correctly.
* config/obj-macho.c: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-riscv.c: Likewise.
* config/tc-s12z.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* read.c: Likewise.
* symbols.c: Likewise.
* write.c: Likewise.
RISC-V: Support the ISA-dependent CSR checking. According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 18:18:49 +08:00
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
RISC-V: Support the read-only CSR checking. CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address is 0x3. The read-only CSR can not be written by the CSR instructions. gas/ * config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate we are assembling instruction with CSR. Call riscv_csr_read_only_check after parsing all arguments. (enum csr_insn_type): New enum is used to classify the CSR instruction. (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These are used to check if we write a read-only CSR by the CSR instruction. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test all CSR for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test all CSR instructions for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
2020-02-12 18:18:51 +08:00
* config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate
we are assembling instruction with CSR. Call riscv_csr_read_only_check
after parsing all arguments.
(enum csr_insn_type): New enum is used to classify the CSR instruction.
(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
are used to check if we write a read-only CSR by the CSR instruction.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
all CSR for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
all CSR instructions for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
RISC-V: Disable the CSR checking by default. Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check /-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR checking by default. gas/ * config/tc-riscv.c: Add new .option and GAS options to enbale/disable the CSR checking. We disable the CSR checking by default. (reg_lookup_internal): Check the `riscv_opts.csr_check` before we doing the CSR checking. * doc/c-riscv.texi: Add description for the new .option and assembler options. * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable the CSR checking. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
2020-02-12 18:18:50 +08:00
* config/tc-riscv.c (struct riscv_set_options): New field csr_check.
(riscv_opts): Initialize it.
(reg_lookup_internal): Check the `riscv_opts.csr_check`
before doing the CSR checking.
(enum options): Add OPTION_CSR_CHECK and OPTION_NO_CSR_CHECK.
(md_longopts): Add mcsr-check and mno-csr-check.
(md_parse_option): Handle new enum option values.
(s_riscv_option): Handle new long options.
* doc/c-riscv.texi: Add description for the new .option and assembler
options.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
the CSR checking.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
RISC-V: Support the ISA-dependent CSR checking. According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-12 18:18:49 +08:00
* config/tc-riscv.c (csr_extra_hash): New.
(enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hashes): New. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(reg_lookup_internal): Call reg_csr_lookup_internal for CSRs.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
pdp11 reloc processing This allows pdp11 to handle 32-bit fixups that can be applied by gas, and improves the error message emitted when the required reloc isn't available. * config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32. (tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
2020-02-20 21:05:21 +08:00
2020-02-21 Alan Modra <amodra@gmail.com>
* config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32.
(tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
PR25569, PDP11 ld -s clobbers last data byte This patch fixes an ancient wart in aout support, in that text and data section sizes are rounded up for alignment rather that just the corresponding header sizes. Changing section sizes could conceivably result in buffer overflows if section contents were held in memory. Also, keeping the original section sizes allows this PR to be fixed nicely. bfd/ PR 25569 * aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use "text", "data" and "bss" section pointer vars. Don't update section size, just exec header sizes. (adjust_sizes_and_vmas): Don't update text section size. Set initial exec header a_text. Print exec headers sizes. * pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic), (adjust_sizes_and_vmas): Similarly. Formatting. (final_link): Correct final file extension. gas/ PR 25569 * config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop on section size adjustment, instead perform another write if exec header size is larger than section size.
2020-02-20 19:23:44 +08:00
2020-02-21 Alan Modra <amodra@gmail.com>
PR 25569
* config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop
on section size adjustment, instead perform another write if
exec header size is larger than section size.
RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc. gas/ * doc/c-riscv.texi: Add the doc entries for -march-attr/ -mno-arch-attr command line options.
2020-02-06 11:14:21 +08:00
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
* doc/c-riscv.texi: Add the doc entries for -march-attr/
-mno-arch-attr command line options.
RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. 2020-02-19 Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/c-add-addi.d: New testcase. * testsuite/gas/riscv/c-add-addi.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed c.mv/c.li if rs1 is zero. Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
2020-02-20 06:51:07 +08:00
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/c-add-addi.d: New testcase.
* testsuite/gas/riscv/c-add-addi.s: Likewise.
Various fixes for the Z80 support. PR 25537 ld * emultempl/z80.em: Remove machine compatability checking. PR 25517 * testsuite/ld-z80/arch_ez80_adl.d: Update command line. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80n.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z80_ez80.d: Likewise. * testsuite/ld-z80/comb_arch_z80_z180.d: Likewise. * testsuite/ld-z80/comb_arch_z80_z80n.d: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_ez80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80n.d: Likewise. bfd * cpu-z80.c: Add machine type compatibility checking. gas * config/tc-z80.c (md_parse_option): Do not use an underscore prefix for local labels in SDCC compatability mode. (z80_start_line_hook): Remove SDCC dollar label support. * testsuite/gas/z80/sdcc.d: Update expected disassembly. * testsuite/gas/z80/sdcc.s: Likewise. * config/tc-z80.c: Add -march option. * doc/as.texi: Update Z80 documentation. * doc/c-z80.texi: Likewise. * testsuite/gas/z80/ez80_adl_all.d: Update command line. * testsuite/gas/z80/ez80_adl_suf.d: Likewise. * testsuite/gas/z80/ez80_pref_dis.d: Likewise. * testsuite/gas/z80/ez80_z80_all.d: Likewise. * testsuite/gas/z80/ez80_z80_suf.d: Likewise. * testsuite/gas/z80/gbz80_all.d: Likewise. * testsuite/gas/z80/r800_extra.d: Likewise. * testsuite/gas/z80/r800_ii8.d: Likewise. * testsuite/gas/z80/r800_z80_doc.d: Likewise. * testsuite/gas/z80/sdcc.d: Likewise. * testsuite/gas/z80/z180.d: Likewise. * testsuite/gas/z80/z180_z80_doc.d: Likewise. * testsuite/gas/z80/z80_doc.d: Likewise. * testsuite/gas/z80/z80_ii8.d: Likewise. * testsuite/gas/z80/z80_in_f_c.d: Likewise. * testsuite/gas/z80/z80_op_ii_ld.d: Likewise. * testsuite/gas/z80/z80_out_c_0.d: Likewise. * testsuite/gas/z80/z80_sli.d: Likewise. * testsuite/gas/z80/z80n_all.d: Likewise. * testsuite/gas/z80/z80n_reloc.d: Likewise.
2020-02-20 01:46:10 +08:00
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25576
* config/tc-z80.c (md_parse_option): Do not use an underscore
prefix for local labels in SDCC compatability mode.
(z80_start_line_hook): Remove SDCC dollar label support.
* testsuite/gas/z80/sdcc.d: Update expected disassembly.
* testsuite/gas/z80/sdcc.s: Likewise.
2020-02-19 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25517
* config/tc-z80.c: Add -march option.
* doc/as.texi: Update Z80 documentation.
* doc/c-z80.texi: Likewise.
* testsuite/gas/z80/ez80_adl_all.d: Update command line.
* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
* testsuite/gas/z80/ez80_z80_all.d: Likewise.
* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
* testsuite/gas/z80/gbz80_all.d: Likewise.
* testsuite/gas/z80/r800_extra.d: Likewise.
* testsuite/gas/z80/r800_ii8.d: Likewise.
* testsuite/gas/z80/r800_z80_doc.d: Likewise.
* testsuite/gas/z80/sdcc.d: Likewise.
* testsuite/gas/z80/z180.d: Likewise.
* testsuite/gas/z80/z180_z80_doc.d: Likewise.
* testsuite/gas/z80/z80_doc.d: Likewise.
* testsuite/gas/z80/z80_ii8.d: Likewise.
* testsuite/gas/z80/z80_in_f_c.d: Likewise.
* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
* testsuite/gas/z80/z80_out_c_0.d: Likewise.
* testsuite/gas/z80/z80_sli.d: Likewise.
* testsuite/gas/z80/z80n_all.d: Likewise.
* testsuite/gas/z80/z80n_reloc.d: Likewise.
x86: Mark cvtpi2ps and cvtpi2pd as MMX * config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd with GNU_PROPERTY_X86_FEATURE_2_MMX. * testsuite/gas/i386/i386.exp: Run property-3 and x86-64-property-3. * testsuite/gas/i386/property-3.d: New file. * testsuite/gas/i386/property-3.s: Likewise. * testsuite/gas/i386/x86-64-property-3.d: Likewise.
2020-02-19 20:54:45 +08:00
2020-02-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd
with GNU_PROPERTY_X86_FEATURE_2_MMX.
* testsuite/gas/i386/i386.exp: Run property-3 and
x86-64-property-3.
* testsuite/gas/i386/property-3.d: New file.
* testsuite/gas/i386/property-3.s: Likewise.
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
x86: Remove CpuABM and add CpuPOPCNT AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt which used to be the part of SSE4.2. This patch removes CpuABM and adds CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2 to also enable popcnt. gas/ * config/tc-i386.c (cpu_arch): Add .popcnt. * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt. Add a tab before @samp{.sse4a}. opcodes/ * i386-gen.c (cpu_flag_init): Replace CpuABM with CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add CPU_POPCNT_FLAGS. (cpu_flags): Remove CpuABM. Add CpuPOPCNT. * i386-opc.h (CpuABM): Removed. (CpuPOPCNT): New. (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on popcnt. Remove CpuABM from lzcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-02-17 23:12:10 +08:00
2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .popcnt.
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
Add a tab before @samp{.sse4a}.
x86: fold AddrPrefixOpReg templates There's no need to have separate Cpu64 and CpuNo64 templates: There already is special logic handling the attribute, and all that's needed is rejecting 16-bit address registers in 64-bit mode. Suppress suffix guessing and group all involved logic together, outside of suffix processing (arguably it doesn't even belong in process_suffix()). Also, since no AddrPrefixOpReg template permits any suffixes, move the No_*Suf specifiers for them to a central place. Along with this drop the no longer relevant NoRex64 from there.
2020-02-17 15:59:07 +08:00
2020-02-17 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Don't try to guess a suffix
for AddrPrefixOpReg templates. Combine the two pieces of
addrprefixopreg handling. Reject 16-bit address reg in 64-bit
mode.
x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X} Generally, the documentation doesn't allow for any explicit operands to be specified with MONITOR/MWAIT. To permit the more legible overriding of the address size via specifying operands, the option is being retained even in Intel mode, but operand swapping is being suppressed by this patch. This is both because it makes no sense here (all of the operands are inputs) and because, as a result, old gcc (prior to 4.8) actually expects it this way with -mintel-syntax (and hence gets fixed by this change rather than, as claimed by a reply in the bug report, broken).
2020-02-17 15:57:54 +08:00
2020-02-17 Jan Beulich <jbeulich@suse.com>
PR gas/14439
* config/tc-i386.c (md_assemble): Also suppress operand
swapping for MONITOR{,X} and MWAIT{,X}.
* testsuite/gas/i386/sse3.s, testsuite/gas/i386/x86-64-sse3.s:
Add Intel syntax monitor/mwait tests.
* testsuite/gas/i386/sse3.d, testsuite/gas/i386/x86-64-sse3.d:
Adjust expectations.
*testsuite/gas/i386/sse3-intel.d,
testsuite/gas/i386/x86-64-sse3-intel.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86/Intel: improve diagnostics for ambiguous VCVT* operands Conversions which shrink element size and which have a memory source can't be disambiguated between their 128- and 256-bit variants by looking at the register operand. "operand size mismatch", however, is a pretty misleading diagnostic. Generalize the logic introduced for VFPCLASSP{S,D} such that, with suitable similar adjustments to the respective templates, it'll cover these cases too. For VCVTNEPS2BF16 also fold the two previously separate AVX512VL templates to achieve the intended effect. This is then also accompanied by a respective addition to the inval-avx512f testcase.
2020-02-17 15:56:18 +08:00
2020-02-17 Jan Beulich <jbeulich@suse.com>
PR gas/6518
* config/tc-i386.c (process_suffix): Re-work Intel-syntax
[XYZ]MMWord memory operand ambiguity recognition logic (largely
re-indentation).
* testsuite/gas/i386/avx512dq-inval.s: Add vcvtqq2ps/vcvtuqq2ps
cases.
* testsuite/gas/i386/inval-avx512f.s: Also test vcvtneps2bf16.
* testsuite/gas/i386/avx512dq-inval.l,
testsuite/gas/i386/inval-avx.l,
testsuite/gas/i386/inval-avx512f.l: Adjust expectations.
* testsuite/gas/i386/avx512vl-ambig.s,
testsuite/gas/i386/avx512vl-ambig.l: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: Don't disable SSE4a when disabling SSE4 commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also adds .sse4a and nosse4a. gas/ * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore nosse4. * doc/c-i386.texi: Document sse4a and nosse4a. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove CPU_ANY_SSE4_FLAGS.
2020-02-17 00:36:51 +08:00
2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
nosse4.
* doc/c-i386.texi: Document sse4a and nosse4a.
Remove the old movsx and movzx documentation for AT&T syntax * doc/c-i386.texi: Remove the old movsx and movzx documentation for AT&T syntax.
2020-02-14 22:09:28 +08:00
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
* doc/c-i386.texi: Remove the old movsx and movzx documentation
for AT&T syntax.
x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix. Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that it is against my own intentions to have MOVSX/MOVZX silently default to a byte source in AT&T mode. This should happen only when the destination register is a 16-bit one. In all other cases there is an ambiguity, and the user should be warned. But it was explicitly requested for this to be done in a way inconsistent with everything else. Note finally that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one.
2020-02-14 21:27:28 +08:00
2020-02-14 Jan Beulich <jbeulich@suse.com>
PR gas/25438
* config/tc-i386.c (md_assemble): Move movsx/movzx special
casing ...
(process_suffix): ... here. Consider just the first operand
initially.
(check_long_reg): Drop opcode 0x63 special case again.
* testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s,
testsuite/gas/i386/ilp32/x86-64.s, testsuite/gas/i386/x86_64.s:
Move ambiguous operand size tests ...
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: ... here.
* testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d
testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d,
testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l,
testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.d,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
testsuite/gas/i386/x86-64-movsxd.d,
testsuite/gas/i386/x86-64-movsxd-intel.d,
testsuite/gas/i386/x86_64.d, testsuite/gas/i386/x86_64-intel.d:
Adjust expectations.
* testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l,
testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l,
testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: adjust segment override prefix emission Since we already suppress the prefix altogether when it's the default one for the chosen addressing mode, let's do so also when instruction prefix and override specified with the memory operand match. (Note that insn prefix specified segment overrides never get discarded.)
2020-02-14 21:04:23 +08:00
2020-02-14 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_operands): Also skip segment
override prefix emission if it matches an already present one.
* testsuite/gas/i386/prefix32.s: Add double segment override
cases.
* testsuite/gas/i386/prefix32.l: Adjust expectations.
x86: optimize away pointless segment overrides When optimizing there's no point keeping the segment overrides when we warn about their presence in the first place.
2020-02-14 21:03:19 +08:00
2020-02-14 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_operands): Drop ineffectual segment
overrides when optimizing.
* testsuite/gas/i386/lea-optimize.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
2020-02-14 Jan Beulich <jbeulich@suse.com>
x86: extend LEA's segment override warning For one both possible forms should be warned about. And then, to guard against future surprises, qualify the original opcode check by excluding VEX/EVEX-like templates.
2020-02-14 21:02:05 +08:00
* config/tc-i386.c (process_operands): Also check insn prefix
for ineffectual segment override warning. Don't cover possible
VEX/EVEX encoded insns there.
* testsuite/gas/i386/lea.s, testsuite/gas/i386/lea.d,
testsuite/gas/i386/lea.e: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: Document movsx/movsxd/movzx for AT&T syntax Document different mnemonics of movsx, movsxd and movzx in AT&T syntax. PR gas/25438 * doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T syntax.
2020-02-14 20:57:01 +08:00
2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25438
* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
syntax.
x86: Resolve PLT32 reloc aganst local symbol to section Since PLT entry isn't needed for branch to local symbol, we can resolve R_386_PLT32/R_X86_64_PLT32 relocation aganst local symbol to section, similar to R_386_PC32/R_X86_64_PC32. 2020-02-13 Fangrui Song <maskray@google.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/25551 * config/tc-i386.c (tc_i386_fix_adjustable): Don't check BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32. * testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4. * testsuite/gas/i386/relax-5.d: New file. * testsuite/gas/i386/relax-5.s: Likewise. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. * testsuite/gas/i386/x86-64-relax-4.s: Likewise.
2020-02-14 05:44:17 +08:00
2020-02-13 Fangrui Song <maskray@google.com>
H.J. Lu <hongjiu.lu@intel.com>
PR gas/25551
* config/tc-i386.c (tc_i386_fix_adjustable): Don't check
BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32.
* testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4.
* testsuite/gas/i386/relax-5.d: New file.
* testsuite/gas/i386/relax-5.s: Likewise.
* testsuite/gas/i386/x86-64-relax-4.d: Likewise.
* testsuite/gas/i386/x86-64-relax-4.s: Likewise.
x86: fix SSE4a dependencies of ".arch .nosse*" Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
2020-02-13 17:19:28 +08:00
2020-02-13 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in
"nosse4" entry.
x86: correct VFPCLASSP{S,D} operand size handling With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
2020-02-12 23:20:56 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (avx512): New (at file scope), moved from
(check_VecOperands): ... here.
(process_suffix): Add [XYZ]MMword operand size handling.
* testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests.
* testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS
tests.
* testsuite/gas/i386/avx512dq-inval.l,
testsuite/gas/i386/noavx512-2.l: Adjust expectations.
x86-64: Intel64 adjustments for insns dealing with far pointers AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-02-12 23:19:03 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
PR gas/24546
* config/tc-i386.c (match_template): Apply AMD64 check to 64-bit
code only.
* config/tc-i386-intel.c (i386_intel_operand): Also handle
CALL/JMP in O_tbyte_ptr case.
* doc/c-i386.texi: Mention far call and full pointer load ISA
differences.
* testsuite/gas/i386/x86-64-branch-3.s,
testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
* testsuite/gas/i386/x86-64-branch-3.d,
testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
* testsuite/gas/i386/x86-64-branch-5.l,
testsuite/gas/i386/x86-64-branch-5.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: also disallow non-byte/-word registers with byte/word suffix Along the lines of be4c5e58bd ("x86: Always disallow double word suffix with word general register") also adjust check_{byte,word}_reg(), to make overall behavior consistent again in this regard.
2020-02-12 17:59:32 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
PR gas/25438
* config/tc-i386.c (REGISTER_WARNINGS): Delete.
(check_byte_reg): Skip only source operand of CRC32. Drop Non-
64-bit-only warning.
(check_word_reg): Consistently error on mismatching register
size and suffix.
* testsuite/gas/i386/general.s: Replace dword GPR with word one
for movw. Replace suffix / GPR for orb.
* testsuite/gas/i386/inval.s: Add tests for movw with dword and
byte GPRs as well as ones for inb/outb with a word accumulator.
* testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l,
testsuite/gas/i386/inval.l: Adjust expectations.
x86/Intel: improve diagnostics The diagnostics issued by check_*_reg() are pretty AT&T-centric. Re-use logic already used for SIMD memory operand size checking also for ones where GPRs would alternatively also be allowed. (There's certainly room for further improvement here.)
2020-02-12 17:58:42 +08:00
2020-02-12 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_register_match): Also fall
through initial two if()-s when the template allows for a GPR
operand. Adjust comment.
x86: drop ShortForm attribute It is very simple to derive from other template properties, and hence there's little point wasting storage for it.
2020-02-11 18:20:55 +08:00
2020-02-11 Jan Beulich <jbeulich@suse.com>
(struct _i386_insn): New field "short_form".
(optimize_encoding): Drop setting of shortform field.
(process_suffix): Set i.short_form. Replace shortform use.
(process_operands): Replace shortform use.
[binutils][gas] Fix build failure with -std=c89 My previous patch introduced the use of a C99 feature. C99 standard is not required for gas, so this feature should be removed. Committed as obvious. gas/ChangeLog: 2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (vcx_handle_register_arguments): Remove `for` loop initial declaration.
2020-02-11 18:17:33 +08:00
2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (vcx_handle_register_arguments): Remove `for`
loop initial declaration.
[binutils][arm] Implement Custom Datapath Extensions for MVE Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.
2020-02-11 00:39:02 +08:00
2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
instructions that can have 5 arguments.
(enum operand_parse_code): Add new operands.
(parse_operands): Account for new operands.
(S5): New macro.
(enum neon_shape_el): Introduce P suffixes for coprocessor.
(neon_select_shape): Account for P suffix.
(LOW1): Move macro to global position.
(HI4): Move macro to global position.
(vcx_assign_vec_d): New.
(vcx_assign_vec_m): New.
(vcx_assign_vec_n): New.
(enum vcx_reg_type): New.
(vcx_get_reg_type): New.
(vcx_size_pos): New.
(vcx_vec_pos): New.
(vcx_handle_shape): New.
(vcx_ensure_register_in_range): New.
(vcx_handle_register_arguments): New.
(vcx_handle_insn_block): New.
(vcx_handle_common_checks): New.
(do_vcx1): New.
(do_vcx2): New.
(do_vcx3): New.
* testsuite/gas/arm/cde-missing-fp.d: New test.
* testsuite/gas/arm/cde-missing-fp.l: New test.
* testsuite/gas/arm/cde-missing-mve.d: New test.
* testsuite/gas/arm/cde-missing-mve.l: New test.
* testsuite/gas/arm/cde-mve-or-neon.d: New test.
* testsuite/gas/arm/cde-mve-or-neon.s: New test.
* testsuite/gas/arm/cde-mve.s: New test.
* testsuite/gas/arm/cde-warnings.l:
* testsuite/gas/arm/cde-warnings.s:
* testsuite/gas/arm/cde.d:
* testsuite/gas/arm/cde.s:
[binutils][arm] arm support for ARMv8.m Custom Datapath Extension This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-11 00:38:00 +08:00
2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_ext_cde*): New feature sets for each
CDE coprocessor that can be enabled.
(enum pred_instruction_type): New pred type.
(BAD_NO_VPT): New error message.
(BAD_CDE): New error message.
(BAD_CDE_COPROC): New error message.
(enum operand_parse_code): Add new immediate operands.
(parse_operands): Account for new immediate operands.
(check_cde_operand): New.
(cde_coproc_enabled): New.
(cde_coproc_pos): New.
(cde_handle_coproc): New.
(cxn_handle_predication): New.
(do_custom_instruction_1): New.
(do_custom_instruction_2): New.
(do_custom_instruction_3): New.
(do_cx1): New.
(do_cx1a): New.
(do_cx1d): New.
(do_cx1da): New.
(do_cx2): New.
(do_cx2a): New.
(do_cx2d): New.
(do_cx2da): New.
(do_cx3): New.
(do_cx3a): New.
(do_cx3d): New.
(do_cx3da): New.
(handle_pred_state): Define new IT block behaviour.
(insns): Add newn CX*{,d}{,a} instructions.
(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
Define new cdecp extension strings.
* doc/c-arm.texi: Document new cdecp extension arguments.
* testsuite/gas/arm/cde-scalar.d: New test.
* testsuite/gas/arm/cde-scalar.s: New test.
* testsuite/gas/arm/cde-warnings.d: New test.
* testsuite/gas/arm/cde-warnings.l: New test.
* testsuite/gas/arm/cde-warnings.s: New test.
* testsuite/gas/arm/cde.d: New test.
* testsuite/gas/arm/cde.s: New test.
x86: Accept Intel64 only instruction by default Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by default. By default, assembler should accept common, Intel64 only and AMD64 ISAs since there are no conflicts. gas/ PR gas/25516 * config/tc-i386.c (intel64): Renamed to ... (isa64): This. (match_template): Accept Intel64 only instruction by default. (i386_displacement): Updated. (md_parse_option): Updated. * c-i386.texi: Update -mamd64/-mintel64 documentation. * testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass -mamd64 to x86-64-sysenter-amd. * testsuite/gas/i386/x86-64-sysenter.d: New file. opcodes/ PR gas/25516 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 with ISA64. * i386-opc.h (AMD64): Removed. (Intel64): Likewose. (AMD64): New. (INTEL64): Likewise. (INTEL64ONLY): Likewise. (i386_opcode_modifier): Replace amd64 and intel64 with isa64. * i386-opc.tbl (Amd64): New. (Intel64): Likewise. (Intel64Only): Likewise. Replace AMD64 with Amd64. Update sysenter/sysenter with Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. * i386-tbl.h: Regenerated.
2020-02-11 00:37:22 +08:00
2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
gas: error for section type, attr, or entsize change * config/obj-elf.c (obj_elf_change_section): Error for section type, attr or entsize changes in assembly. * testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test. * testsuite/gas/elf/section5.l: Update.
2020-02-06 22:12:45 +08:00
2020-02-10 Alan Modra <amodra@gmail.com>
* config/obj-elf.c (obj_elf_change_section): Error for section
type, attr or entsize changes in assembly.
* testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test.
* testsuite/gas/elf/section5.l: Update.
gas -Z flag -Z is supposed to "generate object file even after errors". It doesn't do so at the moment, unless you count a zero length object file as useful output. Fixed for most targets as follows. I suspect avr and pru need target patches. * output-file.c (output_file_close): Do a normal close when flag_always_generate_output. * write.c (write_object_file): Don't stop output when flag_always_generate_output.
2020-02-10 08:57:16 +08:00
2020-02-10 Alan Modra <amodra@gmail.com>
* output-file.c (output_file_close): Do a normal close when
flag_always_generate_output.
* write.c (write_object_file): Don't stop output when
flag_always_generate_output.
Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-07 22:53:46 +08:00
2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25469
* config/tc-z80.c: Add -gbz80 command line option to generate code
for the GameBoy Z80. Add support for generating DWARF.
* config/tc-z80.h: Add support for DWARF debug information
generation.
* doc/c-z80.texi: Document new command line option.
* testsuite/gas/z80/gbz80_all.d: New file.
* testsuite/gas/z80/gbz80_all.s: New file.
* testsuite/gas/z80/z80.exp: Run the new tests.
* testsuite/gas/z80/z80n_all.d: New file.
* testsuite/gas/z80/z80n_all.s: New file.
* testsuite/gas/z80/z80n_reloc.d: New file.
ELF: Support the section flag 'o' in .section directive As shown in https://sourceware.org/bugzilla/show_bug.cgi?id=25490 --gc-sections will silently remove __patchable_function_entries section and generate corrupt result. This patch adds the section flag 'o' to .section directive: .section __patchable_function_entries,"awo",@progbits,foo .section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat .section __patchable_function_entries,"awo",@progbits,bar,unique,4 .section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1 which specifies the symbol name which the section references. Assmebler will set its elf_linked_to_section to a local section where the symbol is defined. Linker is updated to call mark_hook if gc_mark of any of its linked-to sections is set after all sections, except for backend specific ones, have been garbage collected. bfd/ PR gas/25381 * bfd-in2.h: Regenerated. * elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook on section if gc_mark of any of its linked-to sections is set and don't set gc_mark again. * section.c (asection): Add linked_to_symbol_name to map_head union. gas/ PR gas/25381 * config/obj-elf.c (get_section): Also check linked_to_symbol_name. (obj_elf_change_section): Also set map_head.linked_to_symbol_name. (obj_elf_parse_section_letters): Handle the 'o' flag. (build_group_lists): Renamed to ... (build_additional_section_info): This. Set elf_linked_to_section from map_head.linked_to_symbol_name. (elf_adjust_symtab): Updated. * config/obj-elf.h (elf_section_match): Add linked_to_symbol_name. * doc/as.texi: Document the 'o' flag. * testsuite/gas/elf/elf.exp: Run PR gas/25381 tests. * testsuite/gas/elf/section18.d: New file. * testsuite/gas/elf/section18.s: Likewise. * testsuite/gas/elf/section19.d: Likewise. * testsuite/gas/elf/section19.s: Likewise. * testsuite/gas/elf/section20.d: Likewise. * testsuite/gas/elf/section20.s: Likewise. * testsuite/gas/elf/section21.d: Likewise. * testsuite/gas/elf/section21.l: Likewise. * testsuite/gas/elf/section21.s: Likewise. ld/ PR ld/24526 PR ld/25021 PR ld/25490 * testsuite/ld-elf/elf.exp: Run PR ld/25490 tests. * testsuite/ld-elf/pr24526.d: New file. * testsuite/ld-elf/pr24526.s: Likewise. * testsuite/ld-elf/pr25021.d: Likewise. * testsuite/ld-elf/pr25021.s: Likewise. * testsuite/ld-elf/pr25490-2-16.rd: Likewise. * testsuite/ld-elf/pr25490-2-32.rd: Likewise. * testsuite/ld-elf/pr25490-2-64.rd: Likewise. * testsuite/ld-elf/pr25490-2.s: Likewise. * testsuite/ld-elf/pr25490-3-16.rd: Likewise. * testsuite/ld-elf/pr25490-3-32.rd: Likewise. * testsuite/ld-elf/pr25490-3-64.rd: Likewise. * testsuite/ld-elf/pr25490-3.s: Likewise. * testsuite/ld-elf/pr25490-4-16.rd: Likewise. * testsuite/ld-elf/pr25490-4-32.rd: Likewise. * testsuite/ld-elf/pr25490-4-64.rd: Likewise. * testsuite/ld-elf/pr25490-4.s: Likewise. * testsuite/ld-elf/pr25490-5-16.rd: Likewise. * testsuite/ld-elf/pr25490-5-32.rd: Likewise. * testsuite/ld-elf/pr25490-5-64.rd: Likewise. * testsuite/ld-elf/pr25490-5.s: Likewise. * testsuite/ld-elf/pr25490-6-16.rd: Likewise. * testsuite/ld-elf/pr25490-6-32.rd: Likewise. * testsuite/ld-elf/pr25490-6-64.rd: Likewise. * testsuite/ld-elf/pr25490-6.s: Likewise.
2020-02-07 10:04:58 +08:00
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25381
* config/obj-elf.c (get_section): Also check
linked_to_symbol_name.
(obj_elf_change_section): Also set map_head.linked_to_symbol_name.
(obj_elf_parse_section_letters): Handle the 'o' flag.
(build_group_lists): Renamed to ...
(build_additional_section_info): This. Set elf_linked_to_section
from map_head.linked_to_symbol_name.
(elf_adjust_symtab): Updated.
* config/obj-elf.h (elf_section_match): Add linked_to_symbol_name.
* doc/as.texi: Document the 'o' flag.
* testsuite/gas/elf/elf.exp: Run PR gas/25381 tests.
* testsuite/gas/elf/section18.d: New file.
* testsuite/gas/elf/section18.s: Likewise.
* testsuite/gas/elf/section19.d: Likewise.
* testsuite/gas/elf/section19.s: Likewise.
* testsuite/gas/elf/section20.d: Likewise.
* testsuite/gas/elf/section20.s: Likewise.
* testsuite/gas/elf/section21.d: Likewise.
* testsuite/gas/elf/section21.l: Likewise.
* testsuite/gas/elf/section21.s: Likewise.
[2.34] Mention x86 assembler options to align branches * NEWS: Mention x86 assembler options to align branches for binutils 2.34.
2020-02-06 23:50:16 +08:00
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention x86 assembler options to align branches for
binutils 2.34.
x86: Run unique tests only for ELF targets * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique only for ELF targets. * testsuite/gas/i386/unique.d: Don't xfail. * testsuite/gas/i386/x86-64-unique.d: Likewise.
2020-02-06 20:44:39 +08:00
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique
only for ELF targets.
* testsuite/gas/i386/unique.d: Don't xfail.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
xfail x86 gas unique test * testsuite/gas/i386/unique.d: xfail for non-elf targets. * testsuite/gas/i386/x86-64-unique.d: Likewise.
2020-02-06 08:22:29 +08:00
2020-02-06 Alan Modra <amodra@gmail.com>
* testsuite/gas/i386/unique.d: xfail for non-elf targets.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
mbind gas tests and supports_gnu_osabi testsuite infrastructure With the addition of section16 tests we have multiple tests advertising themselves as "mbind sections" and "mbind section contents". This patch fixes that, and fails on quite a few targets that force an OSABI value. It's a pain specifying all the relevant arm targets on an xfail line, so I wrote supports_gnu_osabi. binutils/ * testsuite/lib/binutils-common.exp (match_target): Accept '!' before TCL procedure. (supports_gnu_osabi): New procedure. (is_generic): New, from ld-lib.exp. (supports_gnu_unique): Use the above. gas/ * testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in xfail, and rename test. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. ld/ * testsuite/lib/ld-lib.exp (is_generic): Delete. * testsuite/ld-unique/unique.exp: Exclude tic6x.
2020-02-05 13:49:17 +08:00
2020-02-06 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in
xfail, and rename test.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
ELF: Add support for unique section ID to assembler Clang's integrated assembler supports multiple section with the same name: .section .text,"ax",@progbits,unique,1 nop .section .text,"ax",@progbits,unique,2 nop "unique,N" assigns the number, N, as the section ID, to a section. The valid values of the section ID are between 0 and 4294967295. It can be used to distinguish different sections with the same section name. This is useful with -fno-unique-section-names -ffunction-sections. -ffunction-sections by default generates .text.foo, .text.bar, etc. Using the same string can save lots of space in .strtab. This patch adds section_id to bfd_section and reuses the linker internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler internal use to mark valid section_id. It also updates objdump to compare section pointers if 2 sections comes from the same file since 2 different sections can have the same section name. bfd/ PR gas/25380 * bfd-in2.h: Regenerated. * ecoff.c (bfd_debug_section): Add section_id. * section.c (bfd_section): Add section_id. (SEC_ASSEMBLER_SECTION_ID): New. (BFD_FAKE_SECTION): Add section_id. binutils/ PR gas/25380 * objdump.c (sym_ok): Return FALSE if 2 sections are in the same file with different section pointers. gas/ PR gas/25380 * config/obj-elf.c (section_match): Removed. (get_section): Also match SEC_ASSEMBLER_SECTION_ID and section_id. (obj_elf_change_section): Replace info and group_name arguments with match_p. Also update the section ID and flags from match_p. (obj_elf_section): Handle "unique,N". Update call to obj_elf_change_section. * config/obj-elf.h (elf_section_match): New. (obj_elf_change_section): Updated. * config/tc-arm.c (start_unwind_section): Update call to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texi: Document "unique,N" in .section directive. * testsuite/gas/elf/elf.exp: Run "unique,N" tests. * testsuite/gas/elf/section15.d: New file. * testsuite/gas/elf/section15.s: Likewise. * testsuite/gas/elf/section16.s: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. * testsuite/gas/elf/section17.d: Likewise. * testsuite/gas/elf/section17.l: Likewise. * testsuite/gas/elf/section17.s: Likewise. * testsuite/gas/i386/unique.d: Likewise. * testsuite/gas/i386/unique.s: Likewise. * testsuite/gas/i386/x86-64-unique.d: Likewise. * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique. ld/ PR gas/25380 * testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section directives. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-02-03 09:07:51 +08:00
2020-02-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
elf/section13.s: Replace @nobits with %nobits * testsuite/gas/elf/section13.s: Replace @nobits with %nobits.
2020-02-03 00:20:18 +08:00
2020-02-02 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/elf/section13.s: Replace @nobits with %nobits.
moxie: don't force big-endian mode
2020-02-02 09:59:19 +08:00
2020-02-01 Anthony Green <green@moxielogic.com>
* config/tc-moxie.c (md_begin): Don't force big-endian mode.
nios2: recognize %gotoff relocation in assembler The nios2 ABI documentation lists %gotoff as assembler syntax for the R_NIOS2_GOTOFF relocation, used to represent a 32-bit GOT-relative offset in data sections. This was previously unimplemented in GAS. 2020-01-31 Sandra Loosemore <sandra@codesourcery.com> gas/ * config/tc-nios2.c (nios2_cons): Handle %gotoff as well as %tls_ldo.
2020-02-01 02:32:48 +08:00
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
* config/tc-nios2.c (nios2_cons): Handle %gotoff as well as
%tls_ldo.
Add missing ChangeLog for last patch
2020-02-01 01:13:18 +08:00
2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25472
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for
+mve.
* testsuite/gas/arm/mve_dsp.d: New test.
Fix compile time build problem building the s390 assembler. * config/tc-s390.c (s390_elf_suffix): Return ELF_SUFFIX_NONE rather than BFD_RELOC_NONE.
2020-02-01 00:43:57 +08:00
2020-01-31 Nick Clifton <nickc@redhat.com>
* config/tc-s390.c (s390_elf_suffix): Return ELF_SUFFIX_NONE
rather than BFD_RELOC_NONE.
[ARM]: Add support for vldmia/vldmdb/vstmia/vstmdb instructions in MVE. This patch adds support for assembly instructions vldmia, vldmdb, vstmia and vstmdb in MVE. This instructions are already supported for Armv8-M Floating-point Extension. gas/ChangeLog: 2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMIA instruction for MVE. (fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB instruction for MVE. (fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA instruction for MVE. (fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB instruction for MVE. * testsuite/gas/arm/mve-ldst.d: New test. * testsuite/gas/arm/mve-ldst.s: Likewise.
2020-02-01 00:16:19 +08:00
2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2"
to support VLDMIA instruction for MVE.
(fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB
instruction for MVE.
(fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA
instruction for MVE.
(fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB
instruction for MVE.
* testsuite/gas/arm/mve-ldst.d: New test.
* testsuite/gas/arm/mve-ldst.s: Likewise.
Updated translations for some of the binutils sub-directories
2020-01-31 22:45:51 +08:00
2020-01-31 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
* po/ru.po: Updated Russian translation.
aarch64: Fix MOVPRFX markup for bf16 conversions bfcvt converts a .S input to a .H output, so any predicated movprfx needs to operate on .S rather than .H. In common with SVE2 narrowing top operations, bfcvtnt doesn't accept movprfx. 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. Remove C_SCAN_MOVPRFX for SVE bfcvtnt. gas/ * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than .s for the movprfx. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_28.d, * testsuite/gas/aarch64/sve-movprfx_28.l, * testsuite/gas/aarch64/sve-movprfx_28.s: New test.
2020-01-31 16:03:56 +08:00
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
.s for the movprfx.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_28.d,
* testsuite/gas/aarch64/sve-movprfx_28.l,
* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
x86: prevent undue use of GOT32X and alike relocations Comparison of i.tm.base_opcode against particular but not sufficiently specific values needs to be accompanied by other qualification. Exclude VEX and alike encodings here, and also exclude all forms of prefixes explicitly specified in the opcodes table. While using @GOT with such insns may not be very useful, it also isn't with e.g. ADC and SBB, yet these get explicitly listed in comments as supported.
2020-01-31 00:03:22 +08:00
2020-01-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_disp): Tighten base_opcode check.
* testsuite/gas/i386/got.s: Add LSL, MOVLPS, and BNDCN cases.
* testsuite/gas/i386/got-no-relax.d, testsuite/gas/i386/got.d:
Adjust expectations.
cpu,opcodes,gas: fix neg and neg32 instructions in BPF This patch fixes the neg/neg32 BPF instructions, which have K (=0) instead of X (=1) in their header source bit, despite operating on registes. cpu/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-alu-insn-un): The unary BPF instructions (neg and neg32) use OP_SRC_K even if they operate only in registers. opcodes/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c: Regenerate. gas/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Update expected opcode for `neg'. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise for `neg32'. * testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 20:59:04 +08:00
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
* testsuite/gas/bpf/alu32-be.d: Likewise.
x86-64: honor vendor specifics for near RET While vendors agree about default operand size (64 bits) and hence unavilability of a 32-bit form, AMD honors a 16-bit operand size override (0x66) while Intel doesn't.
2020-01-30 18:36:33 +08:00
2020-01-30 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-branch-2.s,
testsuite/gas/i386/x86-64-branch-4.s,
testsuite/gas/i386/x86-64-branch.s: Add RETW cases.
* testsuite/gas/i386/ilp32/x86-64-branch.d,
testsuite/gas/i386/x86-64-branch-2.d,
testsuite/gas/i386/x86-64-branch-4.l,
testsuite/gas/i386/x86-64-branch.d: Adjust expectations.
x86-64: also diagnose far returns / IRET with ambiguous operand size Other than near returns these default to 32-bit operand size, and hence it isn't really unlikely that 64-bit forms are meant. Hence these should have disambiguating suffixes. In Intel mode, however, don't error in these cases unconditionally - MASM accepts these without suffix _and_ without warning.
2020-01-30 18:35:20 +08:00
2020-01-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): .
testsuite/gas/i386/noreg64.s: Add IRET and LRET cases.
testsuite/gas/i386/x86-64-opcode.s: Add suffix to IRET and LRET.
Add LRETQ case.
testsuite/gas/i386/x86-64-suffix.s: Drop IRET case without
suffix.
testsuite/gas/i386/x86_64.s: Add RETF cases.
* testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l,
testsuite/gas/i386/x86-64-opcode.d,
testsuite/gas/i386/x86-64-suffix-intel.d,
testsuite/gas/i386/x86-64-suffix.d,
testsuite/gas/i386/x86_64-intel.d
testsuite/gas/i386/x86_64.d: Adjust expectations.
* testsuite/gas/i386/x86-64-suffix.e,
testsuite/gas/i386/x86_64.e: New.
x86: drop further pointless/bogus DefaultSize - 64-bit CALL permitting just a single operand size doesn't need it. - FLDENV et al should never have had it. It remains suspicious that a number of 64-bit only insns continue to have the attribute, despite this being intended for .code16gcc handling only.
2020-01-30 18:33:53 +08:00
2020-01-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Redo and move FLDENV et al
special case.
x86-64: Properly encode and decode movsxd movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit destination registers. Its AT&T mnemonic is movslq which only supports 64-bit destination register. There is also a discrepancy between AMD64 and Intel64 on movsxd with 16-bit destination register. AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit destination registers. It also handles movsxd with 16-bit destination register for AMD64 and Intel 64. gas/ PR binutils/25445 * config/tc-i386.c (check_long_reg): Also convert to QWORD for movsxd. * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA differences. Document movslq and movsxd. * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd.d: Likewise. * testsuite/gas/i386/x86-64-movsxd.s: Likewise. opcodes/ PR binutils/25445 * i386-dis.c (MOVSXD_Fixup): New function. (movsxd_mode): New enum. (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. (intel_operand_size): Handle movsxd_mode. (OP_E_register): Likewise. (OP_G): Likewise. * i386-opc.tbl: Remove Rex64 and allow 32-bit destination register on movsxd. Add movsxd with 16-bit destination register for AMD64 and Intel64 ISAs. * i386-tbl.h: Regenerated.
2020-01-27 20:38:10 +08:00
2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/25445
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
movsxd.
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
differences. Document movslq and movsxd.
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
Replace deprecated tcl case statements with switch statements binutils/ * testsuite/lib/binutils-common.exp (big_or_little_endian): Replace case statement with switch statement. gas/ * testsuite/gas/all/gas.exp: Replace case statements with switch statements. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/macros/macros.exp: Likewise. * testsuite/lib/gas-defs.exp: Likewise. ld/ * testsuite/ld-elfvers/vers.exp: Replace case statements with switch statements. * testsuite/ld-ifunc/ifunc.exp: Likewise. * testsuite/ld-unique/unique.exp: Likewise.
2020-01-27 08:21:52 +08:00
2020-01-27 Alan Modra <amodra@gmail.com>
* testsuite/gas/all/gas.exp: Replace case statements with switch
statements.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/macros/macros.exp: Likewise.
* testsuite/lib/gas-defs.exp: Likewise.
AArch64: Fix cfinv disassembly issues This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
2020-01-27 18:40:02 +08:00
2020-01-27 Tamar Christina <tamar.christina@arm.com>
PR 25403
* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
* testsuite/gas/aarch64/armv8_4-a.s: Likewise.
RISC-V: Change -march parsing. bfd/ 2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com> * bfd/elfnn-riscv.c (riscv_skip_prefix): New. (riscv_prefix_cmp): Likewise. (riscv_non_std_ext_p): Deleted. (riscv_std_sv_ext_p): Likewise. (riscv_non_std_sv_ext_p): Likewise. (riscv_merge_non_std_and_sv_ext): Rename to... (riscv_merge_multi_letter_ext): and modified to use riscv_prefix_cmp. (riscv_merge_arch_attr_info): Replace 3 calls to riscv_merge_non_std_and_sv_ext with single call to riscv_merge_multi_letter_ext. * bfd/elfxx-riscv.c (riscv_parse_std_ext): Break if we encounter a 'z' prefix. (riscv_get_prefix_class): New function, return prefix class based on first few characters of input string. (riscv_parse_config): New structure to factor out minor differences in extension class parsing behaviour. (riscv_parse_sv_or_non_std_ext): Rename to... (riscv_parse_prefixed_ext): and parameterise with riscv_parse_config. (riscv_std_z_ext_strtab, riscv_std_s_ext_strtab): New. (riscv_multi_letter_ext_valid_p): New. (riscv_ext_x_valid_p, riscv_ext_z_valid_p, riscv_ext_s_valid_p): New. (riscv_parse_subset): Delegate all non-single-letter parsing work to riscv_parse_prefixed_ext. * bfd/elfxx-riscv.h (riscv_isa_ext_class): New type. (riscv_get_prefix_class): Declare. gas/ 2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com> * testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and s exts must be known, so rename *ok* to *fail*. * testsuite/gas/riscv/march-ok-sx.d: Likewise. * testsuite/gas/riscv/march-ok-s-with-version: Likewise. * testsuite/gas/riscv/march-fail-s.l: Expected error messages for above change. * testsuite/gas/riscv/march-fail-sx.l: Likewise. * testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise. Change-Id: Ic4d91a13d055a10d30ab28752a380a669b59f29c
2020-01-23 08:45:04 +08:00
2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com>
* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
s exts must be known, so rename *ok* to *fail*.
* testsuite/gas/riscv/march-ok-sx.d: Likewise.
* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
above change.
* testsuite/gas/riscv/march-fail-sx.l: Likewise.
* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.
x86: Always disallow double word suffix with word general register In 64-bit mode, double word suffix in mnemonic with word general register is disallowed. Otherwise, assembler gives a warning: $ cat /tmp/x.s movl %ax, %bx movl %ds, %ax movl %ax, %cs $ gcc -c /tmp/x.s /tmp/x.s: Assembler messages: /tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix /tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix /tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix $ gcc -c /tmp/x.s -m32 /tmp/x.s: Assembler messages: /tmp/x.s: Assembler messages: /tmp/x.s:1: Warning: using `%ebx' instead of `%bx' due to `l' suffix /tmp/x.s:1: Warning: using `%eax' instead of `%ax' due to `l' suffix /tmp/x.s:2: Warning: using `%eax' instead of `%ax' due to `l' suffix /tmp/x.s:3: Warning: using `%eax' instead of `%ax' due to `l' suffix This patch makes it a hard error in all modes. Now we get: $ gcc -c /tmp/x.s -m32 /tmp/x.s: Assembler messages: /tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix /tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix /tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix PR gas/25438 * config/tc-i386.c (check_long_reg): Always disallow double word suffix in mnemonic with word general register. * testsuite/gas/i386/general.s: Replace word general register with double word general register for movl. * testsuite/gas/i386/inval.s: Add tests for movl with word general register. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/inval.l: Likewise.
2020-01-23 01:24:14 +08:00
2020-01-22 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25438
* config/tc-i386.c (check_long_reg): Always disallow double word
suffix in mnemonic with word general register.
* testsuite/gas/i386/general.s: Replace word general register
with double word general register for movl.
* testsuite/gas/i386/inval.s: Add tests for movl with word general
register.
* testsuite/gas/i386/general.l: Updated.
* testsuite/gas/i386/inval.l: Likewise.
PowerPC64 __tls_get_addr_desc This implements register saving and restoring in the __tls_get_addr call stub, so that when glibc supports the optimized tls call stub gcc can generate code that assumes only r0, r12 and of course r3 are changed on a __tls_get_addr call. When gcc expects __tls_get_addr calls to preserve registers the call will be to __tls_get_addr_desc, which will be translated by the linker to a call to __tls_get_addr_opt. bfd/ * elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave. * elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and tga_desc_fd. (is_tls_get_addr): Match tga_desc and tga_desc_df too. (STDU_R1_0R1, ADDI_R1_R1): Define. (tls_get_addr_prologue, tls_get_addr_epilogue): New functions. (ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd. Indirect tga_desc_fd to opt_fd, and tga_desc to opt. Set no_tls_get_addr_regsave. (branch_reloc_hash_match): Add hash3 and hash4. (ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too. (ppc64_elf_size_dynamic_sections): Likewise. (ppc64_elf_relocate_section): Likewise. (plt_stub_size, build_plt_stub): Likewise. Size regsave __tls_get_addr stub. (build_tls_get_addr_stub): Build regsave __tls_get_addr stub and eh_frame. (ppc_size_one_stub): Handle tga_desc_fd and tga_desc too. Size eh_frame for regsave __tls_get_addr. gas/ * config/tc-ppc.c (parse_tls_arg): Handle tls arg for __tls_get_addr_desc and __tls_get_addr_opt. ld/ * emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS), (PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support --tls-get-addr-regsave and --no-tls-get-addr-regsave. (params): Init new field. * ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave): Document. * testsuite/ld-powerpc/tlsdesc.s, * testsuite/ld-powerpc/tlsdesc.d, * testsuite/ld-powerpc/tlsdesc.wf, * testsuite/ld-powerpc/tlsdesc2.d, * testsuite/ld-powerpc/tlsdesc2.wf, * testsuite/ld-powerpc/tlsexenors.d, * testsuite/ld-powerpc/tlsexenors.r, * testsuite/ld-powerpc/tlsexers.d, * testsuite/ld-powerpc/tlsexers.r, * testsuite/ld-powerpc/tlsexetocnors.d, * testsuite/ld-powerpc/tlsexetocrs.d, * testsuite/ld-powerpc/tlsexetocrs.r, * testsuite/ld-powerpc/tlsopt6.d, * testsuite/ld-powerpc/tlsopt6.wf: New. * testsuite/ld-powerpc/powerpc.exp: Run new tests.
2020-01-20 10:08:00 +08:00
2020-01-22 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
__tls_get_addr_desc and __tls_get_addr_opt.
x86: testsuite adjustments after commit 1a0351246a5c The odd behavior of certain COFF/PE targets makes necessary some mechanical adjustments.
2020-01-21 21:41:05 +08:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/inval-crc32.s,
testsuite/gas/i386/x86-64-inval-crc32.s: Add alignment directive.
* testsuite/gas/i386/inval-crc32.l,
testsuite/gas/i386/x86-64-inval-crc32.l: Adjust expectations.
x86: replace adhoc ambiguous operand checking for CRC32 There's no need (anymore?) to heavily special case this - just make generic logic consider only its first operand, and deal with the case of an 'l' suffix not being allowed in a pattern.
2020-01-21 15:30:05 +08:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Merge CRC32 handling into
generic code path. Deal with No_lSuf being set in a template.
* testsuite/gas/i386/inval-crc32.l,
testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
instead of error(s) when operand size is ambiguous.
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: Add CRC32 tests.
* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
Adjust expectations.
x86: improve handling of insns with ambiguous operand sizes Commit b76bc5d54e ("x86: don't default variable shift count insns to 8-bit operand size") pointed out a very bad case, but the underlying problem is, as mentioned on various occasions, much larger: Silently selecting a (nowhere documented afaict) certain default operand size when there's no "sizing" suffix and no suitable register operand(s) is simply dangerous (for the programmer to make mistakes). While in Intel syntax mode such mistakes already lead to an error (which is going to remain that way), AT&T syntax mode now gains warnings in such cases by default, which can be suppressed or promoted to an error if so desired by the programmer. Furthermore at least general purpose insns now consistently have a default applied (alongside the warning emission), rather than accepting some and refusing others. No warnings are (as before) to be generated for "DefaultSize" insns as well as ones acting on selector and other fixed-width values. For SYSRET, however, the DefaultSize needs to be dropped - it had been wrongly put there in the first place, as it's unrelated to .code16gcc (no stack accesses involved). As set forth as a prereq when I first mentioned this intended change a few years back, Linux as well as gcc have meanwhile been patched to avoid (emission of) ambiguous operands (and hence triggering of the new warning). Note that I think that in 64-bit mode IRET and far RET would better get a diagnostic too, as it's reasonably likely that a suffix-less instance really is meant to be a 64-bit one. But I guess I better make this a separate follow-on patch. Note further that floating point operations with integer operands are an exception for now: They continue to use short (16-bit) operands by default even in 32- and 64-bit modes. Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also need to be diagnosed, with their 64-bit forms not being very useful I think it is better to continue to avoid warning about them (by way of them carrying IgnoreSize attributes).
2020-01-21 15:28:25 +08:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Drop SYSRET special case
and an intel_syntax check. Re-write lack-of-suffix processing
logic.
* doc/c-i386.texi: Document operand size defaults for suffix-
less AT&T syntax insns.
* testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
testsuite/gas/i386/x86-64-avx-scalar.s,
testsuite/gas/i386/x86-64-avx.s,
testsuite/gas/i386/x86-64-bundle.s,
testsuite/gas/i386/x86-64-intel64.s,
testsuite/gas/i386/x86-64-lock-1.s,
testsuite/gas/i386/x86-64-opcode.s,
testsuite/gas/i386/x86-64-sse2avx.s,
testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
* testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
testsuite/gas/i386/x86-64-nops.s,
testsuite/gas/i386/x86-64-ptwrite.s,
testsuite/gas/i386/x86-64-simd.s,
testsuite/gas/i386/x86-64-sse-noavx.s,
testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
insns.
* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.s: Add further tests.
* testsuite/gas/i386/ilp32/x86-64-nops.d,
testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
testsuite/gas/i386/sse-noavx.d,
testsuite/gas/i386/x86-64-intel64.d,
testsuite/gas/i386/x86-64-nops.d,
testsuite/gas/i386/x86-64-opcode.d,
testsuite/gas/i386/x86-64-ptwrite-intel.d,
testsuite/gas/i386/x86-64-ptwrite.d,
testsuite/gas/i386/x86-64-simd-intel.d,
testsuite/gas/i386/x86-64-simd-suffix.d,
testsuite/gas/i386/x86-64-simd.d,
testsuite/gas/i386/x86-64-sse-noavx.d
testsuite/gas/i386/x86-64-suffix.d,
testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
* testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
testsuite/gas/i386/noreg64.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: VCVTNEPS2BF16{X,Y} should permit broadcasting Just like other VCVT*{X,Y} templates do, and to allow the programmer flexibility (might be relevant in particular when heavily macro-izing code), the two templates should also have Broadcast set, just like their X/Y-suffix-less counterparts. This in turn requires them to also have * Dword set on their memory operands, to cover the logic added to i386gen by 4a1b91eabbe7 ("x86: Expand Broadcast to 3 bits"), * RegXMM/RegYMM set on their source operands, to satisfy broadcast sizing logic in gas itself. Otherwise ATTSyntax templates wouldn't need such operand size attributes. While extending the test cases, also add Intel syntax broadcast forms without explicit size specifiers.
2020-01-21 15:25:31 +08:00
2020-01-21 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512_bf16_vl.s,
testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Add broadcast forms
of VCVTNEPS2BF16{X,Y}. Add operand-size less Intel syntax
broadcast forms of VCVTNEPS2BF16.
* testsuite/gas/i386/avx512_bf16_vl.d,
testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Adjust expectations.
Updated translations for various binutils sub-directories
2020-01-20 23:10:23 +08:00
2020-01-20 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
x86-64: Fix TLSDESC relaxation for x32 For x32, we must encode "lea x@TLSDESC(%rip), %reg" with a REX prefix even if it isn't required. Otherwise linker can’t safely perform GDesc -> IE/LE optimization. X32 TLSDESC sequences can be: 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg ... 67 ff 10 call *x@TLSCALL(%eax) or the same sequence as LP64: 48 8d 05 00 00 00 00 lea foo@TLSDESC(%rip), %reg ... ff 10 call *foo@TLSCALL(%rax) We need to support both sequences for x32. For both GDesc -> IE/LE transitions, 67 ff 10 call *x@TLSCALL(%eax) should relaxed to 0f 1f 00 nopl (%rax) For GDesc -> LE transition, 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg should relaxed to 40 c7 c0 fc ff ff ff rex movl $x@tpoff, %reg For GDesc -> IE transition, 40 8d 05 00 00 00 00 rex lea x@TLSDESC(%rip), %reg should relaxed to 40 8b 05 00 00 00 00 rex movl x@gottpoff(%rip), %eax bfd/ PR ld/25416 * elf64-x86-64.c (elf_x86_64_check_tls_transition): Support "rex leal x@tlsdesc(%rip), %reg" and "call *x@tlsdesc(%eax)" in X32 mode. (elf_x86_64_relocate_section): In x32 mode, for GDesc -> LE transition, relax "rex leal x@tlsdesc(%rip), %reg" to "rex movl $x@tpoff, %reg", for GDesc -> IE transition, relax "rex leal x@tlsdesc(%rip), %reg" to "rex movl x@gottpoff(%rip), %eax". For both transitions, relax "call *(%eax)" to "nopl (%rax)". gas/ PR ld/25416 * config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating x32 object. * testsuite/gas/i386/ilp32/x32-tls.d: Updated. * testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with R_X86_64_GOTPC32_TLSDESC relocation. ld/ PR ld/25416 * testsuite/ld-x86-64/pr25416-1.s: New file * testsuite/ld-x86-64/pr25416-1a.d: Likewise. * testsuite/ld-x86-64/pr25416-1b.d: Likewise. * testsuite/ld-x86-64/pr25416-1.s: Likewise. * testsuite/ld-x86-64/pr25416-2.s: Likewise. * testsuite/ld-x86-64/pr25416-2a.d: Likewise. * testsuite/ld-x86-64/pr25416-2b.d: Likewise. * testsuite/ld-x86-64/pr25416-3.d: Likewise. * testsuite/ld-x86-64/pr25416-3.s: Likewise. * testsuite/ld-x86-64/pr25416-4.d: Likewise. * testsuite/ld-x86-64/pr25416-4.s: Likewise. * testsuite/ld-x86-64/pr25416-5a.c: Likewise. * testsuite/ld-x86-64/pr25416-5b.s: Likewise. * testsuite/ld-x86-64/pr25416-5c.s: Likewise. * testsuite/ld-x86-64/pr25416-5d.s: Likewise. * testsuite/ld-x86-64/pr25416-5e.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/25416 tests.
2020-01-20 22:58:51 +08:00
2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
PR ld/25416
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
x32 object.
* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
R_X86_64_GOTPC32_TLSDESC relocation.
Update version to 2.34.50. Regenerate configure and .pot files.
2020-01-18 22:12:07 +08:00
2020-01-18 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.34 branch to the NEWS files and ChangeLogs.
2020-01-18 21:50:25 +08:00
2020-01-18 Nick Clifton <nickc@redhat.com>
Binutils 2.34 branch created.
x86: Add {vex} pseudo prefix There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix can't encode all operands. By default, assembler tries 2-byte VEX prefix first. {vex3} can be used to force 3-byte VEX prefix. This patch adds {vex} pseudo prefix and keeps {vex2} for backward compatibility. gas/ * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2 with vex_encoding_vex. (parse_insn): Likewise. * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex} and {vex3} documentation. * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with {vex}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. opcodes/ * i386-opc.tbl: Add {vex} pseudo prefix. * i386-tbl.h: Regenerated.
2020-01-17 23:07:55 +08:00
2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
with vex_encoding_vex.
(parse_insn): Likewise.
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
and {vex3} documentation.
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
{vex}.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
[binutils][arm] PR25376 Change MVE into a CORE_HIGH feature This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-16 21:50:52 +08:00
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.
x86: drop found_cpu_match local variable 50aecf8c5f could have done so right away; perhaps the variable shouldn't have been introduced in the first place.
2020-01-16 17:07:36 +08:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Drop found_cpu_match local
variable.
x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand forms accepted even outside of 64-bit mode, and this even without any {evex} pseudo-prefix (otherwise one could argue that this is an attempt to follow one possible, albeit somewhat odd, interpretation of the SDM wording to this effect). For consistency between the various involved templates drop the * (now) unnecessary IgnoreSize attributes * unnecessary (due to VexW1) Size64 attributes from VEX encoded forms * redundant (with Reg64) Qword operand attributes uniformly.
2020-01-16 17:05:35 +08:00
2020-01-16 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512dq-inval.l,
testsuite/gas/i386/avx512dq-inval.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
MSP430: Fix relocation overflow when using #lo(EXP) macro gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-15 21:17:27 +08:00
2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
relocations when the target is 430X, except when extracting part of an
expression.
(msp430_srcoperand): Adjust comment.
Initialize the expp member of the msp430_operand_s struct as
appropriate.
(msp430_dstoperand): Likewise.
* testsuite/gas/msp430/msp430.exp: Run new test.
* testsuite/gas/msp430/reloc-lo-430x.d: New test.
* testsuite/gas/msp430/reloc-lo-430x.s: New test.
Reinstate gas em=freebsd for sparc-freebsd In commit c9098af41e3 I over-simplified the sparc target decoding, missing the fact that prior to that patch sparc-*-freebsd fell through to the generic *-*-freebsd match. * configure.tgt: Add sparc-*-freebsd case.
2020-01-15 13:45:43 +08:00
2020-01-15 Alan Modra <amodra@gmail.com>
* configure.tgt: Add sparc-*-freebsd case.
x86: Updated align branch tests for Darwin and i686-pc-elf 1. Update align branch assembler tests to match Darwin disassembler outputs. 2. Skip unsupported "call *foo" tests in 64-bit mode on Darwin. 3. Update align branch linker test to match any addresses for i686-pc-elf. gas/ * testsuite/gas/i386/align-branch-1a.d: Updated for Darwin. * testsuite/gas/i386/align-branch-1b.d: Likewise. * testsuite/gas/i386/align-branch-1c.d: Likewise. * testsuite/gas/i386/align-branch-1d.d: Likewise. * testsuite/gas/i386/align-branch-1e.d: Likewise. * testsuite/gas/i386/align-branch-1f.d: Likewise. * testsuite/gas/i386/align-branch-1g.d: Likewise. * testsuite/gas/i386/align-branch-1h.d: Likewise. * testsuite/gas/i386/align-branch-1i.d: Likewise. * testsuite/gas/i386/align-branch-5.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. * testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a, x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin. ld/ * testsuite/ld-i386/align-branch-1.d: Updated for i686-pc-elf.
2020-01-15 00:59:37 +08:00
2020-01-14 Lili Cui <lili.cui@intel.com>
* testsuite/gas/i386/align-branch-1a.d: Updated for Darwin.
* testsuite/gas/i386/align-branch-1b.d: Likewise.
* testsuite/gas/i386/align-branch-1c.d: Likewise.
* testsuite/gas/i386/align-branch-1d.d: Likewise.
* testsuite/gas/i386/align-branch-1e.d: Likewise.
* testsuite/gas/i386/align-branch-1f.d: Likewise.
* testsuite/gas/i386/align-branch-1g.d: Likewise.
* testsuite/gas/i386/align-branch-1h.d: Likewise.
* testsuite/gas/i386/align-branch-1i.d: Likewise.
* testsuite/gas/i386/align-branch-5.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise.
* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.
* testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a,
x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin.
Fix various assembler testsuite failures for the Z80 target. PR 25377 gas * config/tc-z80.c: Add support for half precision, single precision and double precision floating point values. * config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes. * doc/as.texi: Add new z80 command line options. * doc/c-z80.texi: Document new z80 command line options. * testsuite/gas/z80/ez80_pref_dis.s: New test. * testsuite/gas/z80/ez80_pref_dis.d: New test driver. * testsuite/gas/z80/z80.exp: Run the new test. * testsuite/gas/z80/fp_math48.d: Use correct command line option. * testsuite/gas/z80/fp_zeda32.d: Likewise. * testsuite/gas/z80/strings.d: Update expected output. opcodes * z80-dis.c (suffix): Use .db instruction to generate double prefix.
2020-01-14 21:13:57 +08:00
2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25377
* config/tc-z80.c: Add support for half precision, single
precision and double precision floating point values.
* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
* doc/as.texi: Add new z80 command line options.
* doc/c-z80.texi: Document new z80 command line options.
* testsuite/gas/z80/ez80_pref_dis.s: New test.
* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
* testsuite/gas/z80/z80.exp: Run the new test.
* testsuite/gas/z80/fp_math48.d: Use correct command line option.
* testsuite/gas/z80/fp_zeda32.d: Likewise.
* testsuite/gas/z80/strings.d: Update expected output.
[gas][aarch64] Turn on SVE when using f32mm or f64mm extensions There are no instructions under these matrix multiply extensions that can be used without having SVE enabled. Since these extensions require SVE, we make that explicit in the options table. Tested on aarch64-none-elf without regressions. gas/ChangeLog: 2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature dependency.
2020-01-13 23:31:39 +08:00
2020-01-13 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature
dependency.
[ARC][committed] Code cleanup and improvements. Code clean up and improvements when changing the cpu from command line. Also, remove unused/old emulations. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change the CPU. * config/tc-arc.h: Add header if/defs. * testsuite/gas/arc/pseudos.d: Improve matching pattern. ls/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * Makefile.am: Remove earcelf_prof.c and earclinux_prof.c emulations. * Makefile.in: Regenerate. * configure.tgt: Likewise. * emulparams/arcelf_prof.sh: Remove file. * emulparams/arclinux_prof.sh: Likewise. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (C_NE): Make it required.
2020-01-13 17:16:47 +08:00
2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
the CPU.
* config/tc-arc.h: Add header if/defs.
* testsuite/gas/arc/pseudos.d: Improve matching pattern.
ubsan: wasm32: signed integer overflow The signed integer overflow occurred when adding one to target_count for (i = 0; i < target_count + 1; i++) but that's the least of the worries here. target_count was long and i int, leading to the possibility of a loop that never ended. So to avoid this type of vulnerability, this patch uses what I believe to be the proper types for arguments of various wasm32 opcodes, rather than using "long" which may change in size. gas/ * testsuite/gas/wasm32/allinsn.d: Update expected output. opcodes/ * wasm32-dis.c (print_insn_wasm32): Localise variables. Store result of wasm_read_leb128 in a uint64_t and check that bits are not lost when copying to other locals. Use uint32_t for most locals. Use PRId64 when printing int64_t.
2020-01-13 11:57:19 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* testsuite/gas/wasm32/allinsn.d: Update expected output.
tic4x: sign extension using shifts Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-12 17:46:22 +08:00
2020-01-13 Alan Modra <amodra@gmail.com>
* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
insertion.
HPUX gas testsuite fixes * testsuite/gas/elf/pr14891.s: Don't start directives in first column. * testsuite/gas/elf/pr21661.d: Don't run on hpux.
2020-01-10 14:59:59 +08:00
2020-01-10 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/pr14891.s: Don't start directives in first column.
* testsuite/gas/elf/pr21661.d: Don't run on hpux.
Fix compile time warnings about comparisons always being false. PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
2020-01-09 19:47:44 +08:00
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25224
* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
opcode byte values.
(emit_ld_r_r): Likewise.
(emit_ld_rr_m): Likewise.
(emit_ld_rr_nn): Likewise.
x86: refine when to trigger optimizations Checking just the base opcode without also checking this isn't a VEX encoding, and without there being other insn properties avoiding a match once respective VEX/XOP/EXEX-encoded insns would appear, is at least dangerous. Add respective checks. At the same time there's no real need to check the extension opcode to be None for the 0xA8 form - there's nothing it can be confused with, and non-VEX-and-alike forms also can't appear.
2020-01-09 18:40:04 +08:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Add
is_any_vex_encoding() invocations. Drop respective
i.tm.extension_opcode == None checks.
x86-64: assert sane internal state for REX conversions For the comments about "hi" registers to be really applicable, RegRex may not be set on the respective registers. Assert this is the case.
2020-01-09 18:39:33 +08:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Check RegRex is clear during
REX transformations. Correct comment indentation.
x86: consistently convert to byte registers for TEST w/ imm optimization Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing testq to testb") didn't go quite far enough: In order to avoid confusing other code registers would better be converted to byte ones uniformly.
2020-01-09 18:38:59 +08:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Generalize register
transformation for TEST optimization.
x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-09 18:38:01 +08:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-sysenter-amd.s,
testsuite/gas/i386/x86-64-sysenter-amd.d,
testsuite/gas/i386/x86-64-sysenter-amd.l,
testsuite/gas/i386/x86-64-sysenter-intel.d,
testsuite/gas/i386/x86-64-sysenter-mixed.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
Document the fact that the assembler's alignment pseudo-ops can be issued without any argumemtns. PR 25284 * doc/as.texi (Align): Document the fact that all arguments can be omitted. (Balign): Likewise. (P2align): Likewise.
2020-01-09 01:00:54 +08:00
2020-01-08 Nick Clifton <nickc@redhat.com>
PR 25284
* doc/as.texi (Align): Document the fact that all arguments can be
omitted.
(Balign): Likewise.
(P2align): Likewise.
Make the assembler generate an error if there is an attempt to define a section with the same name as an already defined symbol. PR 14891 * config/obj-elf.c (obj_elf_section): Fail if the section name is already defined as a different symbol type. * testsuite/gas/elf/pr14891.s: New test source file. * testsuite/gas/elf/pr14891.d: New test driver. * testsuite/gas/elf/pr14891.s: New test expected error output. * testsuite/gas/elf/elf.exp: Run the new test.
2020-01-09 00:30:20 +08:00
2020-01-08 Nick Clifton <nickc@redhat.com>
PR 14891
* config/obj-elf.c (obj_elf_section): Fail if the section name is
already defined as a different symbol type.
* testsuite/gas/elf/pr14891.s: New test source file.
* testsuite/gas/elf/pr14891.d: New test driver.
* testsuite/gas/elf/pr14891.s: New test expected error output.
* testsuite/gas/elf/elf.exp: Run the new test.
ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]' The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
2020-01-08 09:12:36 +08:00
2020-01-08 Alan Modra <amodra@gmail.com>
* config/tc-z8k.c (md_begin): Make idx unsigned.
(get_specific): Likewise for this_index.
[ARC] Improve parsing instruction operands. We use gas' expression function to parse the operands of an instruction in a generic way. There are situations when we have labels and registers having the same name as well as the substraction sign doesn't always stands for the arithmetical operation but for the register range (e.g. enter instruction). This patch improves parsing symbols found in a instruction operand, cleans up code and avoids using default or undefined variables. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_reloc_symbol): New function. (tokenize_arguments): Clean up, use parse_reloc_symbol function. (md_operand): Set X_md to absent. (arc_parse_name): Check for X_md.
2020-01-07 21:29:16 +08:00
2020-01-07 Claudiu Zissulescu <claziss@synopsys.com>
* onfig/tc-arc.c (parse_reloc_symbol): New function.
(tokenize_arguments): Clean up, use parse_reloc_symbol function.
(md_operand): Set X_md to absent.
(arc_parse_name): Check for X_md.
Allow individual targets to decide if string escapes should be allowed. Disable for PPC and Z80. PR 25311 * as.h (TC_STRING_ESCAPES): Provide a default definition. * app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of NO_STRING_ESCAPES. * read.c (next_char_of_string): Likewise. * config/tc-ppc.h (TC_STRING_ESCAPES): Define. * config/tc-z80.h (TC_STRING_ESCAPES): Define.
2020-01-04 00:23:19 +08:00
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25311
* as.h (TC_STRING_ESCAPES): Provide a default definition.
* app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of
NO_STRING_ESCAPES.
* read.c (next_char_of_string): Likewise.
* config/tc-ppc.h (TC_STRING_ESCAPES): Define.
* config/tc-z80.h (TC_STRING_ESCAPES): Define.
Updated Swedish translation for the GAS subdirectory.
2020-01-03 20:59:54 +08:00
2020-01-03 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 17:16:44 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}.
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 17:14:16 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for
by-element usdot. Add 64-bit form tests for by-element sudot.
* testsuite/gas/aarch64/i8mm.d: Adjust expectations.
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 17:13:31 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 17:12:49 +08:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.d,
testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 22:10:40 +08:00
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add
support for assembler code generated by SDCC. Add new relocation
types. Add z80-elf target support.
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
labels. Local labels starts from ".L".
* NEWS: Mention the new support.
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/all/cond.l: Likewise.
* testsuite/gas/all/cond.s: Likewise.
* testsuite/gas/all/fwdexp.d: Likewise.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/elf/section2.e-mips: Likewise.
* testsuite/gas/elf/section2.l: Likewise.
* testsuite/gas/elf/section2.s: Likewise.
* testsuite/gas/macros/app1.d: Likewise.
* testsuite/gas/macros/app1.s: Likewise.
* testsuite/gas/macros/app2.d: Likewise.
* testsuite/gas/macros/app2.s: Likewise.
* testsuite/gas/macros/app3.d: Likewise.
* testsuite/gas/macros/app3.s: Likewise.
* testsuite/gas/macros/app4.d: Likewise.
* testsuite/gas/macros/app4.s: Likewise.
* testsuite/gas/macros/app4b.s: Likewise.
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
* testsuite/gas/z80/z80.exp: Add new tests
* testsuite/gas/z80/dollar.d: New file.
* testsuite/gas/z80/dollar.s: New file.
* testsuite/gas/z80/ez80_adl_all.d: New file.
* testsuite/gas/z80/ez80_adl_all.s: New file.
* testsuite/gas/z80/ez80_adl_suf.d: New file.
* testsuite/gas/z80/ez80_isuf.s: New file.
* testsuite/gas/z80/ez80_z80_all.d: New file.
* testsuite/gas/z80/ez80_z80_all.s: New file.
* testsuite/gas/z80/ez80_z80_suf.d: New file.
* testsuite/gas/z80/r800_extra.d: New file.
* testsuite/gas/z80/r800_extra.s: New file.
* testsuite/gas/z80/r800_ii8.d: New file.
* testsuite/gas/z80/r800_z80_doc.d: New file.
* testsuite/gas/z80/z180.d: New file.
* testsuite/gas/z80/z180.s: New file.
* testsuite/gas/z80/z180_z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.s: New file.
* testsuite/gas/z80/z80_ii8.d: New file.
* testsuite/gas/z80/z80_ii8.s: New file.
* testsuite/gas/z80/z80_in_f_c.d: New file.
* testsuite/gas/z80/z80_in_f_c.s: New file.
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
* testsuite/gas/z80/z80_out_c_0.d: New file.
* testsuite/gas/z80/z80_out_c_0.s: New file.
* testsuite/gas/z80/z80_reloc.d: New file.
* testsuite/gas/z80/z80_reloc.s: New file.
* testsuite/gas/z80/z80_sli.d: New file.
* testsuite/gas/z80/z80_sli.s: New file.
[ARM][gas] fix build breakage with gcc-10 by using correct enum type Fixes ../../gas/config/tc-arm.c: In function 'parse_reg_list': ../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion] 1946 | reg = arm_reg_parse (&str, REGLIST_RN); | ^~~~~~~~~~ gas/ChangeLog: * config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of REGLIST_RN.
2019-10-21 23:59:11 +08:00
2020-01-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of
REGLIST_RN.
Re: Update year range in copyright notice of binutils files Add the ChangeLog entry.
2020-01-01 16:22:19 +08:00
2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2020-01-01 15:37:11 +08:00
For older changes see ChangeLog-2019
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2020-01-01 15:37:11 +08:00
Copyright (C) 2020 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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