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99 lines
1.5 KiB
ArmAsm
99 lines
1.5 KiB
ArmAsm
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//Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp
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// Spec Reference: dagmodim L=0, I incremented & decremented (by M)
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS 0;
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imm32 i0, 0x10001000;
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imm32 i1, 0x02001100;
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imm32 i2, 0x00301010;
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imm32 i3, 0x00041001;
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imm32 m0, 0x00000005;
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imm32 m1, 0x00000006;
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imm32 m2, 0x00000007;
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imm32 m3, 0x00000008;
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I0 += M0;
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I1 += M1;
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I2 += M2;
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I3 += M3;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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I0 += M1;
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I1 += M2;
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I2 += M3;
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I3 += M0;
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R4 = I0;
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R5 = I1;
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R6 = I2;
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R7 = I3;
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CHECKREG r0, 0x10001005;
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CHECKREG r1, 0x02001106;
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CHECKREG r2, 0x00301017;
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CHECKREG r3, 0x00041009;
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CHECKREG r4, 0x1000100B;
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CHECKREG r5, 0x0200110D;
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CHECKREG r6, 0x0030101F;
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CHECKREG r7, 0x0004100E;
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I0 -= M2;
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I1 -= M3;
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I2 -= M0;
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I3 -= M1;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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I0 -= M3;
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I1 -= M2;
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I2 -= M1;
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I3 -= M0;
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R4 = I0;
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R5 = I1;
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R6 = I2;
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R7 = I3;
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CHECKREG r0, 0x10001004;
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CHECKREG r1, 0x02001105;
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CHECKREG r2, 0x0030101A;
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CHECKREG r3, 0x00041008;
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CHECKREG r4, 0x10000FFC;
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CHECKREG r5, 0x020010FE;
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CHECKREG r6, 0x00301014;
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CHECKREG r7, 0x00041003;
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I0 += M3 (BREV);
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I1 += M0 (BREV);
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I2 += M1 (BREV);
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I3 += M2 (BREV);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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I0 += M2 (BREV);
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I1 += M3 (BREV);
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I2 += M0 (BREV);
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I3 += M1 (BREV);
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R4 = I0;
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R5 = I1;
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R6 = I2;
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R7 = I3;
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CHECKREG r0, 0x10000FF2;
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CHECKREG r1, 0x020010F8;
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CHECKREG r2, 0x00301011;
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CHECKREG r3, 0x00041005;
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CHECKREG r4, 0x10000FF4;
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CHECKREG r5, 0x020010F4;
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CHECKREG r6, 0x00301014;
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CHECKREG r7, 0x00041000;
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pass
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