2018-08-10 04:35:24 +08:00
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/* Native-dependent code for GNU/Linux RISC-V.
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2022-01-01 22:56:03 +08:00
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Copyright (C) 2018-2022 Free Software Foundation, Inc.
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2018-08-10 04:35:24 +08:00
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "regcache.h"
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#include "gregset.h"
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#include "linux-nat.h"
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#include "riscv-tdep.h"
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2018-11-29 06:42:27 +08:00
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#include "inferior.h"
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2018-08-10 04:35:24 +08:00
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2018-08-30 01:52:42 +08:00
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#include "elf/common.h"
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2020-02-06 01:21:12 +08:00
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#include "nat/riscv-linux-tdesc.h"
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2018-08-10 04:35:24 +08:00
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#include <sys/ptrace.h>
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2020-02-03 20:07:02 +08:00
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/* Work around glibc header breakage causing ELF_NFPREG not to be usable. */
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#ifndef NFPREG
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# define NFPREG 33
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#endif
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2018-08-10 04:35:24 +08:00
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/* RISC-V Linux native additions to the default linux support. */
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class riscv_linux_nat_target final : public linux_nat_target
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{
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public:
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/* Add our register access methods. */
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void fetch_registers (struct regcache *regcache, int regnum) override;
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void store_registers (struct regcache *regcache, int regnum) override;
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2018-11-29 06:42:27 +08:00
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/* Read suitable target description. */
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const struct target_desc *read_description () override;
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2018-08-10 04:35:24 +08:00
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};
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static riscv_linux_nat_target the_riscv_linux_nat_target;
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/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
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from regset GREGS into REGCACHE. */
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static void
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supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs,
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int regnum)
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{
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int i;
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const elf_greg_t *regp = *gregs;
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if (regnum == -1)
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{
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/* We only support the integer registers and PC here. */
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for (i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++)
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regcache->raw_supply (i, regp + i);
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/* GDB stores PC in reg 32. Linux kernel stores it in reg 0. */
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2022-08-09 19:10:03 +08:00
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regcache->raw_supply (RISCV_PC_REGNUM, regp + 0);
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2018-08-10 04:35:24 +08:00
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/* Fill the inaccessible zero register with zero. */
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2022-08-09 19:10:03 +08:00
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regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
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2018-08-10 04:35:24 +08:00
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}
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else if (regnum == RISCV_ZERO_REGNUM)
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2022-08-09 19:10:03 +08:00
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regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
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2018-08-10 04:35:24 +08:00
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else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM)
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regcache->raw_supply (regnum, regp + regnum);
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else if (regnum == RISCV_PC_REGNUM)
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2022-08-09 19:10:03 +08:00
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regcache->raw_supply (RISCV_PC_REGNUM, regp + 0);
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2018-08-10 04:35:24 +08:00
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}
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/* Copy all general purpose registers from regset GREGS into REGCACHE. */
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void
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supply_gregset (struct regcache *regcache, const prgregset_t *gregs)
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{
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supply_gregset_regnum (regcache, gregs, -1);
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}
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/* Copy floating point register REGNUM (or all fp regs if REGNUM == -1)
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from regset FPREGS into REGCACHE. */
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static void
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supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs,
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int regnum)
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{
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2020-02-03 20:07:02 +08:00
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int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM);
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union
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{
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const prfpregset_t *fpregs;
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const gdb_byte *buf;
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}
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fpbuf = { .fpregs = fpregs };
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2018-08-10 04:35:24 +08:00
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int i;
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if (regnum == -1)
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{
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/* We only support the FP registers and FCSR here. */
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2020-02-03 20:07:02 +08:00
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for (i = RISCV_FIRST_FP_REGNUM;
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i <= RISCV_LAST_FP_REGNUM;
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i++, fpbuf.buf += flen)
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regcache->raw_supply (i, fpbuf.buf);
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2018-08-10 04:35:24 +08:00
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2020-02-03 20:07:02 +08:00
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regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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2018-08-10 04:35:24 +08:00
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}
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else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
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2020-02-03 20:07:02 +08:00
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{
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fpbuf.buf += flen * (regnum - RISCV_FIRST_FP_REGNUM);
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regcache->raw_supply (regnum, fpbuf.buf);
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}
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2018-08-10 04:35:24 +08:00
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else if (regnum == RISCV_CSR_FCSR_REGNUM)
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2020-02-03 20:07:02 +08:00
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{
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fpbuf.buf += flen * (RISCV_LAST_FP_REGNUM - RISCV_FIRST_FP_REGNUM + 1);
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regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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}
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2018-08-10 04:35:24 +08:00
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}
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/* Copy all floating point registers from regset FPREGS into REGCACHE. */
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void
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supply_fpregset (struct regcache *regcache, const prfpregset_t *fpregs)
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{
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supply_fpregset_regnum (regcache, fpregs, -1);
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}
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/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
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from REGCACHE into regset GREGS. */
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void
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fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)
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{
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elf_greg_t *regp = *gregs;
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if (regnum == -1)
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{
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/* We only support the integer registers and PC here. */
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for (int i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++)
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regcache->raw_collect (i, regp + i);
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2022-08-09 19:10:03 +08:00
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regcache->raw_collect (RISCV_PC_REGNUM, regp + 0);
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2018-08-10 04:35:24 +08:00
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}
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else if (regnum == RISCV_ZERO_REGNUM)
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/* Nothing to do here. */
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;
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else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM)
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regcache->raw_collect (regnum, regp + regnum);
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else if (regnum == RISCV_PC_REGNUM)
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2022-08-09 19:10:03 +08:00
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regcache->raw_collect (RISCV_PC_REGNUM, regp + 0);
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2018-08-10 04:35:24 +08:00
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}
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/* Copy floating point register REGNUM (or all fp regs if REGNUM == -1)
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from REGCACHE into regset FPREGS. */
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void
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fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs,
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int regnum)
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{
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2020-02-03 20:07:02 +08:00
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int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM);
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union
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{
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prfpregset_t *fpregs;
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gdb_byte *buf;
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}
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fpbuf = { .fpregs = fpregs };
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int i;
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2018-08-10 04:35:24 +08:00
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if (regnum == -1)
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{
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/* We only support the FP registers and FCSR here. */
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2020-02-03 20:07:02 +08:00
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for (i = RISCV_FIRST_FP_REGNUM;
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i <= RISCV_LAST_FP_REGNUM;
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i++, fpbuf.buf += flen)
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regcache->raw_collect (i, fpbuf.buf);
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2018-08-10 04:35:24 +08:00
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2020-02-03 20:07:02 +08:00
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regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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2018-08-10 04:35:24 +08:00
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}
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else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
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2020-02-03 20:07:02 +08:00
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{
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fpbuf.buf += flen * (regnum - RISCV_FIRST_FP_REGNUM);
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regcache->raw_collect (regnum, fpbuf.buf);
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}
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2018-08-10 04:35:24 +08:00
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else if (regnum == RISCV_CSR_FCSR_REGNUM)
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2020-02-03 20:07:02 +08:00
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{
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fpbuf.buf += flen * (RISCV_LAST_FP_REGNUM - RISCV_FIRST_FP_REGNUM + 1);
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regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
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}
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2018-08-10 04:35:24 +08:00
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}
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2018-11-29 06:42:27 +08:00
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/* Return a target description for the current target. */
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const struct target_desc *
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riscv_linux_nat_target::read_description ()
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{
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gdb/riscv: Update API for looking up target descriptions
In preparation for adding the RISC-V gdbserver, this commit
restructures the API for looking up target descriptions.
The current API is riscv_create_target_description, which creates a
target description from a riscv_gdbarch_features, but also caches the
created target descriptions so that for a given features object we
always get back the same target description object. This is important
for GDB due to the way gdbarch objects are reused.
As the same target description is always returned to GDB, and can be
returned multiple times, it is returned as a const, however, the
current cache actually stores a non-const target description. This is
improved in this patch so that the cache holds a const target
description.
For gdbsever, this caching of the target descriptions is not needed,
the gdbserver looks up one target description to describe the target
it is actually running on and that is it. Further the gdbserver
actually needs to modify the target description that is looked up, so
for the gdbsever, returning a const target description is not
acceptable.
This commit aims to address this by creating two parallel target
description APIs, on is the old riscv_create_target_description,
however, this no longer performs any caching, and just creates a new
target description, and returns it as non-const.
The second API is riscv_lookup_target_description, this one performs
the caching, and calls riscv_create_target_description to create a
target description when needed.
In order to make sure the correct API is used in the correct place I
have guarded the code using the GDBSERVER define. For GDB the
riscv_create_target_description is static, and not generally usable
throughout GDB, only the lookup API is global. In gdbserver, the
lookup functions, and the cache are not defined or created at all,
only the riscv_create_target_description API is available.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define
if GDBSERVER is not defined.
(riscv_tdesc_cache): Likewise, also store const target_desc.
(STATIC_IN_GDB): Define.
(riscv_create_target_description): Update declaration with
STATIC_IN_GDB.
(riscv_lookup_target_description): New function, only define if
GDBSERVER is not defined.
* arch/riscv.h (riscv_create_target_description): Declare only
when GDBSERVER is defined.
(riscv_lookup_target_description): New declaration when GDBSERVER
is not defined.
* nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to...
(riscv_linux_read_features): ...this, and return
riscv_gdbarch_features instead of target_desc.
* nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'.
(riscv_linux_read_description): Rename to...
(riscv_linux_read_features): ...this.
* riscv-linux-nat.c (riscv_linux_nat_target::read_description):
Update to use riscv_gdbarch_features and
riscv_lookup_target_description.
* riscv-tdep.c (riscv_find_default_target_description): Use
riscv_lookup_target_description instead of
riscv_create_target_description.
2020-02-19 09:24:37 +08:00
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const struct riscv_gdbarch_features features
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[gdb/tdep] Use pid to choose process 64/32-bitness
In a linux kernel mailing list discussion, it was mentioned that "gdb has
this odd thing where it takes the 64-bit vs 32-bit data for the whole process
from one thread, and picks the worst possible thread to do it (ie explicitly
not even the main thread, ...)" [1].
The picking of the thread is done here in
x86_linux_nat_target::read_description:
...
/* GNU/Linux LWP ID's are process ID's. */
tid = inferior_ptid.lwp ();
if (tid == 0)
tid = inferior_ptid.pid (); /* Not a threaded program. */
...
To understand what this code does, let's investigate a scenario in which
inferior_ptid.lwp () != inferior_ptid.pid ().
Say we start exec jit-attach-pie, identified with pid x. The main thread
starts another thread that sleeps, and then the main thread waits for the
sleeping thread. So we have two threads, identified with LWP IDs x and x+1:
...
PID LWP CMD
x x ./jit-attach-pie
x x+1 ./jit-attach-pie
...
[ The thread with LWP x is known as the thread group leader. ]
When attaching to this exec using the pid, gdb does a stop_all_threads which
iterates over all the threads, first LWP x, and then LWP x+1.
So the state we arrive with at x86_linux_nat_target::read_description is:
...
(gdb) p inferior_ptid
$1 = {m_pid = x, m_lwp = x+1, m_tid = 0}
...
and consequently we probe 64/32-bitness from thread LWP x+1.
[ Note that this is different from when gdb doesn't attach but instead
launches the exec itself, in which case there's just one thread to begin with,
and consequently the probed thread is LWP x. ]
According to aforementioned remark, a better choice would have been the main
thread, that is, LWP x.
This patch implement that choice, by simply doing:
...
tid = inferior_ptid.pid ();
...
The fact that gdb makes a per-process permanent choice for 64/32-bitness is a
problem in itself: each thread can be in either 64 or 32 bit mode, and change
forth and back. That is a problem that this patch doesn't fix.
Now finally: why does this matter in the context of the linux kernel
discussion? The discussion was related to a patch that exposed io_uring
threads to user-space. This made it possible that one of those threads would
be picked out to select 64/32-bitness. Given that such threads are atypical
user-space threads in the sense that they don't return to user-space and don't
have a userspace register state, reading their registers returns garbage, and
so it could f.i. occur that in a 64-bit process with all normal user-space
threads in 64-bit mode, the probing would return 32-bit.
It may be that this is worked-around on the kernel side by providing userspace
register state in those threads such that current gdb is happy. Nevertheless,
it seems prudent to fix this on the gdb size as well.
Tested on x86_64-linux.
[1] https://lore.kernel.org/io-uring/CAHk-=wh0KoEZXPYMGkfkeVEerSCEF1AiCZSvz9TRrx=Kj74D+Q@mail.gmail.com/
gdb/ChangeLog:
2021-05-23 Tom de Vries <tdevries@suse.de>
PR tdep/27822
* target.h (struct target_ops): Mention target_thread_architecture in
read_description comment.
* x86-linux-nat.c (x86_linux_nat_target::read_description): Use
pid to determine if process is 64-bit or 32-bit.
* aarch64-linux-nat.c (aarch64_linux_nat_target::read_description):
Same.
* ppc-linux-nat.c (ppc_linux_nat_target::read_description): Same.
* riscv-linux-nat.c (riscv_linux_nat_target::read_description): Same.
* s390-linux-nat.c (s390_linux_nat_target::read_description): Same.
* arm-linux-nat.c (arm_linux_nat_target::read_description): Same.
Likewise, use pid to determine if kernel supports reading VFP
registers.
2021-05-23 16:08:45 +08:00
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= riscv_linux_read_features (inferior_ptid.pid ());
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gdb/riscv: Update API for looking up target descriptions
In preparation for adding the RISC-V gdbserver, this commit
restructures the API for looking up target descriptions.
The current API is riscv_create_target_description, which creates a
target description from a riscv_gdbarch_features, but also caches the
created target descriptions so that for a given features object we
always get back the same target description object. This is important
for GDB due to the way gdbarch objects are reused.
As the same target description is always returned to GDB, and can be
returned multiple times, it is returned as a const, however, the
current cache actually stores a non-const target description. This is
improved in this patch so that the cache holds a const target
description.
For gdbsever, this caching of the target descriptions is not needed,
the gdbserver looks up one target description to describe the target
it is actually running on and that is it. Further the gdbserver
actually needs to modify the target description that is looked up, so
for the gdbsever, returning a const target description is not
acceptable.
This commit aims to address this by creating two parallel target
description APIs, on is the old riscv_create_target_description,
however, this no longer performs any caching, and just creates a new
target description, and returns it as non-const.
The second API is riscv_lookup_target_description, this one performs
the caching, and calls riscv_create_target_description to create a
target description when needed.
In order to make sure the correct API is used in the correct place I
have guarded the code using the GDBSERVER define. For GDB the
riscv_create_target_description is static, and not generally usable
throughout GDB, only the lookup API is global. In gdbserver, the
lookup functions, and the cache are not defined or created at all,
only the riscv_create_target_description API is available.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define
if GDBSERVER is not defined.
(riscv_tdesc_cache): Likewise, also store const target_desc.
(STATIC_IN_GDB): Define.
(riscv_create_target_description): Update declaration with
STATIC_IN_GDB.
(riscv_lookup_target_description): New function, only define if
GDBSERVER is not defined.
* arch/riscv.h (riscv_create_target_description): Declare only
when GDBSERVER is defined.
(riscv_lookup_target_description): New declaration when GDBSERVER
is not defined.
* nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to...
(riscv_linux_read_features): ...this, and return
riscv_gdbarch_features instead of target_desc.
* nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'.
(riscv_linux_read_description): Rename to...
(riscv_linux_read_features): ...this.
* riscv-linux-nat.c (riscv_linux_nat_target::read_description):
Update to use riscv_gdbarch_features and
riscv_lookup_target_description.
* riscv-tdep.c (riscv_find_default_target_description): Use
riscv_lookup_target_description instead of
riscv_create_target_description.
2020-02-19 09:24:37 +08:00
|
|
|
return riscv_lookup_target_description (features);
|
2018-11-29 06:42:27 +08:00
|
|
|
}
|
|
|
|
|
2018-08-10 04:35:24 +08:00
|
|
|
/* Fetch REGNUM (or all registers if REGNUM == -1) from the target
|
|
|
|
into REGCACHE using PTRACE_GETREGSET. */
|
|
|
|
|
|
|
|
void
|
|
|
|
riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
|
|
|
|
{
|
|
|
|
int tid;
|
|
|
|
|
|
|
|
tid = get_ptrace_pid (regcache->ptid());
|
|
|
|
|
|
|
|
if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM)
|
|
|
|
|| (regnum == -1))
|
|
|
|
{
|
|
|
|
struct iovec iov;
|
|
|
|
elf_gregset_t regs;
|
|
|
|
|
|
|
|
iov.iov_base = ®s;
|
|
|
|
iov.iov_len = sizeof (regs);
|
|
|
|
|
|
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
|
|
|
|
(PTRACE_TYPE_ARG3) &iov) == -1)
|
|
|
|
perror_with_name (_("Couldn't get registers"));
|
|
|
|
else
|
|
|
|
supply_gregset_regnum (regcache, ®s, regnum);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((regnum >= RISCV_FIRST_FP_REGNUM
|
|
|
|
&& regnum <= RISCV_LAST_FP_REGNUM)
|
|
|
|
|| (regnum == RISCV_CSR_FCSR_REGNUM)
|
|
|
|
|| (regnum == -1))
|
|
|
|
{
|
|
|
|
struct iovec iov;
|
|
|
|
elf_fpregset_t regs;
|
|
|
|
|
|
|
|
iov.iov_base = ®s;
|
2020-02-03 20:07:02 +08:00
|
|
|
iov.iov_len = ELF_NFPREG * register_size (regcache->arch (),
|
|
|
|
RISCV_FIRST_FP_REGNUM);
|
|
|
|
gdb_assert (iov.iov_len <= sizeof (regs));
|
2018-08-10 04:35:24 +08:00
|
|
|
|
2018-08-30 01:52:42 +08:00
|
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
|
2018-08-10 04:35:24 +08:00
|
|
|
(PTRACE_TYPE_ARG3) &iov) == -1)
|
|
|
|
perror_with_name (_("Couldn't get registers"));
|
|
|
|
else
|
|
|
|
supply_fpregset_regnum (regcache, ®s, regnum);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((regnum == RISCV_CSR_MISA_REGNUM)
|
|
|
|
|| (regnum == -1))
|
2018-10-28 18:43:26 +08:00
|
|
|
{
|
|
|
|
/* TODO: Need to add a ptrace call for this. */
|
|
|
|
regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM);
|
|
|
|
}
|
2018-08-10 04:35:24 +08:00
|
|
|
|
|
|
|
/* Access to other CSRs has potential security issues, don't support them for
|
|
|
|
now. */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Store REGNUM (or all registers if REGNUM == -1) to the target
|
|
|
|
from REGCACHE using PTRACE_SETREGSET. */
|
|
|
|
|
|
|
|
void
|
|
|
|
riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
|
|
|
|
{
|
|
|
|
int tid;
|
|
|
|
|
|
|
|
tid = get_ptrace_pid (regcache->ptid ());
|
|
|
|
|
|
|
|
if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM)
|
|
|
|
|| (regnum == -1))
|
|
|
|
{
|
|
|
|
struct iovec iov;
|
|
|
|
elf_gregset_t regs;
|
|
|
|
|
|
|
|
iov.iov_base = ®s;
|
|
|
|
iov.iov_len = sizeof (regs);
|
|
|
|
|
|
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
|
|
|
|
(PTRACE_TYPE_ARG3) &iov) == -1)
|
|
|
|
perror_with_name (_("Couldn't get registers"));
|
|
|
|
else
|
|
|
|
{
|
|
|
|
fill_gregset (regcache, ®s, regnum);
|
|
|
|
|
|
|
|
if (ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS,
|
|
|
|
(PTRACE_TYPE_ARG3) &iov) == -1)
|
|
|
|
perror_with_name (_("Couldn't set registers"));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((regnum >= RISCV_FIRST_FP_REGNUM
|
|
|
|
&& regnum <= RISCV_LAST_FP_REGNUM)
|
|
|
|
|| (regnum == RISCV_CSR_FCSR_REGNUM)
|
|
|
|
|| (regnum == -1))
|
|
|
|
{
|
|
|
|
struct iovec iov;
|
|
|
|
elf_fpregset_t regs;
|
|
|
|
|
|
|
|
iov.iov_base = ®s;
|
2020-02-03 20:07:02 +08:00
|
|
|
iov.iov_len = ELF_NFPREG * register_size (regcache->arch (),
|
|
|
|
RISCV_FIRST_FP_REGNUM);
|
|
|
|
gdb_assert (iov.iov_len <= sizeof (regs));
|
2018-08-10 04:35:24 +08:00
|
|
|
|
2018-08-30 01:52:42 +08:00
|
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
|
2018-08-10 04:35:24 +08:00
|
|
|
(PTRACE_TYPE_ARG3) &iov) == -1)
|
|
|
|
perror_with_name (_("Couldn't get registers"));
|
|
|
|
else
|
|
|
|
{
|
|
|
|
fill_fpregset (regcache, ®s, regnum);
|
|
|
|
|
2018-08-30 01:52:42 +08:00
|
|
|
if (ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET,
|
2018-08-10 04:35:24 +08:00
|
|
|
(PTRACE_TYPE_ARG3) &iov) == -1)
|
|
|
|
perror_with_name (_("Couldn't set registers"));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Access to CSRs has potential security issues, don't support them for
|
|
|
|
now. */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize RISC-V Linux native support. */
|
|
|
|
|
2020-01-14 03:01:38 +08:00
|
|
|
void _initialize_riscv_linux_nat ();
|
2018-08-10 04:35:24 +08:00
|
|
|
void
|
2020-01-14 03:01:38 +08:00
|
|
|
_initialize_riscv_linux_nat ()
|
2018-08-10 04:35:24 +08:00
|
|
|
{
|
|
|
|
/* Register the target. */
|
|
|
|
linux_target = &the_riscv_linux_nat_target;
|
|
|
|
add_inf_child_target (&the_riscv_linux_nat_target);
|
|
|
|
}
|