2020-01-01 15:57:01 +08:00
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@c Copyright (C) 2009-2020 Free Software Foundation, Inc.
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2012-08-13 22:52:54 +08:00
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@c Contributed by ARM Ltd.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c man end
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@ifset GENERIC
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@page
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@node AArch64-Dependent
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@chapter AArch64 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter AArch64 Dependent Features
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@end ifclear
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@cindex AArch64 support
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@menu
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* AArch64 Options:: Options
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2014-03-14 01:10:04 +08:00
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* AArch64 Extensions:: Extensions
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2012-08-13 22:52:54 +08:00
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* AArch64 Syntax:: Syntax
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* AArch64 Floating Point:: Floating Point
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* AArch64 Directives:: AArch64 Machine Directives
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* AArch64 Opcodes:: Opcodes
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* AArch64 Mapping Symbols:: Mapping Symbols
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@end menu
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@node AArch64 Options
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@section Options
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@cindex AArch64 options (none)
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@cindex options for AArch64 (none)
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@c man begin OPTIONS
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@table @gcctabopt
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2018-07-02 18:18:24 +08:00
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@cindex @option{-EB} command-line option, AArch64
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2012-08-13 22:52:54 +08:00
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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2018-07-02 18:18:24 +08:00
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@cindex @option{-EL} command-line option, AArch64
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2012-08-13 22:52:54 +08:00
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor.
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2018-07-02 18:18:24 +08:00
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@cindex @option{-mabi=} command-line option, AArch64
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2013-07-20 00:25:54 +08:00
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@item -mabi=@var{abi}
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Specify which ABI the source code uses. The recognized arguments
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are: @code{ilp32} and @code{lp64}, which decides the generated object
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file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
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2018-07-02 18:18:24 +08:00
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@cindex @option{-mcpu=} command-line option, AArch64
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2014-03-14 01:10:04 +08:00
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@item -mcpu=@var{processor}[+@var{extension}@dots{}]
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This option specifies the target processor. The assembler will issue an error
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message if an attempt is made to assemble an instruction which will not execute
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on the target processor. The following processor names are recognized:
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Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.
gas * NEWS: Mention the Arm and AArch64 new processors.
* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
* doc/c-aarch64.texi: Document new CPUs.
* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
* testsuite/gas/aarch64/nop-asm.s: New test.
bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-21 00:13:29 +08:00
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@code{cortex-a34},
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2015-11-12 20:04:22 +08:00
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@code{cortex-a35},
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2014-03-14 01:10:04 +08:00
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@code{cortex-a53},
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2017-06-21 16:13:25 +08:00
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@code{cortex-a55},
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2014-03-14 01:10:04 +08:00
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@code{cortex-a57},
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Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.
gas * NEWS: Mention the Arm and AArch64 new processors.
* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
* doc/c-aarch64.texi: Document new CPUs.
* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
* testsuite/gas/aarch64/nop-asm.s: New test.
bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-21 00:13:29 +08:00
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@code{cortex-a65},
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@code{cortex-a65ae},
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2015-02-05 03:17:12 +08:00
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@code{cortex-a72},
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2016-06-03 23:59:24 +08:00
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@code{cortex-a73},
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2017-06-21 16:13:25 +08:00
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@code{cortex-a75},
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2018-06-08 22:39:47 +08:00
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@code{cortex-a76},
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Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.
gas * NEWS: Mention the Arm and AArch64 new processors.
* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
* doc/c-aarch64.texi: Document new CPUs.
* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
* testsuite/gas/aarch64/nop-asm.s: New test.
bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-21 00:13:29 +08:00
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@code{cortex-a76ae},
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@code{cortex-a77},
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2019-01-08 23:18:32 +08:00
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@code{ares},
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2015-03-27 04:18:08 +08:00
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@code{exynos-m1},
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2016-10-20 02:59:34 +08:00
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@code{falkor},
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2019-02-22 17:56:50 +08:00
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@code{neoverse-n1},
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2019-02-22 17:57:45 +08:00
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@code{neoverse-e1},
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2015-11-11 01:19:45 +08:00
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@code{qdf24xx},
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2017-11-03 22:03:03 +08:00
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@code{saphira},
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2014-10-21 02:39:49 +08:00
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@code{thunderx},
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2016-06-13 21:17:31 +08:00
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@code{vulcan},
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2014-11-18 19:24:14 +08:00
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@code{xgene1}
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2014-03-14 01:10:04 +08:00
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and
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2014-11-18 19:24:14 +08:00
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@code{xgene2}.
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2014-03-14 01:10:04 +08:00
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The special name @code{all} may be used to allow the assembler to accept
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instructions valid for any supported processor, including all optional
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extensions.
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In addition to the basic instruction set, the assembler can be told to
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accept, or restrict, various extension mnemonics that extend the
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processor. @xref{AArch64 Extensions}.
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If some implementations of a particular processor can have an
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extension, then then those extensions are automatically enabled.
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Consequently, you will not normally have to specify any additional
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extensions.
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2018-07-02 18:18:24 +08:00
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@cindex @option{-march=} command-line option, AArch64
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2014-03-14 01:10:04 +08:00
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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This option specifies the target architecture. The assembler will
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issue an error message if an attempt is made to assemble an
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instruction which will not execute on the target architecture. The
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2015-11-19 17:12:49 +08:00
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following architecture names are recognized: @code{armv8-a},
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2018-09-26 17:38:59 +08:00
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@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
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2019-11-08 00:18:51 +08:00
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@code{armv8.5-a}, and @code{armv8.6-a}.
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2014-03-14 01:10:04 +08:00
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If both @option{-mcpu} and @option{-march} are specified, the
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assembler will use the setting for @option{-mcpu}. If neither are
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specified, the assembler will default to @option{-mcpu=all}.
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The architecture option can be extended with the same instruction set
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extension options as the @option{-mcpu} option. Unlike
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@option{-mcpu}, extensions are not always enabled by default,
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@xref{AArch64 Extensions}.
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2018-07-02 18:18:24 +08:00
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@cindex @code{-mverbose-error} command-line option, AArch64
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2014-03-19 01:41:43 +08:00
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@item -mverbose-error
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This option enables verbose error messages for AArch64 gas. This option
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is enabled by default.
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2018-07-02 18:18:24 +08:00
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@cindex @code{-mno-verbose-error} command-line option, AArch64
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2014-03-19 01:41:43 +08:00
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@item -mno-verbose-error
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This option disables verbose error messages in AArch64 gas.
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2012-08-13 22:52:54 +08:00
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@end table
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@c man end
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2014-03-14 01:10:04 +08:00
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@node AArch64 Extensions
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@section Architecture Extensions
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The table below lists the permitted architecture extensions that are
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supported by the assembler and the conditions under which they are
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automatically enabled.
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Multiple extensions may be specified, separated by a @code{+}.
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Extension mnemonics may also be removed from those the assembler
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accepts. This is done by prepending @code{no} to the option that adds
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the extension. Extensions that are removed must be listed after all
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extensions that have been added.
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Enabling an extension that requires other extensions will
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automatically cause those extensions to be enabled. Similarly,
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disabling an extension that is required by other extensions will
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automatically cause those extensions to be disabled.
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@multitable @columnfractions .12 .17 .17 .54
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@headitem Extension @tab Minimum Architecture @tab Enabled by default
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@tab Description
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[binutils][aarch64] Matrix Multiply extension enablement [8/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the aarch64 backend.
The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
(parse_operands): Add new operand.
* testsuite/gas/aarch64/i8mm.s: New test.
* testsuite/gas/aarch64/i8mm.d: New test.
* testsuite/gas/aarch64/f32mm.s: New test.
* testsuite/gas/aarch64/f32mm.d: New test.
* testsuite/gas/aarch64/f64mm.s: New test.
* testsuite/gas/aarch64/f64mm.d: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
(AARCH64_FEATURE_F32MM): New.
(AARCH64_FEATURE_F64MM): New.
(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
instructions that do not require special handling.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
aarch64_feature_f64mm): New feature sets.
(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
instructions.
(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
macros.
(QL_MMLA64, OP_SVE_SBB): New qualifiers.
(OP_SVE_QQQ): New qualifier.
(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
the movprfx constraint.
(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
(aarch64_opcode_table): Define new instructions smmla,
ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
uzip{1/2}, trn{1/2}.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_ADDR_RI_S4x32.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
Account for new instructions.
* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
S4x32 operand.
* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
Regression tested on arm-none-eabi.
Is it ok for trunk?
Regards,
Mihail
2019-11-08 01:10:01 +08:00
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@item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
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@tab Enable Int8 Matrix Multiply extension.
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@item @code{f32mm} @tab ARMv8.2-A @tab No
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@tab Enable F32 Matrix Multiply extension.
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@item @code{f64mm} @tab ARMv8.2-A @tab No
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@tab Enable F64 Matrix Multiply extension.
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[binutils][aarch64] Bfloat16 enablement [2/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.
This patch introduces the following BFloat16 instructions to the
aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b],
bfcvtn2.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Special case the
S_2H operand qualifier.
* doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions.
* testsuite/gas/aarch64/bfloat16.d: New test.
* testsuite/gas/aarch64/bfloat16.s: New test.
* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
include/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros.
(AARCH64_ARCH_V8_6): Include BFloat16 feature macros.
(enum aarch64_opnd_qualifier): Introduce new operand qualifier
AARCH64_OPND_QLF_S_2H.
(enum aarch64_insn_class): Introduce new class "bfloat16".
(BFLOAT16_SVE_INSNC): New feature set for bfloat16
instructions to support the movprfx constraint.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-dis-2.c (aarch64_opcode_lookup_1,
aarch64_find_next_opcode): Account for new instructions.
* aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
in reglane special case.
* aarch64-opc.c (struct operand_qualifier_data): Add data for
new AARCH64_OPND_QLF_S_2H qualifier.
* aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
(aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve,
aarch64_feature_bfloat16_bfmmla4): New feature sets.
(BFLOAT_SVE, BFLOAT): New feature set macros.
(BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros
to define BFloat16 instructions.
(aarch64_opcode_table): Define new instructions bfdot,
bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
bfcvtn2, bfcvt.
Regression tested on aarch64-elf.
Is it ok for trunk?
Regards,
Mihail
2019-11-08 00:38:59 +08:00
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@item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
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@tab Enable BFloat16 extension.
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2017-02-25 02:27:26 +08:00
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@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
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@tab Enable the complex number SIMD extensions. This implies
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@code{fp16} and @code{simd}.
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2015-12-10 21:58:21 +08:00
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@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
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2014-03-14 01:10:04 +08:00
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@tab Enable CRC instructions.
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@item @code{crypto} @tab ARMv8-A @tab No
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2017-11-17 00:13:01 +08:00
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@tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
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@item @code{aes} @tab ARMv8-A @tab No
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@tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
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@item @code{sha2} @tab ARMv8-A @tab No
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@tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
|
|
|
|
@item @code{sha3} @tab ARMv8.2-A @tab No
|
|
|
|
@tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
|
|
|
|
@item @code{sm4} @tab ARMv8.2-A @tab No
|
|
|
|
@tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
|
2014-03-14 01:10:04 +08:00
|
|
|
@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
|
|
|
|
@tab Enable floating-point extensions.
|
2015-11-27 21:19:50 +08:00
|
|
|
@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
|
|
|
|
@tab Enable ARMv8.2 16-bit floating-point support. This implies
|
|
|
|
@code{fp}.
|
2016-04-07 20:29:50 +08:00
|
|
|
@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
|
|
|
|
@tab Enable Limited Ordering Regions extensions.
|
|
|
|
@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
|
|
|
|
@tab Enable Large System extensions.
|
|
|
|
@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
|
|
|
|
@tab Enable Privileged Access Never support.
|
2015-12-11 17:30:26 +08:00
|
|
|
@item @code{profile} @tab ARMv8.2-A @tab No
|
|
|
|
@tab Enable statistical profiling extensions.
|
2016-04-20 16:31:49 +08:00
|
|
|
@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
|
|
|
|
@tab Enable the Reliability, Availability and Serviceability
|
|
|
|
extension.
|
2017-03-01 22:51:13 +08:00
|
|
|
@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
|
|
|
|
@tab Enable the weak release consistency extension.
|
2016-04-07 20:29:50 +08:00
|
|
|
@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
|
|
|
|
@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
|
|
|
|
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
|
|
|
|
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
|
|
|
@item @code{sve} @tab ARMv8.2-A @tab No
|
|
|
|
@tab Enable the Scalable Vector Extensions. This implies @code{fp16},
|
|
|
|
@code{simd} and @code{compnum}.
|
2017-11-17 00:13:01 +08:00
|
|
|
@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
|
2017-06-28 18:09:01 +08:00
|
|
|
@tab Enable the Dot Product extension. This implies @code{simd}.
|
2017-11-17 00:19:37 +08:00
|
|
|
@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
|
|
|
|
@tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
|
|
|
|
This implies @code{fp16}.
|
2018-09-26 17:47:40 +08:00
|
|
|
@item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
|
|
|
|
@tab Enable the speculation barrier instruction sb.
|
2018-09-26 17:52:51 +08:00
|
|
|
@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
|
|
|
|
@tab Enable the Execution and Data and Prediction instructions.
|
2018-09-26 17:57:16 +08:00
|
|
|
@item @code{rng} @tab ARMv8.5-A @tab No
|
|
|
|
@tab Enable ARMv8.5-A random number instructions.
|
2018-09-26 18:04:32 +08:00
|
|
|
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
|
|
|
|
@tab Enable Speculative Store Bypassing Safe state read and write.
|
2018-11-12 20:45:30 +08:00
|
|
|
@item @code{memtag} @tab ARMv8.5-A @tab No
|
|
|
|
@tab Enable ARMv8.5-A Memory Tagging Extensions.
|
2019-05-02 00:14:01 +08:00
|
|
|
@item @code{tme} @tab ARMv8-A @tab No
|
|
|
|
@tab Enable Transactional Memory Extensions.
|
[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 17:29:12 +08:00
|
|
|
@item @code{sve2} @tab ARMv8-A @tab No
|
|
|
|
@tab Enable the SVE2 Extension.
|
2019-07-19 19:18:02 +08:00
|
|
|
@item @code{sve2-bitperm} @tab ARMv8-A @tab No
|
[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 17:29:12 +08:00
|
|
|
@tab Enable SVE2 BITPERM Extension.
|
|
|
|
@item @code{sve2-sm4} @tab ARMv8-A @tab No
|
|
|
|
@tab Enable SVE2 SM4 Extension.
|
|
|
|
@item @code{sve2-aes} @tab ARMv8-A @tab No
|
[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.
Only the variant specifying .Q -> .D sizes should have that
restriction.
This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).
We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size. This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.
Regtested targeting aarch64-linux.
gas/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
* doc/c-aarch64.texi: Add special note of pmull{t,b}
instructions under the sve2-aes architecture extension.
* testsuite/gas/aarch64/illegal-sve2.s: Add small size
pmull{t,b} instructions.
* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
disassembly.
* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
instructions.
include/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
renamed to sve_size_13.
opcodes/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
(OP_SVE_VVV_Q_D): Add new qualifier.
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
(struct aarch64_opcode): Split pmull{t,b} into those requiring
AES and those not.
2019-07-01 22:17:22 +08:00
|
|
|
@tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the
|
|
|
|
@code{pmullt} and @code{pmullb} instructions.
|
[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 17:29:12 +08:00
|
|
|
@item @code{sve2-sha3} @tab ARMv8-A @tab No
|
|
|
|
@tab Enable SVE2 SHA3 Extension.
|
2014-03-14 01:10:04 +08:00
|
|
|
@end multitable
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@node AArch64 Syntax
|
|
|
|
@section Syntax
|
|
|
|
@menu
|
|
|
|
* AArch64-Chars:: Special Characters
|
|
|
|
* AArch64-Regs:: Register Names
|
|
|
|
* AArch64-Relocations:: Relocations
|
|
|
|
@end menu
|
|
|
|
|
|
|
|
@node AArch64-Chars
|
|
|
|
@subsection Special Characters
|
|
|
|
|
|
|
|
@cindex line comment character, AArch64
|
|
|
|
@cindex AArch64 line comment character
|
|
|
|
The presence of a @samp{//} on a line indicates the start of a comment
|
|
|
|
that extends to the end of the current line. If a @samp{#} appears as
|
|
|
|
the first character of a line, the whole line is treated as a comment.
|
|
|
|
|
|
|
|
@cindex line separator, AArch64
|
|
|
|
@cindex statement separator, AArch64
|
|
|
|
@cindex AArch64 line separator
|
|
|
|
The @samp{;} character can be used instead of a newline to separate
|
|
|
|
statements.
|
|
|
|
|
|
|
|
@cindex immediate character, AArch64
|
|
|
|
@cindex AArch64 immediate character
|
|
|
|
The @samp{#} can be optionally used to indicate immediate operands.
|
|
|
|
|
|
|
|
@node AArch64-Regs
|
|
|
|
@subsection Register Names
|
|
|
|
|
|
|
|
@cindex AArch64 register names
|
|
|
|
@cindex register names, AArch64
|
|
|
|
Please refer to the section @samp{4.4 Register Names} of
|
|
|
|
@samp{ARMv8 Instruction Set Overview}, which is available at
|
|
|
|
@uref{http://infocenter.arm.com}.
|
|
|
|
|
|
|
|
@node AArch64-Relocations
|
|
|
|
@subsection Relocations
|
|
|
|
|
|
|
|
@cindex relocations, AArch64
|
|
|
|
@cindex AArch64 relocations
|
|
|
|
@cindex MOVN, MOVZ and MOVK group relocations, AArch64
|
|
|
|
Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
|
|
|
|
by prefixing the label with @samp{#:abs_g2:} etc.
|
|
|
|
For example to load the 48-bit absolute address of @var{foo} into x0:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
movz x0, #:abs_g2:foo // bits 32-47, overflow check
|
|
|
|
movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
|
|
|
|
movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@cindex ADRP, ADD, LDR/STR group relocations, AArch64
|
|
|
|
Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
|
|
|
|
instructions can be generated by prefixing the label with
|
2014-06-06 14:29:19 +08:00
|
|
|
@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
|
2012-08-13 22:52:54 +08:00
|
|
|
|
2013-01-11 03:51:55 +08:00
|
|
|
For example to use 33-bit (+/-4GB) pc-relative addressing to
|
2012-08-13 22:52:54 +08:00
|
|
|
load the address of @var{foo} into x0:
|
|
|
|
|
|
|
|
@smallexample
|
2014-06-06 14:29:19 +08:00
|
|
|
adrp x0, :pg_hi21:foo
|
2012-08-13 22:52:54 +08:00
|
|
|
add x0, x0, #:lo12:foo
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
Or to load the value of @var{foo} into x0:
|
|
|
|
|
|
|
|
@smallexample
|
2014-06-06 14:29:19 +08:00
|
|
|
adrp x0, :pg_hi21:foo
|
2012-08-13 22:52:54 +08:00
|
|
|
ldr x0, [x0, #:lo12:foo]
|
|
|
|
@end smallexample
|
|
|
|
|
2014-06-06 14:29:19 +08:00
|
|
|
Note that @samp{:pg_hi21:} is optional.
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
@smallexample
|
|
|
|
adrp x0, foo
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
is equivalent to
|
|
|
|
|
|
|
|
@smallexample
|
2014-06-06 14:29:19 +08:00
|
|
|
adrp x0, :pg_hi21:foo
|
2012-08-13 22:52:54 +08:00
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
@node AArch64 Floating Point
|
|
|
|
@section Floating Point
|
|
|
|
|
|
|
|
@cindex floating point, AArch64 (@sc{ieee})
|
|
|
|
@cindex AArch64 floating point (@sc{ieee})
|
|
|
|
The AArch64 architecture uses @sc{ieee} floating-point numbers.
|
|
|
|
|
|
|
|
@node AArch64 Directives
|
|
|
|
@section AArch64 Machine Directives
|
|
|
|
|
|
|
|
@cindex machine directives, AArch64
|
|
|
|
@cindex AArch64 machine directives
|
|
|
|
@table @code
|
|
|
|
|
|
|
|
@c AAAAAAAAAAAAAAAAAAAAAAAAA
|
2015-02-03 22:02:24 +08:00
|
|
|
|
|
|
|
@cindex @code{.arch} directive, AArch64
|
|
|
|
@item .arch @var{name}
|
|
|
|
Select the target architecture. Valid values for @var{name} are the same as
|
2018-07-02 18:18:24 +08:00
|
|
|
for the @option{-march} command-line option.
|
2015-02-03 22:02:24 +08:00
|
|
|
|
|
|
|
Specifying @code{.arch} clears any previously selected architecture
|
|
|
|
extensions.
|
|
|
|
|
|
|
|
@cindex @code{.arch_extension} directive, AArch64
|
|
|
|
@item .arch_extension @var{name}
|
|
|
|
Add or remove an architecture extension to the target architecture. Valid
|
|
|
|
values for @var{name} are the same as those accepted as architectural
|
2018-07-02 18:18:24 +08:00
|
|
|
extensions by the @option{-mcpu} command-line option.
|
2015-02-03 22:02:24 +08:00
|
|
|
|
|
|
|
@code{.arch_extension} may be used multiple times to add or remove extensions
|
|
|
|
incrementally to the architecture being compiled for.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
|
|
|
|
|
|
|
|
@cindex @code{.bss} directive, AArch64
|
|
|
|
@item .bss
|
|
|
|
This directive switches to the @code{.bss} section.
|
|
|
|
|
|
|
|
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
|
2016-03-19 01:30:12 +08:00
|
|
|
|
|
|
|
@cindex @code{.cpu} directive, AArch64
|
|
|
|
@item .cpu @var{name}
|
|
|
|
Set the target processor. Valid values for @var{name} are the same as
|
2018-07-02 18:18:24 +08:00
|
|
|
those accepted by the @option{-mcpu=} command-line option.
|
2016-03-19 01:30:12 +08:00
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
|
2016-03-19 01:30:12 +08:00
|
|
|
|
|
|
|
@cindex @code{.dword} directive, AArch64
|
|
|
|
@item .dword @var{expressions}
|
|
|
|
The @code{.dword} directive produces 64 bit values.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
|
2016-03-19 01:30:12 +08:00
|
|
|
|
|
|
|
@cindex @code{.even} directive, AArch64
|
|
|
|
@item .even
|
|
|
|
The @code{.even} directive aligns the output on the next even byte
|
|
|
|
boundary.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
|
2019-08-22 18:13:23 +08:00
|
|
|
|
|
|
|
@cindex @code{.float16} directive, AArch64
|
|
|
|
@item .float16 @var{value [,...,value_n]}
|
|
|
|
Place the half precision floating point representation of one or more
|
|
|
|
floating-point values into the current section.
|
|
|
|
The format used to encode the floating point values is always the
|
|
|
|
IEEE 754-2008 half precision floating point format.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
|
|
|
|
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
|
|
|
|
@c IIIIIIIIIIIIIIIIIIIIIIIIII
|
2016-03-19 01:30:12 +08:00
|
|
|
|
|
|
|
@cindex @code{.inst} directive, AArch64
|
|
|
|
@item .inst @var{expressions}
|
|
|
|
Inserts the expressions into the output as if they were instructions,
|
|
|
|
rather than data.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
|
|
|
|
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
|
|
|
|
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
|
|
|
|
|
|
|
|
@cindex @code{.ltorg} directive, AArch64
|
|
|
|
@item .ltorg
|
|
|
|
This directive causes the current contents of the literal pool to be
|
|
|
|
dumped into the current section (which is assumed to be the .text
|
|
|
|
section) at the current location (aligned to a word boundary).
|
2014-03-14 01:10:04 +08:00
|
|
|
GAS maintains a separate literal pool for each section and each
|
2012-08-13 22:52:54 +08:00
|
|
|
sub-section. The @code{.ltorg} directive will only affect the literal
|
|
|
|
pool of the current section and sub-section. At the end of assembly
|
|
|
|
all remaining, un-empty literal pools will automatically be dumped.
|
|
|
|
|
2014-03-14 01:10:04 +08:00
|
|
|
Note - older versions of GAS would dump the current literal
|
2012-08-13 22:52:54 +08:00
|
|
|
pool any time a section change occurred. This is no longer done, since
|
|
|
|
it prevents accurate control of the placement of literal pools.
|
|
|
|
|
|
|
|
@c MMMMMMMMMMMMMMMMMMMMMMMMMM
|
|
|
|
|
|
|
|
@c NNNNNNNNNNNNNNNNNNNNNNNNNN
|
|
|
|
@c OOOOOOOOOOOOOOOOOOOOOOOOOO
|
|
|
|
|
|
|
|
@c PPPPPPPPPPPPPPPPPPPPPPPPPP
|
|
|
|
|
|
|
|
@cindex @code{.pool} directive, AArch64
|
|
|
|
@item .pool
|
|
|
|
This is a synonym for .ltorg.
|
|
|
|
|
|
|
|
@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
|
|
|
|
@c RRRRRRRRRRRRRRRRRRRRRRRRRR
|
|
|
|
|
|
|
|
@cindex @code{.req} directive, AArch64
|
|
|
|
@item @var{name} .req @var{register name}
|
|
|
|
This creates an alias for @var{register name} called @var{name}. For
|
|
|
|
example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
foo .req w0
|
|
|
|
@end smallexample
|
|
|
|
|
2017-08-15 20:58:01 +08:00
|
|
|
ip0, ip1, lr and fp are automatically defined to
|
|
|
|
alias to X16, X17, X30 and X29 respectively.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
|
|
|
|
|
|
|
|
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
|
|
|
|
|
2016-03-19 01:30:12 +08:00
|
|
|
@cindex @code{.tlsdescadd} directive, AArch64
|
|
|
|
@item @code{.tlsdescadd}
|
|
|
|
Emits a TLSDESC_ADD reloc on the next instruction.
|
|
|
|
|
|
|
|
@cindex @code{.tlsdesccall} directive, AArch64
|
|
|
|
@item @code{.tlsdesccall}
|
|
|
|
Emits a TLSDESC_CALL reloc on the next instruction.
|
|
|
|
|
|
|
|
@cindex @code{.tlsdescldr} directive, AArch64
|
|
|
|
@item @code{.tlsdescldr}
|
|
|
|
Emits a TLSDESC_LDR reloc on the next instruction.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
|
|
|
|
|
|
|
|
@cindex @code{.unreq} directive, AArch64
|
|
|
|
@item .unreq @var{alias-name}
|
|
|
|
This undefines a register alias which was previously defined using the
|
|
|
|
@code{req} directive. For example:
|
|
|
|
|
|
|
|
@smallexample
|
|
|
|
foo .req w0
|
|
|
|
.unreq foo
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
An error occurs if the name is undefined. Note - this pseudo op can
|
|
|
|
be used to delete builtin in register name aliases (eg 'w0'). This
|
|
|
|
should only be done if it is really necessary.
|
|
|
|
|
|
|
|
@c VVVVVVVVVVVVVVVVVVVVVVVVVV
|
|
|
|
|
2019-04-25 22:06:53 +08:00
|
|
|
@cindex @code{.variant_pcs} directive, AArch64
|
|
|
|
@item .variant_pcs @var{symbol}
|
|
|
|
This directive marks @var{symbol} referencing a function that may
|
|
|
|
follow a variant procedure call standard with different register
|
|
|
|
usage convention from the base procedure call standard.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
|
|
|
|
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
|
|
|
|
|
2015-07-16 17:51:04 +08:00
|
|
|
@cindex @code{.xword} directive, AArch64
|
2016-03-19 01:30:12 +08:00
|
|
|
@item .xword @var{expressions}
|
|
|
|
The @code{.xword} directive produces 64 bit values. This is the same
|
|
|
|
as the @code{.dword} directive.
|
|
|
|
|
|
|
|
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
|
|
|
|
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
|
2015-07-16 17:51:04 +08:00
|
|
|
|
[aarch64] Add support for pointer authentication B key
Armv8.3-A has another key used in pointer authentication called the
B-key (other than the A-key that is already supported). In order for
stack unwinders to work it is necessary to be able to identify frames
that have been signed with the B-key rather than the A-key and it was
felt that keeping this as an augmentation character in the CIE was the
best bet. The DWARF extensions for ARM therefore propose to add a new
augmentation character 'B' to the CIE augmentation string and the
corresponding cfi directive ".cfi_b_key_frame". I've made the relevant
changes to GAS and LD to add support for B-key unwinding, which required
modifying LD to check for 'B' in the augmentation string, adding the
".cfi_b_key_frame" directive to GAS and adding a "pauth_key" field to
GAS's fde_entry and cie_entry structs.
The pointer authentication instructions will behave as NOPs on
architectures that don't support them, and so a check for the
architecture being assembled for is not necessary since there will be no
behavioural difference between augmentation strings with and without the
'B' character on such architectures.
2018-12-05 Sam Tebbs <sam.tebbs@arm.com>
bfd/
* elf-eh-frame.c (_bfd_elf_parse_eh_frame): Add check for 'B'.
gas/
* dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation.
(alloc_fde_entry): Add tc_fde_entry_init_extra invocation.
(output_cie): Add tc_output_cie_extra invocation.
(select_cie_for_fde): Add tc_cie_fde_equivalent_extra and
tc_cie_entry_init_extra invocation.
(frch_cfi_data, cfa_save_data): Move to dwgencfi.h.
* config/tc-aarch64.c (s_aarch64_cfi_b_key_frame): Declare.
(md_pseudo_table): Add "cfi_b_key_frame".
* config/tc-aarch64.h (tc_fde_entry_extras, tc_cie_entry_extras,
tc_fde_entry_init_extra, tc_output_cie_extra,
tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define.
* dw2gencfi.h (struct fde_entry): Add tc_fde_entry_extras invocation.
(pointer_auth_key): Define.
(frch_cfi_data, cfa_save_data): Move from dwgencfi.c.
* doc/c-aarch64.texi (.cfi_b_key_frame): Add documentation.
* testsuite/gas/aarch64/(pac_ab_key.d, pac_ab_key.s): New file.
2018-12-06 02:27:23 +08:00
|
|
|
@cindex @code{.cfi_b_key_frame} directive, AArch64
|
|
|
|
@item @code{.cfi_b_key_frame}
|
|
|
|
The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
|
|
|
|
corresponding to the current frame's FDE, meaning that its return address has
|
|
|
|
been signed with the B-key. If two frames are signed with differing keys then
|
|
|
|
they will not share the same CIE. This information is intended to be used by
|
|
|
|
the stack unwinder in order to properly authenticate return addresses.
|
|
|
|
|
2012-08-13 22:52:54 +08:00
|
|
|
@end table
|
|
|
|
|
|
|
|
@node AArch64 Opcodes
|
|
|
|
@section Opcodes
|
|
|
|
|
|
|
|
@cindex AArch64 opcodes
|
|
|
|
@cindex opcodes for AArch64
|
2014-03-14 01:10:04 +08:00
|
|
|
GAS implements all the standard AArch64 opcodes. It also
|
2012-08-13 22:52:54 +08:00
|
|
|
implements several pseudo opcodes, including several synthetic load
|
2013-01-11 03:51:55 +08:00
|
|
|
instructions.
|
2012-08-13 22:52:54 +08:00
|
|
|
|
|
|
|
@table @code
|
|
|
|
|
|
|
|
@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
|
|
|
|
@item LDR =
|
|
|
|
@smallexample
|
|
|
|
ldr <register> , =<expression>
|
|
|
|
@end smallexample
|
|
|
|
|
|
|
|
The constant expression will be placed into the nearest literal pool (if it not
|
|
|
|
already there) and a PC-relative LDR instruction will be generated.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
For more information on the AArch64 instruction set and assembly language
|
|
|
|
notation, see @samp{ARMv8 Instruction Set Overview} available at
|
|
|
|
@uref{http://infocenter.arm.com}.
|
|
|
|
|
|
|
|
|
|
|
|
@node AArch64 Mapping Symbols
|
|
|
|
@section Mapping Symbols
|
|
|
|
|
|
|
|
The AArch64 ELF specification requires that special symbols be inserted
|
|
|
|
into object files to mark certain features:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
|
|
|
|
@cindex @code{$x}
|
|
|
|
@item $x
|
|
|
|
At the start of a region of code containing AArch64 instructions.
|
|
|
|
|
|
|
|
@cindex @code{$d}
|
|
|
|
@item $d
|
|
|
|
At the start of a region of data.
|
|
|
|
|
|
|
|
@end table
|