binutils-gdb/ld/testsuite/ld-x86-64/apic.d

#name: 32-bit relocs w/ index but no base
#ld: --defsym APIC_BASE=0xfee00000
#objdump: -dw

.*: +file format .*


Disassembly of section \.text:

#...
[0-9a-f]+[ 	]+<apic_read>:
[ 	]*[0-9a-f]+:[ 	]+67 8b 04 bd 00 00 e0 fe[ 	]+mov[ 	]+(0xfee|-0x12)00000\(,%edi,4\),%eax
[ 	]*[0-9a-f]+:[ 	]+c3[ 	]+retq?[ 	]*
#...
[0-9a-f]+[ 	]+<apic_write>:
[ 	]*[0-9a-f]+:[ 	]+67 89 34 bd 00 00 e0 fe[ 	]+mov[ 	]+%esi,(0xfee|-0x12)00000\(,%edi,4\)
[ 	]*[0-9a-f]+:[ 	]+c3[ 	]+retq?[ 	]*
#pass
x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base reg Except for %eip-relative addressing, where we don't have a suitable relocation type silently wrapping at the 4G boundary, consistently force use of R_X86_64_32 (in ELF terms) instead of its sign-extending counterpart. This wasn't right in case there was no base register in the addressing expression. 2017-11-23 18:02:30 +08:00			`#name: 32-bit relocs w/ index but no base`
			`#ld: --defsym APIC_BASE=0xfee00000`
			`#objdump: -dw`

			`.: +file format .`


			`Disassembly of section \.text:`

			`#...`
			`[0-9a-f]+[ ]+<apic_read>:`
			`[ ]*[0-9a-f]+:[ ]+67 8b 04 bd 00 00 e0 fe[ ]+mov[ ]+(0xfee\|-0x12)00000\(,%edi,4\),%eax`
			`[ ][0-9a-f]+:[ ]+c3[ ]+retq?[ ]`
			`#...`
			`[0-9a-f]+[ ]+<apic_write>:`
			`[ ]*[0-9a-f]+:[ ]+67 89 34 bd 00 00 e0 fe[ ]+mov[ ]+%esi,(0xfee\|-0x12)00000\(,%edi,4\)`
			`[ ][0-9a-f]+:[ ]+c3[ ]+retq?[ ]`
			`#pass`