2003-08-30 00:41:31 +08:00
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# frv testcase for nfdmuls $FRi,$FRj,$FRk
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2003-10-09 02:21:02 +08:00
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# mach: fr500 fr550 frv
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2003-08-30 00:41:31 +08:00
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.include "testutils.inc"
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float_constants
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start
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load_float_constants
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load_float_constants1
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.global nfdmuls
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nfdmuls:
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nfdmuls fr16,fr4,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr8,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr12,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr16,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr20,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr24,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr28,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr32,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr36,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr40,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr44,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr16,fr48,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr4,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr8,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr12,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr16,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr3,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr2,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr20,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr24,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr28,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr32,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr36,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr40,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr44,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr20,fr48,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr0,fr2
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test_fr_fr fr2,fr0
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test_fr_fr fr3,fr0
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr4,fr2
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test_fr_fr fr2,fr4
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test_fr_fr fr3,fr4
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr8,fr2
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test_fr_fr fr2,fr8
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test_fr_fr fr3,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr12,fr2
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test_fr_fr fr2,fr12
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test_fr_fr fr3,fr12
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr16,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr20,fr2
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test_fr_fr fr2,fr16
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test_fr_fr fr2,fr20
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test_fr_fr fr3,fr16
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test_fr_fr fr3,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr24,fr2
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test_fr_fr fr2,fr24
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test_fr_fr fr3,fr24
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr28,fr2
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test_fr_fr fr2,fr28
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test_fr_fr fr3,fr28
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr32,fr2
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test_fr_fr fr2,fr32
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test_fr_fr fr3,fr32
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr36,fr2
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test_fr_fr fr2,fr36
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test_fr_fr fr3,fr36
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr40,fr2
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test_fr_fr fr2,fr40
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test_fr_fr fr3,fr40
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr44,fr2
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test_fr_fr fr2,fr44
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test_fr_fr fr3,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr48,fr2
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test_fr_fr fr2,fr48
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test_fr_fr fr3,fr48
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr52,fr2
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test_fr_fr fr2,fr52
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test_fr_fr fr3,fr52
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr28,fr8,fr2
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test_fr_fr fr2,fr8
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test_fr_fr fr3,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr8,fr28,fr2
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test_fr_fr fr2,fr8
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test_fr_fr fr3,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr32,fr36,fr2
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test_fr_fr fr2,fr40
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test_fr_fr fr3,fr40
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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; try to cause exceptions
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nfdmuls fr48,fr32,fr2
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; test_fr_fr fr2,fr44
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; test_fr_fr fr3,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr52,fr28,fr2
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; test_fr_fr fr2,fr44
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; test_fr_fr fr3,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr56,fr28,fr2
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; test_fr_fr fr2,fr44
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; test_fr_fr fr3,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdmuls fr60,fr28,fr2
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; test_fr_fr fr2,fr44
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; test_fr_fr fr3,fr44
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test_spr_immed 0xc,fner1
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test_spr_immed 0,fner0
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pass
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