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binutils-gdb/ld/testsuite/ld-mips-elf/lsi-4010-isa.d

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MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core (for an odd reason referred to as LSI R4010 across our code base) as a MIPS II processor in BFD as well, fixing a bug that has been there since forever and addressing linker warnings like: $ as -m4010 empty.s -o 4010.o $ ld -r 4010.o -o 4010-r.o ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags $ due to the ISA level being recorded as MIPS III in ELF file header's `e_flags' vs MIPS II in the MIPS ABI Flags section: $ readelf -Ah 4010.o ELF Header: Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, big endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: REL (Relocatable file) Machine: MIPS R3000 Version: 0x1 Entry point address: 0x0 Start of program headers: 0 (bytes into file) Start of section headers: 348 (bytes into file) Flags: 0x20821000, 4010, o32, mips3 Size of this header: 52 (bytes) Size of program headers: 0 (bytes) Number of program headers: 0 Size of section headers: 40 (bytes) Number of section headers: 11 Section header string table index: 10 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float (double precision) MIPS ABI Flags Version: 0 ISA: MIPS2 GPR size: 32 CPR1 size: 32 CPR2 size: 0 FP ABI: Hard float (double precision) ISA Extension: LSI R4010 ASEs: None FLAGS 1: 00000000 FLAGS 2: 00000000 $ Available documentation[1][2] clearly indicates the LSI CW4010 processor is only backwards compatible with the MIPS R4000 processor as far as the latter's 32-bit instructions are concerned and consequently can only be considered a MIPS II ISA implementation (with vendor extensions). This fixes an LD testsuite failure: FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32" triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets. References: [1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995, presented at Hot Chips VII, Stanford University, Stanford, California, August 1995 [2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017 bfd/ * cpu-mips.c (arch_info_struct): Mark the 4010 32-bit. * elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'. (mips_mach_extensions): Mark `bfd_mach_mips4010' as extending `bfd_mach_mips6000' rather than `bfd_mach_mips4000'. ld/ * testsuite/ld-mips-elf/lsi-4010-isa.d: New test. * ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-06-27 02:20:50 +08:00
#readelf: -Ah
#name: LSI 4010 processor ISA level
#source: empty.s
MIPS/LD/testsuite: Correct mips-elf.exp test ABI/emul/endian arrangement Similarly to commit 86b24e15c45b ("MIPS/LD/testsuite: Correct comm-data.exp test ABI/emul/endian arrangement") update the mips-elf.exp test script to: - correctly select emulations for targets using non-traditional MIPS emulations, - correctly select ABIs for targets that do not support all of them, - use the default endianness selection where possible to benefit targets that support only one, - simplify test invocation by providing ABI-specific `run_dump_test' wrappers, specifically `run_dump_test_o32', `run_dump_test_n32', `run_dump_test_n64' and `run_dump_test_eabi', which remove the need to use conditionals across the Expect script or to repeat ABI-specific GAS and LD flags with each invocation, removing numerous test failures for `mips-sgi-irix6', `mips64-openbsd', `mips64el-openbsd' and `mips64el-ps2-elf' targets and broadening coverage for several MIPS targets. There are some new failures for the `mips64el-ps2-elf' target with tests that were not previously run for that target: FAIL: MIPS16 link branch to absolute expression (n32) FAIL: MIPS16 link branch to absolute expression 1 (n32) FAIL: MIPS16 link branch to absolute expression 2 (n32) FAIL: microMIPS link branch to absolute expression (n32) FAIL: MIPS ELF got reloc n32 FAIL: MIPS ELF xgot reloc n32 FAIL: undefined weak symbol overflow (n32) FAIL: R_MIPS16_HI16 and R_MIPS16_LO16 relocs n32 FAIL: ld-mips-elf/attr-gnu-4-0-n32-ph FAIL: ld-mips-elf/attr-gnu-4-1-n32-ph FAIL: ld-mips-elf/attr-gnu-4-2-n32-ph FAIL: ld-mips-elf/attr-gnu-4-3-n32-ph FAIL: MIPSr6 JALR reloc unaligned/cross-mode link test (n32) which are mostly due to dump discrepancies caused by mapping differences coming from the default linker scripts used by these test cases, or sometimes because of the specific MIPS processor architecture recorded in the ELF file taking precedence over the general MIPS ISA level also recorded. Finally, the R_MIPS16_HI16/R_MIPS16_LO16 relocation test failure is a preexisting issue with the IRIX style emulation. These failures will have to be addressed separately. ld/ * testsuite/ld-mips-elf/mips-elf.exp (run_dump_test_abi) (run_dump_test_o32, run_dump_test_n32, run_dump_test_n64) (run_dump_test_eabi): New procedures. (has_newabi, has_elf32): Remove variables. (has_abi): New associative array variable. (abi_asflags, abi_ldflags): Update settings across targets. (irixemul): New variable. Replace `run_dump_test' calls where applicable throughout with `run_dump_test_o32', `run_dump_test_n32', `run_dump_test_n64' and `run_dump_test_eabi' as appropriate. Remove explicit passing of `abi_asflags' and `abi_ldflags'. Use `noarch' for tests that require their own architecture setting. Force the big endianness for tests that require it. Select the endianness required for `objdump invocation with the `reloc-2' test. Conditionalize tests run via `run_ld_link_tests' on the ABI required and use the ABI list from the `has_abi' array where appropriate. * testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d: Remove ABI and endianness selection options from `ld' and `source' tags. Relax output format matching. * testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d: Likewise. * testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: Remove ABI and endianness selection options from `as', `ld', `source' tags, and also the `-march=from-abi' option. Remove the `as' tag where it would become empty. * testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-addend.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-local-micromips.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-local-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-local-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-local.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-n32.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-n64.d: Likewise. * testsuite/ld-mips-elf/bal-jalx-pic.d: Likewise. * testsuite/ld-mips-elf/branch-absolute-addend-n32.d: Likewise. * testsuite/ld-mips-elf/branch-absolute-addend-n64.d: Likewise. * testsuite/ld-mips-elf/branch-absolute-addend.d: Likewise. * testsuite/ld-mips-elf/branch-absolute-n32.d: Likewise. * testsuite/ld-mips-elf/branch-absolute-n64.d: Likewise. * testsuite/ld-mips-elf/branch-absolute.d: Likewise. * testsuite/ld-mips-elf/dyn-sec64.d: Likewise. * testsuite/ld-mips-elf/eh-frame1-n32.d: Likewise. * testsuite/ld-mips-elf/eh-frame1-n64.d: Likewise. * testsuite/ld-mips-elf/eh-frame2-n32.d: Likewise. * testsuite/ld-mips-elf/eh-frame2-n64.d: Likewise. * testsuite/ld-mips-elf/elf-rel-got-n32-embed.d: Likewise. * testsuite/ld-mips-elf/elf-rel-got-n32.d: Likewise. * testsuite/ld-mips-elf/elf-rel-got-n64-embed.d: Likewise. * testsuite/ld-mips-elf/elf-rel-got-n64-irix.d: Likewise. * testsuite/ld-mips-elf/elf-rel-got-n64.d: Likewise. * testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise. * testsuite/ld-mips-elf/elf-rel-xgot-n32.d: Likewise. * testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise. * testsuite/ld-mips-elf/elf-rel-xgot-n64-irix.d: Likewise. * testsuite/ld-mips-elf/elf-rel-xgot-n64.d: Likewise. * testsuite/ld-mips-elf/emit-relocs-1.d: Likewise. * testsuite/ld-mips-elf/got-dump-2.d: Likewise. * testsuite/ld-mips-elf/got-page-2.d: Likewise. * testsuite/ld-mips-elf/jal-global-overflow-0.d: Likewise. * testsuite/ld-mips-elf/jal-global-overflow-1.d: Likewise. * testsuite/ld-mips-elf/jal-local-overflow-0.d: Likewise. * testsuite/ld-mips-elf/jal-local-overflow-1.d: Likewise. * testsuite/ld-mips-elf/jalbal.d: Likewise. * testsuite/ld-mips-elf/jalx-addend-n32.d: Likewise. * testsuite/ld-mips-elf/jalx-addend-n64.d: Likewise. * testsuite/ld-mips-elf/jalx-addend.d: Likewise. * testsuite/ld-mips-elf/jalx-local-n32.d: Likewise. * testsuite/ld-mips-elf/jalx-local-n64.d: Likewise. * testsuite/ld-mips-elf/jalx-local.d: Likewise. * testsuite/ld-mips-elf/jr-to-b-1.d: Likewise. * testsuite/ld-mips-elf/jr-to-b-2.d: Likewise. * testsuite/ld-mips-elf/lsi-4010-isa.d: Likewise. * testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: Likewise. * testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: Likewise. * testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: Likewise. * testsuite/ld-mips-elf/micromips-branch-absolute.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-2.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-3.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-1.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-2.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-1.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32-1.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64-1.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-n32-1.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-n32-2.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-n64-1.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-n64-2.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-absolute.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-addend-2.d: Likewise. * testsuite/ld-mips-elf/mips16-branch-addend-3.d: Likewise. * testsuite/ld-mips-elf/mips16-hilo-n32.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-0.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-1.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-addend-2.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-addend-6.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-n32-0.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-n32-1.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-0.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-1.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-addend-2.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-addend-6.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-n32-0.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-n32-1.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-n64-sym32-0.d: Likewise. * testsuite/ld-mips-elf/mips16e2-pcrel-n64-sym32-1.d: Likewise. * testsuite/ld-mips-elf/multi-got-1.d: Likewise. * testsuite/ld-mips-elf/multi-got-hidden-1.d: Likewise. * testsuite/ld-mips-elf/multi-got-hidden-2.d: Likewise. * testsuite/ld-mips-elf/multi-got-no-shared.d: Likewise. * testsuite/ld-mips-elf/no-shared-1-n32.d: Likewise. * testsuite/ld-mips-elf/no-shared-1-n64.d: Likewise. * testsuite/ld-mips-elf/no-shared-1-o32.d: Likewise. * testsuite/ld-mips-elf/pic-and-nonpic-2.d: Likewise. * testsuite/ld-mips-elf/pic-and-nonpic-3-error.d: Likewise. * testsuite/ld-mips-elf/pic-and-nonpic-4-error.d: Likewise. * testsuite/ld-mips-elf/pie-n32.d: Likewise. * testsuite/ld-mips-elf/pie-n64.d: Likewise. * testsuite/ld-mips-elf/pie-o32.d: Likewise. * testsuite/ld-mips-elf/rel32-n32.d: Likewise. * testsuite/ld-mips-elf/rel32-o32.d: Likewise. * testsuite/ld-mips-elf/rel64.d: Likewise. * testsuite/ld-mips-elf/relax-jalr-n32.d: Likewise. * testsuite/ld-mips-elf/reloc-1-n32.d: Likewise. * testsuite/ld-mips-elf/reloc-1-n64.d: Likewise. * testsuite/ld-mips-elf/reloc-2.d: Likewise. * testsuite/ld-mips-elf/reloc-3-n32.d: Likewise. * testsuite/ld-mips-elf/reloc-local-overflow.d: Likewise. * testsuite/ld-mips-elf/textrel-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-2.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch-r6-2.d: Likewise. * testsuite/ld-mips-elf/unaligned-branch.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-0.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-0.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-0.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jump-micromips.d: Likewise. * testsuite/ld-mips-elf/unaligned-jump-mips16.d: Likewise. * testsuite/ld-mips-elf/unaligned-jump.d: Likewise. * testsuite/ld-mips-elf/unaligned-ldpc-0.d: Likewise. * testsuite/ld-mips-elf/unaligned-ldpc-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-lwpc-0.d: Likewise. * testsuite/ld-mips-elf/unaligned-lwpc-1.d: Likewise.
2018-07-13 03:01:44 +08:00
#as: -m4010
#ld: -r
MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core (for an odd reason referred to as LSI R4010 across our code base) as a MIPS II processor in BFD as well, fixing a bug that has been there since forever and addressing linker warnings like: $ as -m4010 empty.s -o 4010.o $ ld -r 4010.o -o 4010-r.o ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags $ due to the ISA level being recorded as MIPS III in ELF file header's `e_flags' vs MIPS II in the MIPS ABI Flags section: $ readelf -Ah 4010.o ELF Header: Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, big endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: REL (Relocatable file) Machine: MIPS R3000 Version: 0x1 Entry point address: 0x0 Start of program headers: 0 (bytes into file) Start of section headers: 348 (bytes into file) Flags: 0x20821000, 4010, o32, mips3 Size of this header: 52 (bytes) Size of program headers: 0 (bytes) Number of program headers: 0 Size of section headers: 40 (bytes) Number of section headers: 11 Section header string table index: 10 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float (double precision) MIPS ABI Flags Version: 0 ISA: MIPS2 GPR size: 32 CPR1 size: 32 CPR2 size: 0 FP ABI: Hard float (double precision) ISA Extension: LSI R4010 ASEs: None FLAGS 1: 00000000 FLAGS 2: 00000000 $ Available documentation[1][2] clearly indicates the LSI CW4010 processor is only backwards compatible with the MIPS R4000 processor as far as the latter's 32-bit instructions are concerned and consequently can only be considered a MIPS II ISA implementation (with vendor extensions). This fixes an LD testsuite failure: FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32" triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets. References: [1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995, presented at Hot Chips VII, Stanford University, Stanford, California, August 1995 [2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017 bfd/ * cpu-mips.c (arch_info_struct): Mark the 4010 32-bit. * elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'. (mips_mach_extensions): Mark `bfd_mach_mips4010' as extending `bfd_mach_mips6000' rather than `bfd_mach_mips4000'. ld/ * testsuite/ld-mips-elf/lsi-4010-isa.d: New test. * ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-06-27 02:20:50 +08:00
ELF Header:
#...
Flags: 0x1082[01]000, 4010(?:, o32)?, mips2
#...
MIPS ABI Flags Version: 0
ISA: MIPS2
GPR size: 32
CPR1 size: 32
CPR2 size: 0
FP ABI: .*
ISA Extension: LSI R4010
ASEs:
None
FLAGS 1: .*
FLAGS 2: .*
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