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https://sourceware.org/git/binutils-gdb.git
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217 lines
3.3 KiB
ArmAsm
217 lines
3.3 KiB
ArmAsm
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//Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp
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# mach: bfin
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.include "testutils.inc"
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start
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// Spec Reference: ldimmhalf lzhi ibml
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I0 = 0x2001 (Z);
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I0.H = 0x2000;
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I1 = 0x2003 (Z);
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I1.H = 0x2002;
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I2 = 0x2005 (Z);
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I2.H = 0x2004;
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I3 = 0x2007 (Z);
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I3.H = 0x2006;
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L0 = 0x2009 (Z);
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L0.H = 0x2008;
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L1 = 0x200b (Z);
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L1.H = 0x200a;
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L2 = 0x200d (Z);
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L2.H = 0x200c;
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L3 = 0x200f (Z);
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L3.H = 0x200e;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x20002001;
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CHECKREG r1, 0x20022003;
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CHECKREG r2, 0x20042005;
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CHECKREG r3, 0x20062007;
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CHECKREG r4, 0x20082009;
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CHECKREG r5, 0x200a200b;
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CHECKREG r6, 0x200c200d;
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CHECKREG r7, 0x200e200f;
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I0 = 0x0111 (Z);
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I0.H = 0x1000;
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I1 = 0x1111 (Z);
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I1.H = 0x1000;
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I2 = 0x2222 (Z);
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I2.H = 0x2000;
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I3 = 0x3333 (Z);
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I3.H = 0x3000;
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L0 = 0x4444 (Z);
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L0.H = 0x4000;
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L1 = 0x5555 (Z);
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L1.H = 0x5000;
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L2 = 0x6666 (Z);
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L2.H = 0x6000;
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L3 = 0x7777 (Z);
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L3.H = 0x7000;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x10000111;
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CHECKREG r1, 0x10001111;
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CHECKREG r2, 0x20002222;
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CHECKREG r3, 0x30003333;
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CHECKREG r4, 0x40004444;
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CHECKREG r5, 0x50005555;
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CHECKREG r6, 0x60006666;
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CHECKREG r7, 0x70007777;
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I0 = 0x8888 (Z);
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I0.H = 0x8000;
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I1 = 0x9aaa (Z);
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I1.H = 0x9000;
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I2 = 0xabbb (Z);
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I2.H = 0xa000;
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I3 = 0xbccc (Z);
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I3.H = 0xb000;
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L0 = 0xcddd (Z);
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L0.H = 0xc000;
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L1 = 0xdeee (Z);
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L1.H = 0xd000;
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L2 = 0xefff (Z);
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L2.H = 0xe000;
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L3 = 0xf111 (Z);
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L3.H = 0xf000;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x80008888;
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CHECKREG r1, 0x90009aaa;
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CHECKREG r2, 0xa000abbb;
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CHECKREG r3, 0xb000bccc;
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CHECKREG r4, 0xc000cddd;
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CHECKREG r5, 0xd000deee;
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CHECKREG r6, 0xe000efff;
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CHECKREG r7, 0xf000f111;
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B0 = 0x3001 (Z);
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B0.H = 0x3000;
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B1 = 0x3003 (Z);
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B1.H = 0x3002;
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B2 = 0x3005 (Z);
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B2.H = 0x3004;
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B3 = 0x3007 (Z);
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B3.H = 0x3006;
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M0 = 0x3009 (Z);
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M0.H = 0x3008;
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M1 = 0x300b (Z);
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M1.H = 0x300a;
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M2 = 0x300d (Z);
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M2.H = 0x300c;
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M3 = 0x300f (Z);
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M3.H = 0x300e;
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x30003001;
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CHECKREG r1, 0x30023003;
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CHECKREG r2, 0x30043005;
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CHECKREG r3, 0x30063007;
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CHECKREG r4, 0x30083009;
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CHECKREG r5, 0x300A300B;
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CHECKREG r6, 0x300c300d;
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CHECKREG r7, 0x300e300f;
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B0 = 0x0110 (Z);
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B0.H = 0x1000;
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B1 = 0x1110 (Z);
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B1.H = 0x1000;
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B2 = 0x2220 (Z);
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B2.H = 0x2000;
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B3 = 0x3330 (Z);
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B3.H = 0x3000;
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M0 = 0x4440 (Z);
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M0.H = 0x4000;
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M1 = 0x5550 (Z);
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M1.H = 0x5000;
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M2 = 0x6660 (Z);
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M2.H = 0x6000;
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M3 = 0x7770 (Z);
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M3.H = 0x7000;
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x10000110;
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CHECKREG r1, 0x10001110;
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CHECKREG r2, 0x20002220;
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CHECKREG r3, 0x30003330;
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CHECKREG r4, 0x40004440;
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CHECKREG r5, 0x50005550;
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CHECKREG r6, 0x60006660;
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CHECKREG r7, 0x70007770;
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B0 = 0xf880 (Z);
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B0.H = 0x8000;
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B1 = 0xfaa0 (Z);
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B1.H = 0xa000;
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B2 = 0xfbb0 (Z);
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B2.H = 0xb000;
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B3 = 0xfcc0 (Z);
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B3.H = 0xc000;
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M0 = 0xfdd0 (Z);
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M0.H = 0xd000;
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M1 = 0xfee0 (Z);
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M1.H = 0xe000;
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M2 = 0xfff0 (Z);
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M2.H = 0xf000;
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M3 = 0xf110 (Z);
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M3.H = 0x1000;
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x8000f880;
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CHECKREG r1, 0xa000faa0;
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CHECKREG r2, 0xb000fbb0;
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CHECKREG r3, 0xc000fcc0;
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CHECKREG r4, 0xd000fdd0;
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CHECKREG r5, 0xe000fee0;
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CHECKREG r6, 0xf000fff0;
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CHECKREG r7, 0x1000f110;
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pass
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