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120 lines
2.8 KiB
ArmAsm
120 lines
2.8 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp
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// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round)
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# mach: bfin
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.include "testutils.inc"
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start
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A1 = A0 = 0;
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// The result accumulated in A , and stored to a reg half
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imm32 r0, 0xf3545abd;
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imm32 r1, 0x7fbcfec7;
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imm32 r2, 0xc7fff679;
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imm32 r3, 0xd0799007;
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imm32 r4, 0xefb79f69;
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imm32 r5, 0xcd35700b;
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imm32 r6, 0xe00c87fd;
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imm32 r7, 0xf78e909f;
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A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (ISS2);
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R1 = A0.w;
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A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (ISS2);
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R3 = A0.w;
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A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (ISS2);
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R5 = A0.w;
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A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (ISS2);
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R7 = A0.w;
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CHECKREG r0, 0xF3548000;
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CHECKREG r1, 0xFF910EEB;
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CHECKREG r2, 0xC7FF8000;
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CHECKREG r3, 0xE71226F2;
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CHECKREG r4, 0xEFB78000;
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CHECKREG r5, 0xEA4D52D5;
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CHECKREG r6, 0xE00C8000;
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CHECKREG r7, 0xEE42DC2B;
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// The result accumulated in A , and stored to a reg half (MNOP)
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imm32 r0, 0xc5548abd;
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imm32 r1, 0x9b5cfec7;
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imm32 r2, 0xa9b55679;
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imm32 r3, 0xb09b5007;
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imm32 r4, 0xcfb9b5c9;
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imm32 r5, 0x52359b5c;
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imm32 r6, 0xe50c5098;
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imm32 r7, 0x675e7509;
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R0.L = ( A0 -= R1.L * R0.L ) (ISS2);
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R1 = A0.w;
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R2.L = ( A0 += R2.L * R3.H ) (ISS2);
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R3 = A0.w;
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R4.L = ( A0 = R4.H * R5.L ) (ISS2);
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R5 = A0.w;
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R6.L = ( A0 -= R6.H * R7.H ) (ISS2);
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R7 = A0.w;
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CHECKREG r0, 0xC5548000;
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CHECKREG r1, 0xEDB37D40;
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CHECKREG r2, 0xA9B58000;
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CHECKREG r3, 0xD2E20883;
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CHECKREG r4, 0xCFB97FFF;
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CHECKREG r5, 0x12FAA97C;
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CHECKREG r6, 0xE50C7FFF;
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CHECKREG r7, 0x1DDCBB14;
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// The result accumulated in A , and stored to a reg half (MNOP)
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imm32 r0, 0x4b54babd;
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imm32 r1, 0x12346ec7;
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imm32 r2, 0xa4bbe679;
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imm32 r3, 0x8abdb707;
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imm32 r4, 0x9f4b7b69;
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imm32 r5, 0xa234877b;
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imm32 r6, 0xb00c4887;
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imm32 r7, 0xc78ea4b8;
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R0.L = ( A0 = R1.L * R0.L ) (ISS2);
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R1 = A0.w;
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R2.L = ( A0 -= R2.H * R3.L ) (ISS2);
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R3 = A0.w;
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R4.L = ( A0 = R4.H * R5.H ) (ISS2);
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R5 = A0.w;
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R6.L = ( A0 += R6.L * R7.H ) (ISS2);
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R7 = A0.w;
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CHECKREG r0, 0x4B548000;
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CHECKREG r1, 0xE2075EEB;
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CHECKREG r2, 0xA4BB8000;
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CHECKREG r3, 0xC80330CE;
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CHECKREG r4, 0x9F4B7FFF;
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CHECKREG r5, 0x236ED13C;
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CHECKREG r6, 0xB00C7FFF;
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CHECKREG r7, 0x1370FD1E;
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// The result accumulated in A , and stored to a reg half
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imm32 r0, 0x1a545abd;
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imm32 r1, 0x42fcfec7;
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imm32 r2, 0xc53f5679;
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imm32 r3, 0x9c64f007;
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imm32 r4, 0xafc7ec69;
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imm32 r5, 0xd23c891b;
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imm32 r6, 0xc00cc602;
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imm32 r7, 0x678edc7e;
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A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (ISS2);
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R3 = A0.w;
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A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (ISS2);
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R7 = A0.w;
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A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (ISS2);
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R5 = A0.w;
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A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (ISS2);
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R1 = A0.w;
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CHECKREG r0, 0x1A548000;
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CHECKREG r1, 0xF0477293;
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CHECKREG r2, 0xC53F7FFF;
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CHECKREG r3, 0x13020C09;
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CHECKREG r4, 0xAFC78000;
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CHECKREG r5, 0xEEE57293;
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CHECKREG r6, 0xC00C8000;
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CHECKREG r7, 0xFD3CE337;
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pass
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