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binutils-gdb/opcodes/ChangeLog

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x86: fold various non-memory operand AVX512VL templates There's little point carrying up to three templates per insn flavor when the sole difference is operand size and the dependency on AVX512VL being enabled. Instead the need for AVX512VL can be derived from an operand allowing for ZMMword as well as one or both or XMMword and YMMword (irrespective of whether this is a register or memory operand). Without further abstraction to deal with the different Disp8MemShift values between the templates, only a limited set (mostly ones only allowing for non-memory operands) can be folded, which is being done here. Also drop IgnoreSize wherever possible from anything that's being touched anyway.
2018-04-26 14:55:02 +08:00
2018-04-26 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Fold various non-memory operand AVX512VL
templates into their base ones.
* i386-tlb.h: Re-generate.
x86: CpuXSAVE is a prereq for various other features All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as XRSTOR should be enabled when enabling these ISA extensions. Leverage these implications to shorten some of the cpu_flag_init[] entries.
2018-04-26 14:48:56 +08:00
2018-04-26 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
* i386-init.h: Re-generate.
x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask It's not clear to me why they had been introduced - the respective comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers are very well supported (and necessary) with just AVX512F.
2018-04-26 14:48:01 +08:00
2018-04-26 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
comment.
(cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
and CpuRegMask.
* i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
CpuRegMask: Delete.
(union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
cpuregzmm, and cpuregmask.
* i386-init.h: Re-generate.
* i386-tbl.h: Re-generate.
x86: x87-related adjustments Neither 287 wrt 8087 nor 387 wrt 287 are proper supersets - in each case some insns get removed from the ISA (they become NOPs, but code intended for newer co-processors should not use them). Furthermore with .no87, ST should not be recognized as a register name.
2018-04-26 14:45:35 +08:00
2018-04-26 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
* i386-init.h: Re-generate.
x86: drop VexImmExt It's only used in assertions, and hence not really needed for correct code generation.
2018-04-26 14:30:06 +08:00
2018-04-26 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (VexImmExt): Delete.
* i386-opc.h (VexImmExt, veximmext): Delete.
* i386-opc.tbl: Drop all VexImmExt uses.
* i386-tlb.h: Re-generate.
x86: drop redundant AVX512VL shift templates These were wrongly left in place by commit ed438a93f1 ("x86: fold certain AVX512 rotate and shift templates").
2018-04-25 22:26:10 +08:00
2018-04-25 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
register-only forms.
* i386-tlb.h: Re-generate.
Fix the mask for the sqrdml(a|s)h instructions. Rn is supposed to have a 5 bit range but instead was given 4 bits causing these instructions to disassemble as unknown instructions. opcodes/ * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks. gas/ * testsuite/gas/aarch64/rdma.s: Test for larger register numbers. * testsuite/gas/aarch64/rdma.d: Update results. * testsuite/gas/aarch64/rdma-directive.d: Likewise.
2018-04-25 20:37:30 +08:00
2018-04-25 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
Enable Intel CLDEMOTE instruction. gas/ * config/tc-i386.c (cpu_arch): Add .cldemote. * doc/c-i386.texi: Document cldemote/.cldemote. * testsuite/gas/i386/cldemote-intel.d: New. * testsuite/gas/i386/cldemote.d: Likewise. * testsuite/gas/i386/cldemote.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. * testsuite/gas/i386/x86-64-cldemote-intel.d: New. * testsuite/gas/i386/x86-64-cldemote.d: Likewise. * testsuite/gas/i386/x86-64-cldemote.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c NOP encoding that maps to cldemote. * testsuite/gas/i386/nops.d: Likewise. * testsuite/gas/i386/nops.s: Likewise. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops.s: Likewise. opcode/ * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, PREFIX_0F1C. * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, (cpu_flags): Add CpuCLDEMOTE. * i386-init.h: Regenerate. * i386-opc.h (enum): Add CpuCLDEMOTE, (i386_cpu_flags): Add cpucldemote. * i386-opc.tbl: Add cldemote. * i386-tbl.h: Regenerate.
2018-04-17 05:09:01 +08:00
2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
PREFIX_0F1C.
* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
(cpu_flags): Add CpuCLDEMOTE.
* i386-init.h: Regenerate.
* i386-opc.h (enum): Add CpuCLDEMOTE,
(i386_cpu_flags): Add cpucldemote.
* i386-opc.tbl: Add cldemote.
* i386-tbl.h: Regenerate.
Remove sh5 and sh64 support include/ * dis-asm.h: Remove sh5 and sh64 support. bfd/ * Makefile.am: Remove sh5 and sh64 support. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-sh.c: Likewise. * elf32-sh-relocs.h: Likewise. * elf32-sh.c: Likewise. * targets.c: Likewise. * elf32-sh64-com.c: Delete. * elf32-sh64.c: Delete. * elf32-sh64.h: Delete. * elf64-sh64.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove sh5 and sh64 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Delete. * sh64-opc.c: Delete. * sh64-opc.h: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. bintuils/ * testsuite/binutils-all/objcopy.exp: Remove sh5 and sh64 support. gas/ * Makefile.am: Remove sh5 and sh64 support. * config/tc-sh.c: Likewise. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/as.texinfo: Likewise. * testsuite/gas/cfi/cfi.exp: Likewise. * testsuite/gas/sh/basic.exp: Likewise. * config/tc-sh64.c: Delete. * config/tc-sh64.h: Delete. * doc/c-sh64.texi: Delete. * testsuite/gas/sh/sh64/abi-32.d: Delete. * testsuite/gas/sh/sh64/abi-32.s: Delete. * testsuite/gas/sh/sh64/abi-64.d: Delete. * testsuite/gas/sh/sh64/abi-64.s: Delete. * testsuite/gas/sh/sh64/basic-1.d: Delete. * testsuite/gas/sh/sh64/basic-1.s: Delete. * testsuite/gas/sh/sh64/case-1.d: Delete. * testsuite/gas/sh/sh64/case-1.s: Delete. * testsuite/gas/sh/sh64/case-noexp-1.d: Delete. * testsuite/gas/sh/sh64/crange1-1.d: Delete. * testsuite/gas/sh/sh64/crange1-2.d: Delete. * testsuite/gas/sh/sh64/crange1.s: Delete. * testsuite/gas/sh/sh64/crange2-1.d: Delete. * testsuite/gas/sh/sh64/crange2-2.d: Delete. * testsuite/gas/sh/sh64/crange2-noexp-1.d: Delete. * testsuite/gas/sh/sh64/crange2.s: Delete. * testsuite/gas/sh/sh64/crange3-1.d: Delete. * testsuite/gas/sh/sh64/crange3.s: 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* testsuite/gas/sh/sh64/lineno.s: Delete. * testsuite/gas/sh/sh64/localcom-1.d: Delete. * testsuite/gas/sh/sh64/localcom-1.s: Delete. * testsuite/gas/sh/sh64/mix-1.d: Delete. * testsuite/gas/sh/sh64/mix-1.s: Delete. * testsuite/gas/sh/sh64/mix-noexp-1.d: Delete. * testsuite/gas/sh/sh64/movi-1.s: Delete. * testsuite/gas/sh/sh64/movi-2.s: Delete. * testsuite/gas/sh/sh64/movi-3.d: Delete. * testsuite/gas/sh/sh64/movi-3.s: Delete. * testsuite/gas/sh/sh64/movi32-1.d: Delete. * testsuite/gas/sh/sh64/movi32-2.d: Delete. * testsuite/gas/sh/sh64/movi32-noexp-2.d: Delete. * testsuite/gas/sh/sh64/movi64-1.d: Delete. * testsuite/gas/sh/sh64/movi64-2.d: Delete. * testsuite/gas/sh/sh64/movi64-2.s: Delete. * testsuite/gas/sh/sh64/movi64-3.d: Delete. * testsuite/gas/sh/sh64/movi64-noexp-2.d: Delete. * testsuite/gas/sh/sh64/pt-1.d: Delete. * testsuite/gas/sh/sh64/pt-1.s: Delete. * testsuite/gas/sh/sh64/pt-2.s: Delete. * testsuite/gas/sh/sh64/pt-noexp-1.d: Delete. * testsuite/gas/sh/sh64/pt32-1.d: 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* testsuite/ld-srec/srec.exp: Likewise. * testsuite/ld-undefined/undefined.exp: Likewise. * emulparams/shelf32.sh: Delete. * emulparams/shelf32_linux.sh: Delete. * emulparams/shelf32_nbsd.sh: Delete. * emulparams/shelf64.sh: Delete. * emulparams/shelf64_nbsd.sh: Delete. * emulparams/shlelf32.sh: Delete. * emulparams/shlelf32_linux.sh: Delete. * emulparams/shlelf32_nbsd.sh: Delete. * emulparams/shlelf64.sh: Delete. * emulparams/shlelf64_nbsd.sh: Delete. * emultempl/sh64elf.em: Delete. * testsuite/ld-sh/sh64/abi32.sd: Delete. * testsuite/ld-sh/sh64/abi32.xd: Delete. * testsuite/ld-sh/sh64/abi64.sd: Delete. * testsuite/ld-sh/sh64/abi64.xd: Delete. * testsuite/ld-sh/sh64/abixx-noexp.sd: Delete. * testsuite/ld-sh/sh64/cmpct1.sd: Delete. * testsuite/ld-sh/sh64/cmpct1.xd: Delete. * testsuite/ld-sh/sh64/crange-1.s: Delete. * testsuite/ld-sh/sh64/crange-2a.s: Delete. * testsuite/ld-sh/sh64/crange-2b.s: Delete. * testsuite/ld-sh/sh64/crange-2c.s: Delete. * testsuite/ld-sh/sh64/crange-2d.s: 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* testsuite/ld-sh/sh64/reldl32.rd: Delete. * testsuite/ld-sh/sh64/reldl64.rd: Delete. * testsuite/ld-sh/sh64/relfail.exp: Delete. * testsuite/ld-sh/sh64/relfail.s: Delete. * testsuite/ld-sh/sh64/sh64-1.s: Delete. * testsuite/ld-sh/sh64/sh64-2.s: Delete. * testsuite/ld-sh/sh64/sh64.exp: Delete. * testsuite/ld-sh/sh64/shcmp-1.s: Delete. * testsuite/ld-sh/sh64/shdl-1.s: Delete. * testsuite/ld-sh/sh64/shdl-2.s: Delete. * testsuite/ld-sh/sh64/shdl32.xd: Delete. * testsuite/ld-sh/sh64/shdl64.sd: Delete. * testsuite/ld-sh/sh64/shdl64.xd: Delete. * testsuite/ld-sh/sh64/shmix-1.s: Delete. * testsuite/ld-sh/sh64/shmix-2.s: Delete. * testsuite/ld-sh/sh64/shmix-3.s: Delete. * testsuite/ld-sh/sh64/stobin-0-dso.d: Delete. * testsuite/ld-sh/sh64/stobin-1.d: Delete. * testsuite/ld-sh/sh64/stobin.s: Delete. * testsuite/ld-sh/sh64/stolib.s: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-16 13:59:39 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove sh5 and sh64 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* sh-dis.c: Likewise.
* sh64-dis.c: Delete.
* sh64-opc.c: Delete.
* sh64-opc.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
Remove w65 support include/ * coff/internal.h: Remove w65 support. * coff/w65.h: Delete. bfd/ * Makefile.am: Remove w65 support. * archures.c: Likewise. * coffcode.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * coff-w65.c: Delete. * cpu-w65.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove w65 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * w65-dis.c: Delete. * w65-opc.h: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove w65 support. ld/ * Makefile.am: Remove w65 support. * configure.tgt: Likewise. * emulparams/w65.sh: Delete. * scripttempl/w65.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-16 13:56:05 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove w65 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* w65-dis.c: Delete.
* w65-opc.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
Remove we32k support include/ * coff/we32k.h: Delete. bfd/ * Makefile.am: Remove we32k support. * archures.c: Likewise. * coffcode.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * coff-we32k.c: Delete. * cpu-we32k.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * configure.ac: Remove we32k support. * configure: Regenerate. bintuils/ * testsuite/binutils-all/objdump.exp: Remove we32k support.
2018-04-16 13:54:43 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* configure.ac: Remove we32k support.
* configure: Regenerate.
Remove m88k support include/ * coff/internal.h: Remove m88k support. * coff/m88k.h: Delete. * opcode/m88k.h: Delete. bfd/ * Makefile.am: Remove m88k support. * aoutx.h: Likewise. * archures.c: Likewise. * coffcode.h: Likewise. * coffswap.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-ns32k.c: Likewise. * elf32-nds32.c: Likewise. * mach-o.c: Likewise. * netbsd-core.c: Likewise. * reloc.c: Likewise. * targets.c: Likewise. * coff-m88k.c: Delete. * cpu-m88k.c: Delete. * elf32-m88k.c: Delete. * hosts/m88kmach3.h: Delete. * m88kmach3.c: Delete. * m88kopenbsd.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove m88k support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * m88k-dis.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * MAINTAINERS (Mark Kettenis): Move to past maintainers. * testsuite/binutils-all/objdump.exp: Remove m88k support. gas/ * configure.ac: Remove m88k support. * config.in: Regenerate. * configure: Regenerate. ld/ * Makefile.am: Remove m88k support. * configure.host: Likewise. * configure.tgt: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * emulparams/m88kbcs.sh: Delete. * scripttempl/m88kbcs.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-16 13:53:38 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove m88k support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* m88k-dis.c: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
Remove i370 support include/ * elf/i370.h: Delete. * opcode/i370.h: Delete. bfd/ * Makefile.am: Remove i370 support. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * cpu-i370.c: Delete. * elf32-i370.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove i370 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * i370-dis.c: Delete. * i370-opc.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * readelf.c: Remove i370 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * Makefile.am: Remove i370 support. * app.c: Likewise. * config/obj-elf.c: Likewise. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Likewise. * testsuite/gas/elf/warn-2.s: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * config/tc-i370.c: Delete. * config/tc-i370.h: Delete. * doc/c-i370.texi: Delete. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am: Remove i370 support. * configure.tgt: Likewise. * testsuite/ld-elf/compressed1d.d: Likewise. * testsuite/ld-elf/group8a.d: Likewise. * testsuite/ld-elf/group8b.d: Likewise. * testsuite/ld-elf/group9a.d: Likewise. * testsuite/ld-elf/group9b.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/pr12851.d: Likewise. * testsuite/ld-elf/pr12975.d: Likewise. * testsuite/ld-elf/pr13177.d: Likewise. * testsuite/ld-elf/pr13195.d: Likewise. * testsuite/ld-elf/pr17615.d: Likewise. * testsuite/ld-elf/pr21562a.d: Likewise. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/pr22677.d: Likewise. * testsuite/lib/ld-lib.exp: Likewise. * emulparams/elf32i370.sh: Delete. * scripttempl/elfi370.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-16 13:51:56 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove i370 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* i370-dis.c: Delete.
* i370-opc.c: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
Remove h8500 support include/ * coff/h8500.h: Delete. * coff/internal.h: Remove h8500 support. bfd/ * Makefile.am: Remove h8500 support. * archures.c: Likewise. * coffcode.h: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * coff-h8500.c: Delete. * cpu-h8500.c: Delete. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * Makefile.am: Remove h8500 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * h8500-dis.c: Delete. * h8500-opc.h: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove h8500 support. * testsuite/lib/binutils-common.exp: Likewise. gas/ * config/obj-coff.h: Remove h8500 support. ld/ * Makefile.am: Remove h8500 support. * configure.tgt: Likewise. * emulparams/h8500.sh: Delete. * emulparams/h8500b.sh: Delete. * emulparams/h8500c.sh: Delete. * emulparams/h8500m.sh: Delete. * emulparams/h8500s.sh: Delete. * scripttempl/h8500.sc: Delete. * scripttempl/h8500b.sc: Delete. * scripttempl/h8500c.sc: Delete. * scripttempl/h8500m.sc: Delete. * scripttempl/h8500s.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-16 13:49:41 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove h8500 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* h8500-dis.c: Delete.
* h8500-opc.h: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
Remove tahoe support include/ * opcode/tahoe.h: Delete. bfd/ * archures.c: Remove tahoe support. * config.bfd: Likewise. * configure.ac: Likewise. * hosts/tahoe.h: Delete. * bfd-in2.h: Regenerate. * configure: Regenerate. opcodes/ * configure.ac: Remove tahoe support. * configure: Regenerate. binutils/ * testsuite/binutils-all/objdump.exp: Remove tahoe support. gprof/ * Makefile.am: Remove tahoe support. * corefile.c: Likewise. * tahoe.c: Delete. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2018-04-16 13:38:40 +08:00
2018-04-16 Alan Modra <amodra@gmail.com>
* configure.ac: Remove tahoe support.
* configure: Regenerate.
x86: Allow 32-bit registers for tpause and umwait Since only the first 32 bits of input operand are used for tpause and umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit registers are allowed. gas/ * testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers tests for tpause and umwait. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace Em with Edq on tpause and umwait. * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in 64-bit mode. * i386-tbl.h: Regenerated.
2018-04-15 23:38:23 +08:00
2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
umwait.
* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
64-bit mode.
* i386-tbl.h: Regenerated.
Enable Intel WAITPKG instructions. Intel has disclosed a set of new instructions for Tremont processor. The spec is https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference This patch enables Intel WAITPKG instructions. gas/ * config/tc-i386.c (cpu_arch): Add WAITPKG. (cpu_noarch): Likewise. * doc/c-i386.texi: Document WAITPKG. * i386/i386.exp: Run WAITPKG tests. * testsuite/gas/i386/waitpkg-intel.d: New test. * testsuite/gas/i386/waitpkg.d: Likewise. * testsuite/gas/i386/waitpkg.s: Likewise. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. * testsuite/gas/i386/x86-64-waitpkg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6, PREFIX_MOD_1_0FAE_REG_6. (va_mode): New. (OP_E_register): Use va_mode. * i386-dis-evex.h (prefix_table): New instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add WAITPKG. (cpu_flags): Likewise. * i386-opc.h (enum): Likewise. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add umonitor, umwait, tpause. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-04-09 18:58:50 +08:00
2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
PREFIX_MOD_1_0FAE_REG_6.
(va_mode): New.
(OP_E_register): Use va_mode.
* i386-dis-evex.h (prefix_table):
New instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add WAITPKG.
(cpu_flags): Likewise.
* i386-opc.h (enum): Likewise.
(i386_cpu_flags): Likewise.
* i386-opc.tbl: Add umonitor, umwait, tpause.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Remove i860, i960, bout and aout-adobe targets Plus remove a few leftovers from the 29k support. include/ * aout/adobe.h: Delete. * aout/reloc.h: Delete. * coff/i860.h: Delete. * coff/i960.h: Delete. * elf/i860.h: Delete. * elf/i960.h: Delete. * opcode/i860.h: Delete. * opcode/i960.h: Delete. * aout/aout64.h (enum reloc_type): Trim off 29k and other unused values. * aout/ar.h (ARMAGB): Remove. * coff/internal.h (struct internal_aouthdr, struct internal_scnhdr, union internal_auxent): Remove i960 support. bfd/ * aout-adobe.c: Delete. * bout.c: Delete. * coff-i860.c: Delete. * coff-i960.c: Delete. * cpu-i860.c: Delete. * cpu-i960.c: Delete. * elf32-i860.c: Delete. * elf32-i960.c: Delete. * hosts/i860mach3.h: Delete. * Makefile.am: Remove i860, i960, bout, and adobe support. * archures.c: Remove i860 and i960 support. * coffcode.h: Likewise. * reloc.c: Likewise. * aoutx.h: Comment updates. * archive.c: Remove BOUT and i960 support. * bfd.c: Remove BOUT support. * coffswap.h: Remove i960 support. * config.bfd: Remove i860, i960 and adobe targets. * configure.ac: Remove adode, bout, i860, i960, icoff targets. * targets.c: Likewise. * ieee.c: Remove i960 support. * mach-o.c: Remove i860 support. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * opcodes/i860-dis.c: Delete. * opcodes/i960-dis.c: Delete. * Makefile.am: Remove i860 and i960 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * ieee.c: Remove i960 support. * od-macho.c: Remove i860 support. * readelf.c: Remove i860 and i960 support. * testsuite/binutils-all/objcopy.exp: Likewise. * testsuite/binutils-all/objdump.exp: Likewise. * testsuite/lib/binutils-common.exp: Likewise. gas/ * config/aout_gnu.h: Delete. * config/tc-i860.c: Delete. * config/tc-i860.h: Delete. * config/tc-i960.c: Delete. * config/tc-i960.h: Delete. * doc/c-i860.texi: Delete. * doc/c-i960.texi: Delete. * testsuite/gas/i860/README.i860: Delete. * testsuite/gas/i860/bitwise.d: Delete. * testsuite/gas/i860/bitwise.s: Delete. * testsuite/gas/i860/branch.d: Delete. * testsuite/gas/i860/branch.s: Delete. * testsuite/gas/i860/bte.d: Delete. * testsuite/gas/i860/bte.s: Delete. * testsuite/gas/i860/dir-align01.d: Delete. * testsuite/gas/i860/dir-align01.s: Delete. * testsuite/gas/i860/dir-intel01.d: Delete. * testsuite/gas/i860/dir-intel01.s: Delete. * testsuite/gas/i860/dir-intel02.d: Delete. * testsuite/gas/i860/dir-intel02.s: Delete. * testsuite/gas/i860/dir-intel03-err.l: Delete. * testsuite/gas/i860/dir-intel03-err.s: Delete. * testsuite/gas/i860/dual01.d: Delete. * testsuite/gas/i860/dual01.s: Delete. * testsuite/gas/i860/dual02-err.l: Delete. * testsuite/gas/i860/dual02-err.s: Delete. * testsuite/gas/i860/dual03.d: Delete. * testsuite/gas/i860/dual03.s: Delete. * testsuite/gas/i860/fldst01.d: Delete. * testsuite/gas/i860/fldst01.s: Delete. * testsuite/gas/i860/fldst02.d: Delete. * testsuite/gas/i860/fldst02.s: Delete. * testsuite/gas/i860/fldst03.d: Delete. * testsuite/gas/i860/fldst03.s: Delete. * testsuite/gas/i860/fldst04.d: Delete. * testsuite/gas/i860/fldst04.s: Delete. * testsuite/gas/i860/fldst05.d: Delete. * testsuite/gas/i860/fldst05.s: Delete. * testsuite/gas/i860/fldst06.d: Delete. * testsuite/gas/i860/fldst06.s: Delete. * testsuite/gas/i860/fldst07.d: Delete. * testsuite/gas/i860/fldst07.s: Delete. * testsuite/gas/i860/fldst08.d: Delete. * testsuite/gas/i860/fldst08.s: Delete. * testsuite/gas/i860/float01.d: Delete. * testsuite/gas/i860/float01.s: Delete. * testsuite/gas/i860/float02.d: Delete. * testsuite/gas/i860/float02.s: Delete. * testsuite/gas/i860/float03.d: Delete. * testsuite/gas/i860/float03.s: Delete. * testsuite/gas/i860/float04.d: Delete. * testsuite/gas/i860/float04.s: Delete. * testsuite/gas/i860/form.d: Delete. * testsuite/gas/i860/form.s: Delete. * testsuite/gas/i860/i860.exp: Delete. * testsuite/gas/i860/iarith.d: Delete. * testsuite/gas/i860/iarith.s: Delete. * testsuite/gas/i860/ldst01.d: Delete. * testsuite/gas/i860/ldst01.s: Delete. * testsuite/gas/i860/ldst02.d: Delete. * testsuite/gas/i860/ldst02.s: Delete. * testsuite/gas/i860/ldst03.d: Delete. * testsuite/gas/i860/ldst03.s: Delete. * testsuite/gas/i860/ldst04.d: Delete. * testsuite/gas/i860/ldst04.s: Delete. * testsuite/gas/i860/ldst05.d: Delete. * testsuite/gas/i860/ldst05.s: Delete. * testsuite/gas/i860/ldst06.d: Delete. * testsuite/gas/i860/ldst06.s: Delete. * testsuite/gas/i860/pfam.d: Delete. * testsuite/gas/i860/pfam.s: Delete. * testsuite/gas/i860/pfmam.d: Delete. * testsuite/gas/i860/pfmam.s: Delete. * testsuite/gas/i860/pfmsm.d: Delete. * testsuite/gas/i860/pfmsm.s: Delete. * testsuite/gas/i860/pfsm.d: Delete. * testsuite/gas/i860/pfsm.s: Delete. * testsuite/gas/i860/pseudo-ops01.d: Delete. * testsuite/gas/i860/pseudo-ops01.s: Delete. * testsuite/gas/i860/regress01.d: Delete. * testsuite/gas/i860/regress01.s: Delete. * testsuite/gas/i860/shift.d: Delete. * testsuite/gas/i860/shift.s: Delete. * testsuite/gas/i860/simd.d: Delete. * testsuite/gas/i860/simd.s: Delete. * testsuite/gas/i860/system.d: Delete. * testsuite/gas/i860/system.s: Delete. * testsuite/gas/i860/xp.d: Delete. * testsuite/gas/i860/xp.s: Delete. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/all.texi: Likewise. * testsuite/gas/all/gas.exp * config/obj-coff.h: Remove i960 support. * doc/internals.texi: Likewise. * expr.c: Likewise. * read.c: Likewise. * write.c: Likewise. * write.h: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * testsuite/gas/symver/symver.exp: Likewise. * config/tc-m68k.c: Remove BOUT support. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sparc.c: Likewise. * symbols.c: Likewise. * doc/h8.texi: Likewise. * configure.ac: Remove BOUT and i860 support. * doc/as.texinfo: Remove BOUT, i860 and i960 support * Makefile.in: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * emulparams/coff_i860.sh: Delete. * emulparams/elf32_i860.sh: Delete. * emulparams/elf32_i960.sh: Delete. * emulparams/gld960.sh: Delete. * emulparams/gld960coff.sh: Delete. * emulparams/lnk960.sh: Delete. * emultempl/gld960.em: Delete. * emultempl/gld960c.em: Delete. * emultempl/lnk960.em: Delete. * scripttempl/i860coff.sc: Delete. * scripttempl/i960.sc: Delete. * ld.texinfo: Remove i960 support. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * testsuite/ld-discard/extern.d: Likewise. * testsuite/ld-discard/start.d: Likewise. * testsuite/ld-discard/static.d: Likewise. * testsuite/ld-elf/compressed1d.d: Likewise. * testsuite/ld-elf/group1.d: Likewise. * testsuite/ld-elf/group3b.d: Likewise. * testsuite/ld-elf/group8a.d: Likewise. * testsuite/ld-elf/group8b.d: Likewise. * testsuite/ld-elf/group9a.d: Likewise. * testsuite/ld-elf/group9b.d: Likewise. * testsuite/ld-elf/linkonce2.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise. * testsuite/ld-elf/orphan-10.d: Likewise. * testsuite/ld-elf/orphan-11.d: Likewise. * testsuite/ld-elf/orphan-12.d: Likewise. * testsuite/ld-elf/orphan-9.d: Likewise. * testsuite/ld-elf/orphan-region.d: Likewise. * testsuite/ld-elf/orphan.d: Likewise. * testsuite/ld-elf/orphan3.d: Likewise. * testsuite/ld-elf/pr12851.d: Likewise. * testsuite/ld-elf/pr12975.d: Likewise. * testsuite/ld-elf/pr13177.d: Likewise. * testsuite/ld-elf/pr13195.d: Likewise. * testsuite/ld-elf/pr17550a.d: Likewise. * testsuite/ld-elf/pr17550b.d: Likewise. * testsuite/ld-elf/pr17550c.d: Likewise. * testsuite/ld-elf/pr17550d.d: Likewise. * testsuite/ld-elf/pr17615.d: Likewise. * testsuite/ld-elf/pr20528a.d: Likewise. * testsuite/ld-elf/pr20528b.d: Likewise. * testsuite/ld-elf/pr21562a.d: Likewise. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/pr22677.d: Likewise. * testsuite/ld-elf/pr22836-1a.d: Likewise. * testsuite/ld-elf/pr22836-1b.d: Likewise. * testsuite/ld-elf/pr349.d: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-elf/warn1.d: Likewise. * testsuite/ld-elf/warn2.d: Likewise. * testsuite/ld-elf/warn3.d: Likewise. * testsuite/lib/ld-lib.exp: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-11 17:16:05 +08:00
2018-04-11 Alan Modra <amodra@gmail.com>
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
i386: Clear vex instead of vex.evex "vex" has many fields to control how to decode an instruction. Clear all fields in "vex" before decoding an instruction to avoid using values left from the previous instruction. gas/ PR binutils/23025 * testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with VEX and EVEX prefixes. * testsuite/gas/i386/prefix.d: Updated. opcodes/ PR binutils/23025 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w to 0. (print_insn): Clear vex instead of vex.evex.
2018-04-04 19:36:44 +08:00
2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/23025
* i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
to 0.
(print_insn): Clear vex instead of vex.evex.
Update Spanish translations for ld/ opcodes/ and gold/ sub-directories
2018-04-04 16:00:18 +08:00
2018-04-04 Nick Clifton <nickc@redhat.com>
* po/es.po: Updated Spanish translation.
x86: drop VecESize It again can be inferred from other information. The vpopcntd templates all need to have Dword added to their memory operands; the lack thereof was actually a bug preventing certain Intel syntax code to assemble, so test cases get extended.
2018-03-28 20:25:07 +08:00
2018-03-28 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Delete VecESize.
* i386-opc.h (VecESize): Delete.
(struct i386_opcode_modifier): Delete vecesize.
* i386-opc.tbl: Drop VecESize.
* i386-tlb.h: Re-generate.
x86: convert broadcast insn attribute to boolean The (only) valid broadcast type for an insn can be inferred from other information.
2018-03-28 20:24:05 +08:00
2018-03-28 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
BROADCAST_1TO4, BROADCAST_1TO2): Delete.
(struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
* i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
* i386-tlb.h: Re-generate.
x86: fold to-scalar-int conversion insns
2018-03-28 20:22:56 +08:00
2018-03-28 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
Fold AVX512 forms
* i386-tlb.h: Re-generate.
x86: don't show suffixes for to-scalar-int conversion insns In the course of folding their patterns (possible now that the pointless and partly even bogus VecESize are no longer in the way) I've noticed that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for any suffixes. As that is supposedly intentional, make the disassembler consistently omit suffixes for all to-scalar-int conversion insns.
2018-03-28 20:22:00 +08:00
2018-03-28 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (prefix_table): Drop Y for cvt*2si.
(vex_len_table): Drop Y for vcvt*2si.
(putop): Replace plain 'Y' handling by abort().
Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register. PR 22988 opcode * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_SVE_ADDR_R. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx instructions with only a base address register. * aarch64-opc.c (operand_general_constraint_met_p): Add code to handle AARHC64_OPND_SVE_ADDR_R. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64_dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * config/tc-aarch64.c (parse_operands): Add code to handle AARCH64_OPN_SVE_ADDR_R. * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions with an assumed XZR offset address register. * testsuite/gas/aarch64/sve.d: Update expected disassembly.
2018-03-28 16:44:45 +08:00
2018-03-28 Nick Clifton <nickc@redhat.com>
PR 22988
* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
instructions with only a base address register.
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
handle AARHC64_OPND_SVE_ADDR_R.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64_dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
x86: drop pointless VecESize The attribute is meaningful only in templates allowing embedded broadcast. Drop them everywhere else.
2018-03-22 15:46:25 +08:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Drop VecESize from register only insn forms and
memory forms not allowing broadcast.
* i386-tlb.h: Re-generate.
x86: drop remaining redundant DispN A few of them were missed in commit 7ac2002247 ("x86: derive DispN from BaseIndex") and also couldn't be removed by subsequent commits touching certain templates anyway.
2018-03-22 15:34:24 +08:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
sha256*): Drop Disp<N>.
x86: fix swapped operand handling for BNDMOV The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns.
2018-03-22 15:32:50 +08:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EbndS, bnd_swap_mode): New.
(prefix_table): Use EbndS.
(OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
* i386-opc.tbl (bndmov): Move misplaced Load.
* i386-tlb.h: Re-generate.
x86/Intel: fix fallout from earlier template folding While many templates allowing multiple suitably matching XMM/YMM/ZMM operand sizes can be folded, a few need to be split in order to not wrongly accept "xmmword ptr" operands when only XMM registers are permitted (and memory operands are more narrow). Add a test case validating this.
2018-03-22 15:31:43 +08:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
templates allowing memory operands and folded ones for register
only flavors.
* i386-tlb.h: Re-generate.
x86: fold a few XOP templates Also add a new test case verifying that mixed operands of SIMD insns with a size-less memory operand in the middle are properly rejected.
2018-03-22 15:29:45 +08:00
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
256-bit templates. Drop redundant leftover Disp<N>.
* i386-tlb.h: Re-generate.
RISC-V: Add .insn support. gas/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * config/tc-riscv.c (opcode_name_list): New. (opcode_names_hash): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (validate_riscv_insn): New argument length, and add new format which used in .insn directive. (md_begin): Refine hash table initialization logic into init_opcode_hash. (init_opcode_hash): New. (my_getOpcodeExpression): Parse opcode name for .insn. (riscv_ip): New argument hash, able to handle .insn directive. (s_riscv_insn): Handler for .insn directive. (riscv_pseudo_table): New entry for .insn. * doc/c-riscv.texi: Add documentation for .insn directive. * testsuite/gas/riscv/insn.d: Add testcase for .insn directive. * testsuite/gas/riscv/insn.s: Likewise. include/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * opcode/riscv.h (OP_MASK_FUNCT3): New. (OP_SH_FUNCT3): Likewise. (OP_MASK_FUNCT7): Likewise. (OP_SH_FUNCT7): Likewise. (OP_MASK_OP2): Likewise. (OP_SH_OP2): Likewise. (OP_MASK_CFUNCT4): Likewise. (OP_SH_CFUNCT4): Likewise. (OP_MASK_CFUNCT3): Likewise. (OP_SH_CFUNCT3): Likewise. (riscv_insn_types): Likewise. opcodes/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_insn_types): New.
2018-03-15 07:04:03 +08:00
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_insn_types): New.
Updated Russian and Brazilian Portuguese translations. ld * po/pt_BR.po: Updated Brazilian Portuguese translation. opcodes * po/pt_BR.po: Updated Brazilian Portuguese translation. gas * po/ru.po: Updated Russian translation.
2018-03-14 00:57:29 +08:00
2018-03-13 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portuguese translation.
x86-64: Also optimize "clr reg64" "clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as "xor reg32, reg32". gas/ * config/tc-i386.c (optimize_encoding): Also encode "clr reg64" as "xor reg32, reg32". * testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests. * testsuite/gas/i386/x86-64-optimize-1.d: Updated. opcodes/ * i386-opc.tbl: Add Optimize to clr. * i386-tbl.h: Regenerated.
2018-03-08 22:41:34 +08:00
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add Optimize to clr.
* i386-tbl.h: Regenerated.
x86: Remove support for old (<= 2.8.1) versions of gcc Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and fdivrp instructions. Assembler translates them to correct ones with a warning: [hjl@gnu-cfl-1 gas]$ cat x.s fsubp %st(3),%st [hjl@gnu-cfl-1 gas]$ gcc -c x.s x.s: Assembler messages: x.s:1: Warning: translating to `fsubp %st,%st(3)' [hjl@gnu-cfl-1 gas]$ This patch removes support for old (<= 2.8.1) versions of gcc: [hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s x.s: Assembler messages: x.s:1: Error: operand type mismatch for `fsubp' [hjl@gnu-cfl-1 gas]$ gas/ * NEWS: Mention -mold-gcc removal. * config/tc-i386.c (i386_error): Remove old_gcc_only. (old_gcc): Removed. (match_template): Remove old gcc support. (OPTION_MOLD_GCC): Removed. (OPTION_MRELAX_RELOCATIONS): Updated. (md_longopts): Remove OPTION_MOLD_GCC. (md_parse_option): Likewise. (md_show_usage): Remove -mold-gcc. * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old (<= 2.8.1) versions of gcc. * testsuite/gas/i386/intel.s: Likewise. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intel.e: Likewise. * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general. include/ * opcode/i386 (OLDGCC_COMPAT): Removed. opcodes/ * i386-gen.c (opcode_modifiers): Remove OldGcc. * i386-opc.h (OldGcc): Removed. (i386_opcode_modifier): Remove oldgcc. * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp instructions for old (<= 2.8.1) versions of gcc. * i386-tbl.h: Regenerated.
2018-03-08 22:31:32 +08:00
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove OldGcc.
* i386-opc.h (OldGcc): Removed.
(i386_opcode_modifier): Remove oldgcc.
* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
instructions for old (<= 2.8.1) versions of gcc.
* i386-tbl.h: Regenerated.
x86: fold several AVX512VL templates The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold these as far as possible, and also fold register-only forms. Further folding is possible, but needs other prereq work done first. A note regarding EVEXDYN: This is intended to be used only when no other properties of the template would make is_evex_encoding() return true. In all "normal" cases I think it is preferable to omit this indicator, to keep the table half way readable.
2018-03-08 15:58:55 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (EVEXDYN): New.
* i386-opc.tbl: Fold various AVX512VL templates.
* i386-tlb.h: Re-generate.
x86: fold certain AVX512 rotate and shift templates Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust VexNDD handling to cope with these, allowing their register and memory forms to be folded.
2018-03-08 15:58:05 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
vpexpandd, vpexpandq): Fold AFX512VF templates.
* i386-tlb.h: Re-generate.
x86: fold VEX-encoded GFNI templates
2018-03-08 15:57:19 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
Fold 128- and 256-bit VEX-encoded templates.
* i386-tlb.h: Re-generate.
x86: fold a few AVX512F templates The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold them as far as possible. Further folding is possible, but needs other prereq work done first.
2018-03-08 15:56:47 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
vpexpandd, vpexpandq): Fold AVX512F templates.
* i386-tlb.h: Re-generate.
x86: fold LWP templates Also drop the no longer necessary explicit Disp<N> from them.
2018-03-08 15:56:08 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
64-bit templates. Drop Disp<N>.
* i386-tlb.h: Re-generate.
x86: fold FMA and FMA4 templates
2018-03-08 15:55:37 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
and 256-bit templates.
* i386-tlb.h: Re-generate.
x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIX They aren't really useful (anymore?): The conflicting operand size check isn't applicable to any insn validly using respective memory operand sizes (and if they're used wrongly, another error would result), and the logic in process_suffix() can be easily changed to work without them. While re-structuring conditionals in process_suffix() also drop the CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode table.
2018-03-08 15:52:27 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (cmpxchg8b): Add NoRex64.
* i386-tlb.h: Re-generate.
x86: drop bogus NoAVX These are meaningful only for insns with CpuSSE* (and a few other Cpu*) attribute.
2018-03-08 15:36:41 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
Drop NoAVX.
* i386-tlb.h: Re-generate.
x86: avoid SSE check for LDMXCSR/STMXCSR Neither touches any XMM register, so the check is pointless. It is imo even questionable whether in SSE2AVX mode the two should be converted to their AVX counterparts.
2018-03-08 15:35:48 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
* i386-tlb.h: Re-generate.
x86: drop FloatD It can be expressed by D, when making the consumer look at operand size to tell apart both uses.
2018-03-08 15:34:09 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Delete FloatD.
* i386-opc.h (FloatD): Delete.
(struct i386_opcode_modifier): Delete floatd.
* i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
FloatD by D.
* i386-tlb.h: Re-generate.
x86/Intel: correct disassembly of fsub*/fdiv* fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning).
2018-03-08 15:33:06 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
x86: bogus VMOVD with 64-bit operands should only allow for registers These templates exist solely to satisfy gcc's needs, and gcc only produces these with register operands.
2018-03-08 15:26:35 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vmovd): Disallow Qword memory operands.
* i386-tlb.h: Re-generate.
x86: fold AVX vcvtpd2ps memory forms This requires a change to ModR/M handling: Recording of displacement types must not discard operand size information. Change the respective code to alter only .disp<N>.
2018-03-08 15:25:31 +08:00
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
forms.
* i386-tlb.h: Re-generate.
XCOFF disassembler xcoff (32-bit) objdump accepted but ignored -M options unless -mpowerpc was also given. This patch fixes that, leaving the default as -Mpwr for xcoff. I've also enabled more tests for xcoff targets. binutils/ * configure.ac: Add objdump_private_desc_xcoff for rs6000. * configure: Regenerate. gas/ * testsuite/gas/ppc/aix.exp: Run for rs6000 too. * testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets. * testsuite/gas/ppc/machine.d: Don't run for PE targets. opcodes/ * disassemble.c (disassembler): Use bfd_arch_powerpc entry for bfd_arch_rs6000. * disassemble.h (print_insn_rs6000): Delete. * ppc-dis.c (powerpc_init_dialect): Handle rs6000. (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. (print_insn_rs6000): Delete.
2018-03-07 08:36:15 +08:00
2018-03-07 Alan Modra <amodra@gmail.com>
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
bfd_arch_rs6000.
* disassemble.h (print_insn_rs6000): Delete.
* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
(print_insn_rs6000): Delete.
opcodes error messages Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-02 05:53:50 +08:00
2018-03-03 Alan Modra <amodra@gmail.com>
* sysdep.h (opcodes_error_handler): Define.
(_bfd_error_handler): Declare.
* Makefile.am: Remove stray #.
* opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
EDIT" comment.
* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
opcodes_error_handler to print errors. Standardize error messages.
* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
and include opintl.h.
* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
* i386-gen.c: Standardize error messages.
* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
* Makefile.in: Regenerate.
* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128 When 2 source registers are identical, AVX256 and AVX512 vpsub[bwdq] instructions can be encoded with VEX128 or EVEX128 encodings. gas/ * config/tc-i386.c (optimize_encoding): Optimize AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. opcodes/ * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 vpsub[bwdq] instructions. * i386-tbl.h: Regenerated.
2018-03-01 22:08:04 +08:00
2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
* * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
vpsub[bwdq] instructions.
* i386-tbl.h: Regenerated.
Add missing translations to ALL_LINGUAS binutils/ * configure.ac (ALL_LINGUAS): Add sr. Sort. * configure: Regenerate. gas/ * configure.ac (ALL_LINGUAS): Add uk. Sort. * configure: Regenerate. gprof/ * configure.ac (ALL_LINGUAS): Add it, ro, ru, uk. Sort. * configure: Regenerate. ld/ * configure.ac (ALL_LINGUAS): Add ja. Sort. * configure: Regenerate. opcodes/ * configure.ac (ALL_LINGUAS): Sort. * configure: Regenerate.
2018-03-01 05:56:51 +08:00
2018-03-01 Alan Modra <amodra@gmail.com>
* configure.ac (ALL_LINGUAS): Sort.
* configure: Regenerate.
[ARM] Remove ARM_FEATURE_COPY macro Among the macros to manipulate an arm_feature_set structure is the ARM_FEATURE_COPY which copy the value of a feature set into another. This can be achieved with a simple assignement which most of the existing code does. This patch removes the last 2 uses of that macro and remove the macro altogether. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> include/ * opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY macro by assignements.
2018-02-28 00:40:45 +08:00
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
macro by assignements.
x86: Add -O[2|s] assembler command-line options On x86, some instructions have alternate shorter encodings: 1. When the upper 32 bits of destination registers of andq $imm31, %r64 testq $imm31, %r64 xorq %r64, %r64 subq %r64, %r64 known to be zero, we can encode them without the REX_W bit: andl $imm31, %r32 testl $imm31, %r32 xorl %r32, %r32 subl %r32, %r32 This optimization is enabled with -O, -O2 and -Os. 2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit immediate to 64-bit destination register, we can use it to encode 64-bit mov with 32-bit immediates. This optimization is enabled with -O, -O2 and -Os. 3. Since the upper bits of destination registers of VEX128 and EVEX128 instructions are extended to zero, if all bits of destination registers of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128 encoding to encode AVX256 or AVX512 instructions. When 2 source registers are identical, AVX256 and AVX512 andn and xor instructions: VOP %reg, %reg, %dest_reg can be encoded with VOP128 %reg, %reg, %dest_reg This optimization is enabled with -O2 and -Os. 4. 16-bit, 32-bit and 64-bit register tests with immediate may be encoded as 8-bit register test with immediate. This optimization is enabled with -Os. This patch does: 1. Add {nooptimize} pseudo prefix to disable instruction size optimization. 2. Add optimize to i386_opcode_modifier to tell assembler that encoding of an instruction may be optimized. gas/ PR gas/22871 * NEWS: Mention -O[2|s]. * config/tc-i386.c (_i386_insn): Add no_optimize. (optimize): New. (optimize_for_space): Likewise. (fits_in_imm7): New function. (fits_in_imm31): Likewise. (optimize_encoding): Likewise. (md_assemble): Call optimize_encoding to optimize encoding. (parse_insn): Handle {nooptimize}. (md_shortopts): Append "O::". (md_parse_option): Handle -On. * doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well as {nooptimize}. * testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler. * testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2, optimize-3, x86-64-optimize-1, x86-64-optimize-2, x86-64-optimize-3 and x86-64-optimize-4. * testsuite/gas/i386/optimize-1.d: New file. * testsuite/gas/i386/optimize-1.s: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. opcodes/ PR gas/22871 * i386-gen.c (opcode_modifiers): Add Optimize. * i386-opc.h (Optimize): New enum. (i386_opcode_modifier): Add optimize. * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, vpxord and vpxorq. * i386-tbl.h: Regenerated.
2018-02-27 23:36:33 +08:00
2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
crx string overflow warning gcc8 complains wrongly about the buffer not being large enough, at least at -Og optimization. * crx-dis.c (getregliststring): Allocate a large enough buffer to silence false positive gcc8 warning.
2018-02-24 08:03:33 +08:00
2018-02-26 Alan Modra <amodra@gmail.com>
* crx-dis.c (getregliststring): Allocate a large enough buffer
to silence false positive gcc8 warning.
RISC-V: Make disassebler work for --enable-targets=all config. opcodes/ * disassemble.c (ARCH_riscv): Define if ARCH_all.
2018-02-23 03:28:51 +08:00
2018-02-22 Shea Levy <shea@shealevy.com>
* disassemble.c (ARCH_riscv): Define if ARCH_all.
x86: Add {rex} pseudo prefix Add {rex} pseudo prefix to generate a REX byte for integer and legacy vector instructions if possible. Note that this differs from the rex prefix which generates REX prefix unconditionally. gas/ * config/tc-i386.c (_i386_insn): Add rex_encoding. (md_assemble): When i.rex_encoding is true, generate a REX byte if possible. (parse_insn): Set i.rex_encoding for {rex}. * doc/c-i386.texi: Document {rex}. * testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests. * testsuite/gas/i386/x86-64-pseudos.d: Updated. opcodes/ * i386-opc.tbl: Add {rex}, * i386-tbl.h: Regenerated.
2018-02-22 22:18:27 +08:00
2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add {rex},
* i386-tbl.h: Regenerated.
MIPS16/opcodes: Free up `M' operand code The `M' and `m' MIPS16 operand codes are functionally the same, denoting a 7-bit register list that is encoded the same way for both SAVE and RESTORE. Use `m' for both instructions then, making `M' available for a different use. opcodes/ * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. (mips16_opcodes): Replace `M' with `m' for "restore". include/ * opcode/mips.h: Remove `M' operand code.
2018-02-21 04:51:36 +08:00
2018-02-20 Maciej W. Rozycki <macro@mips.com>
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
(mips16_opcodes): Replace `M' with `m' for "restore".
[ARM] Fix bxns mask Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is not set in the disassembler entry mask. This commit fixes that. 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2018-02-19 20:05:18 +08:00
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Fix BXNS mask.
WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCC Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../bfd/wasm-module.c: In function 'wasm_scan_name_function_section': .../bfd/wasm-module.c:312: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here .../bfd/wasm-module.c: In function 'wasm_register_section': .../bfd/wasm-module.c:494: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here .../bfd/wasm-module.c: In function 'wasm_compute_custom_section_file_position': .../bfd/wasm-module.c:523: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here and: cc1: warnings being treated as errors .../opcodes/wasm32-dis.c: In function 'print_insn_wasm32': .../opcodes/wasm32-dis.c:272: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[4]: *** [wasm32-dis.lo] Error 1 which for versions of GCC before 4.8 prevent support for the WebAssembly target from being built. See also GCC PR c/53066. bfd/ * wasm-module.c (wasm_scan_name_function_section): Rename `index' local variable to `idx'. opcodes/ * wasm32-dis.c (print_insn_wasm32): Rename `index' local variable to `function_index'.
2018-02-13 20:56:29 +08:00
2018-02-13 Maciej W. Rozycki <macro@mips.com>
* wasm32-dis.c (print_insn_wasm32): Rename `index' local
variable to `function_index'.
Fix compile time warning messages from gcc version 8 about cast between incompatible function types. PR 22823 bfd Fix compile time warnings generated by gcc version 8. * libbfd-in.h: Remove extraneous text from prototypes. Add prototypes for bfd_false_any, bfd_true_any, bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any, bfd_n1_any, bfd_void_any. (_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy function. (_bfd_generic_bfd_merge_private_bfd_data): Likewise. (_bfd_generic_bfd_set_private_flags): Likewise. (_bfd_generic_bfd_copy_private_section_data): Likewise. (_bfd_generic_bfd_copy_private_symbol_data): Likewise. (_bfd_generic_bfd_copy_private_header_data): Likewise. (_bfd_generic_bfd_print_private_bfd_data): Likewise. (_bfd_noarchive_construct_extended_name_table): Likewise. (_bfd_noarchive_truncate_arname): Likewise. (_bfd_noarchive_write_ar_hdr): Likewise. (_bfd_noarchive_get_elt_at_index): Likewise. (_bfd_nosymbols_canonicalize_symtab): Likewise. (_bfd_nosymbols_print_symbol): Likewise. (_bfd_nosymbols_get_symbol_info): Likewise. (_bfd_nosymbols_get_symbol_version_string): Likewise. (_bfd_nosymbols_bfd_is_local_label_name): Likewise. (_bfd_nosymbols_bfd_is_target_special_symbol): Likewise. (_bfd_nosymbols_get_lineno): Likewise. (_bfd_nosymbols_find_nearest_line): Likewise. (_bfd_nosymbols_find_line): Likewise. (_bfd_nosymbols_find_inliner_info): Likewise. (_bfd_nosymbols_bfd_make_debug_symbol): Likewise. (_bfd_nosymbols_read_minisymbols): Likewise. (_bfd_nosymbols_minisymbol_to_symbol): Likewise. (_bfd_norelocs_bfd_reloc_type_lookup): Likewise. (_bfd_norelocs_bfd_reloc_name_lookup): Likewise. (_bfd_nowrite_set_arch_mach): Likewise. (_bfd_nowrite_set_section_contents): Likewise. (_bfd_nolink_sizeof_headers): Likewise. (_bfd_nolink_bfd_get_relocated_section_contents): Likewise. (_bfd_nolink_bfd_relax_section): Likewise. (_bfd_nolink_bfd_gc_sections): Likewise. (_bfd_nolink_bfd_lookup_section_flags): Likewise. (_bfd_nolink_bfd_merge_sections): Likewise. (_bfd_nolink_bfd_is_group_section): Likewise. (_bfd_nolink_bfd_discard_group): Likewise. (_bfd_nolink_bfd_link_hash_table_create): Likewise. (_bfd_nolink_bfd_link_add_symbols): Likewise. (_bfd_nolink_bfd_link_just_syms): Likewise. (_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise. (_bfd_nolink_bfd_final_link): Likewise. (_bfd_nolink_bfd_link_split_section): Likewise. (_bfd_nolink_section_already_linked): Likewise. (_bfd_nolink_bfd_define_common_symbol): Likewise. (_bfd_nolink_bfd_define_start_stop): Likewise. (_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise. (_bfd_nodynamic_get_synthetic_symtab): Likewise. (_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise. (_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise. * libbfd.c (bfd_false_any): New function. Like bfd_false but accepts one or more arguments. (bfd_true_any): Likewise. (bfd_nullvoidptr_any): Likewise. (bfd_0_any): Likewise. (bfd_0u_any): Likewise. (bfd_0l_any): Likewise. (_bfd_n1_any): Likewise. (bfd_void_any): Likewise. * libbfd.h (extern): Regenerate * aout-target.h (MY_bfd_is_target_special_symbol): Use vararg based dummy function. * aout-tic30.c (tic30_aout_set_arch_mach): Likewise. * binary.c (binary_get_symbol_info): Likewise. * coff-alpha.c (alpha_ecoff_backend_data): Likewise. * coff-mips.c (mips_ecoff_backend_data): Likewise. * coffcode.h (coff_set_alignment_hook): Likewise. (symname_in_debug_hook): Likewise. (bfd_coff_backend_data bigobj_swap_table): Likewise. * elf-m10300.c (elf_backend_omit_section_dynsym): Likewise. * elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise. * elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise. * elf32-metag.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score7.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise. * elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise. * elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise. * elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise. * elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise. * elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise. (bfd_elfNN_bfd_make_debug_symbol): Likewise. (bfd_elfNN_bfd_merge_private_bfd_data): Likewise. (bfd_elfNN_bfd_set_private_flags): Likewise. (bfd_elfNN_bfd_is_target_special_symbol): Likewise. (elf_backend_init_index_section): Likewise. (elf_backend_allow_non_load_phdr): Likewise. * elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise. * i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise. * ieee.c (ieee_construct_extended_name_table): Likewise. (ieee_write_armap): Likewise. (ieee_write_ar_hdr): Likewise. (ieee_bfd_is_target_special_symbol): Likewise. * ihex.c (ihex_canonicalize_symtab): Likewise. (ihex_bfd_is_target_special_symbol): Likewise. * libaout.h (aout_32_bfd_is_target_special_symbol): Likewise. * libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise. (_bfd_ecoff_set_alignment_hook): Likewise. * mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise. * mmo.c (mmo_bfd_is_target_special_symbol): Likewise. * nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise. * oasys.c (oasys_construct_extended_name_table): Likewise. (oasys_write_armap): Likewise. (oasys_write_ar_hdr): Likewise. (oasys_bfd_is_target_special_symbol): Likewise. * pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise. * plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise. * ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise. * som.c (som_bfd_is_target_special_symbol): Likewise. * srec.c (srec_bfd_is_target_special_symbol): Likewise. * tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise. * verilog.c (verilog_bfd_is_target_special_symbol): Likewise. * versados.c (versados_bfd_is_target_special_symbol): Likewise. (versados_bfd_reloc_name_lookup): Likewise. * vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise. (vms_bfd_define_start_stop): Likewise. (alpha_vms_bfd_is_target_special_symbol): Likewise. * wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise. * xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise. * elf32-arc.c (get_replace_function): Assign replacement function to func pointer. * elf32-i370.c (i370_noop): Update prototype. gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant casts. (obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit. (obj_elf_vtable_inherit): New stub function that calls obj_elf_get_vtable_inherit. (obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry. (obj_elf_vtable_entry): New stub function that calls obj_elf_get_vtable_entry. * config/obj-elf.h (obj_elf_vtable_inherit): Update prototype. (obj_elf_vtable_entry) Likewise. (obj_elf_get_vtable_inherit) Likewise. (obj_elf_get_vtable_entry) Likewise. * config/tc-arm.c (md_pseudo_table): Remove now redundant cast. * config/tc-i386c (md_pseudo_table): Likewise. * config/tc-hppa.c (pa_vtable_entry): Call obj_elf_get_vtable_entry. (pa_vtable_inherit): Call obj_elf_get_vtable_inherit. * config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file with call to dwarf2_get_filename. * dwarf2dbg.c (dwarf2_directive_file): Rename to dwarf2_directive_filename. (dwarf2_directive_file): New stub function that calls dwarf2_directive_filename. * dwarf2dbg.h: Prototype dwarf2_directive_filename. opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning about truncation of printing.
2018-02-13 21:14:47 +08:00
2018-02-13 Nick Clifton <nickc@redhat.com>
PR 22823
* metag-dis.c (print_fmmov): Double buffer size to avoid warning
about truncation of printing.
MIPS: Fix encoding for MIPSr6 sigrie instruction. The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-12 22:50:42 +08:00
2018-02-12 Henry Wong <henry@stuffedcow.net>
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
Updated Brazillian portuguese and Russian translation
2018-02-05 21:09:15 +08:00
2018-02-05 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portuguese translation.
Enable Intel PCONFIG instruction. Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-24 00:56:30 +08:00
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add pconfig.
* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
(cpu_flags): Add CpuPCONFIG.
* i386-opc.h (enum): Add CpuPCONFIG.
(i386_cpu_flags): Add cpupconfig.
* i386-opc.tbl: Add PCONFIG instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Enable Intel WBNOINVD instruction. Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-24 00:39:05 +08:00
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
RISC-V: Fix bug in prior addi/c.nop patch. gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2018-01-18 06:04:16 +08:00
2018-01-17 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
Replace CET bit with IBT and SHSTK bits. The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-18 00:45:52 +08:00
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Update translations for various binutils components. ld * po/pt_BR.po: Updated Brazilian Portugese translation. opcodes * po/pt_BR.po: Updated Brazilian Portugese translation. * po/de.po: Updated German translation. gas * po/fr.po: Updated French translation. binutils* po/fr.po: Updated French translation.
2018-01-16 20:45:44 +08:00
2018-01-16 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portugese translation.
* po/de.po: Updated German translation.
RISC-V: Add support for addi that compresses to c.nop. gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-16 06:53:44 +08:00
2018-01-15 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes
2018-01-15 20:09:11 +08:00
2018-01-15 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Update pot files
2018-01-13 21:56:48 +08:00
2018-01-13 Nick Clifton <nickc@redhat.com>
* po/opcodes.pot: Regenerated.
Bump version number to 2.30.51 bfd/ * version.m4: Bump version to 2.30.51 * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2018-01-13 21:31:12 +08:00
2018-01-13 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
Add note about 2.30 branch creation to changelogs
2018-01-13 21:26:38 +08:00
2018-01-13 Nick Clifton <nickc@redhat.com>
2.30 branch created.
Remove VL variants for 4FMAPS and 4VNNIW insns. AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-11 07:56:45 +08:00
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
* i386-tbl.h: Regenerate.
x86: fix Disp8 handling for scalar AVX512_4FMAPS insns Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10 21:53:43 +08:00
2018-01-10 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
* i386-tbl.h: Re-generate.
x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-10 21:53:05 +08:00
2018-01-10 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
Disp8MemShift of AVX512VL forms.
* i386-tbl.h: Re-generate.
RISC-V: Disassemble x0 based addresses as 0. gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-10 08:40:06 +08:00
2018-01-09 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
[Arm] Add CSDB instruction CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09 22:15:00 +08:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
Add support for the AArch64's CSDB instruction. CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-09 19:28:04 +08:00
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
x86: Properly encode vmovd with 64-bit memeory For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-08 20:36:59 +08:00
2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22681
* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
Remove AVX512 vmovd with 64-bit operands.
* i386-tbl.h: Regenerated.
RISC-V: Print symbol address for jalr w/ zero offset. ld/ * testsuite/ld-riscv-elf/disas-jalr.d: New. * testsuite/ld-riscv-elf/disas-jalr.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase. opcodes/ * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a jalr.
2018-01-06 09:51:23 +08:00
2018-01-05 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
jalr.
Update year range in copyright notice of binutils files
2018-01-03 13:17:27 +08:00
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
x86: partial revert of 10c17abdd0 Other than the variables in tc-i386.c using them, OPERAND_TYPE_REGYMM and OPERAND_TYPE_REGZMM they aren't entirely unused. No need to update i386-init.h though, as it mistakenly wasn't updated by the original commit.
2018-01-02 18:44:04 +08:00
2018-01-02 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
and OPERAND_TYPE_REGZMM entries.
ChangeLog rotation
2018-01-03 13:15:17 +08:00
For older changes see ChangeLog-2017
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2018-01-03 13:15:17 +08:00
Copyright (C) 2018 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
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