2017-03-01 02:32:07 +08:00
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2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
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* dis-asm.h (disasm_options_t): New typedef.
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(parse_arm_disassembler_option): Remove prototype.
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(set_arm_regname_option): Likewise.
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(get_arm_regnames): Likewise.
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(get_arm_regname_num_options): Likewise.
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(disassemble_init_s390): New prototype.
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(disassembler_options_powerpc): Likewise.
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(disassembler_options_arm): Likewise.
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(disassembler_options_s390): Likewise.
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(remove_whitespace_and_extra_commas): Likewise.
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(disassembler_options_cmp): Likewise.
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(next_disassembler_option): New inline function.
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(FOR_EACH_DISASSEMBLER_OPTION): New macro.
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2017-02-28 06:02:36 +08:00
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2017-02-28 Alan Modra <amodra@gmail.com>
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* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
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* elf/ppc.h (R_PPC_16DX_HA): Likewise.
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[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
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(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
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(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
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(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
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2017-02-25 02:27:26 +08:00
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
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(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
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2017-02-23 13:23:05 +08:00
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2017-02-22 Andrew Waterman <andrew@sifive.com>
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* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
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(CSR_MCOUNTEREN): Likewise.
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(scounteren): Declare register.
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(mcounteren): Likewise.
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2017-02-15 07:37:04 +08:00
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2017-02-14 Andrew Waterman <andrew@sifive.com>
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* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
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(MASK_SFENCE_VMA): Likewise.
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(sfence_vma): Declare instruction.
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2017-02-14 18:08:21 +08:00
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2017-02-14 Alan Modra <amodra@gmail.com>
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PR 21118
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* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
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(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
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2017-01-25 20:19:27 +08:00
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2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
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* opcode/hppa.h: Clarify that file is part of GNU opcodes.
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* opcode/i860.h: Ditto.
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* opcode/nios2.h: Ditto.
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* opcode/nios2r1.h: Ditto.
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* opcode/nios2r2.h: Ditto.
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* opcode/pru.h: Ditto.
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2017-01-25 20:24:02 +08:00
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2017-01-24 Alan Hayward <alan.hayward@arm.com>
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2017-01-24 18:37:13 +08:00
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* elf/common.h (NT_ARM_SVE): Define.
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2017-01-04 22:27:52 +08:00
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2017-01-04 Jiong Wang <jiong.wang@arm.com>
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* dwarf2.def: Sync with mainline gcc sources.
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2017-01-04 Richard Earnshaw <rearnsha@arm.com>
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Jiong Wang <jiong.wang@arm.com>
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* dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea.
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(DW_CFA_GNU_window_save): Comments the multiplexing on AArch64.
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2017-01-04 20:27:10 +08:00
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
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(AARCH64_ARCH_V8_3): Update.
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2017-01-04 01:42:01 +08:00
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* opcode/riscv-opc.h: Add support for the "q" ISA extension.
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2017-01-03 23:17:48 +08:00
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2017-01-03 Nick Clifton <nickc@redhat.com>
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* dwarf2.def: Sync with mainline gcc sources
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* dwarf2.h: Likewise.
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2016-12-21 Jakub Jelinek <jakub@redhat.com>
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* dwarf2.def (DW_FORM_ref_sup): Renamed to ...
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(DW_FORM_ref_sup4): ... this. New form.
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(DW_FORM_ref_sup8): New form.
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2016-10-17 Jakub Jelinek <jakub@redhat.com>
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* dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
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calling convention codes.
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(enum dwarf_line_number_content_type): New.
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(enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
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codes.
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(enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
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(enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
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(enum dwarf_name_index_attribute): New.
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(enum dwarf_range_list_entry): New.
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(enum dwarf_unit_type): New.
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* dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
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DW_OP_* and DW_ATE_* entries.
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2016-08-15 Jakub Jelinek <jakub@redhat.com>
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* dwarf2.def (DW_AT_string_length_bit_size,
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DW_AT_string_length_byte_size): New attributes.
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2016-08-12 Alexandre Oliva <aoliva@redhat.com>
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PR debug/63240
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* dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
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* dwarf2.h (enum dwarf_defaulted_attribute): New.
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2017-01-02 11:36:43 +08:00
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2017-01-02 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2017-01-02 11:25:05 +08:00
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For older changes see ChangeLog-2016
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2016-01-01 18:44:31 +08:00
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2017-01-02 11:25:05 +08:00
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Copyright (C) 2017 Free Software Foundation, Inc.
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2016-01-01 18:44:31 +08:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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