2003-08-30 00:41:31 +08:00
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# frv testcase to generate interrupts for bad register alignment
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# mach: frv
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.include "testutils.inc"
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start
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.global align
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align:
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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inc_gr_immed 0x080,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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inc_gr_immed 0x050,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_addr ok1,lr
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set_psr_et 1
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2003-10-11 03:30:50 +08:00
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; Make the the register number odd at bad[1-4], bad9 and bada.
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; We can't simply code an odd register number because the assembler
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; will catch the error.
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set_gr_mem bad1,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,bad1
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set_gr_addr bad1,gr10
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flush_data_cache gr10
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set_gr_mem bad2,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,bad2
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set_gr_addr bad2,gr10
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flush_data_cache gr10
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set_gr_mem bad3,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,bad3
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set_gr_addr bad3,gr10
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flush_data_cache gr10
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set_gr_mem bad4,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,bad4
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set_gr_addr bad4,gr10
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flush_data_cache gr10
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set_gr_mem bad9,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,bad9
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set_gr_addr bad9,gr10
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flush_data_cache gr10
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set_gr_mem bada,gr10
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or_gr_immed 0x02000000,gr10
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set_mem_gr gr10,bada
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set_gr_addr bada,gr10
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flush_data_cache gr10
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2003-08-30 00:41:31 +08:00
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set_gr_immed 4,gr20 ; PC increment
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set_gr_immed 0,gr15
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inc_gr_immed -12,sp ; for memory alignment
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set_gr_addr bad1,gr17
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2003-10-11 03:30:50 +08:00
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bad1: stdi gr0,@(sp,0) ; misaligned reg
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2003-08-30 00:41:31 +08:00
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test_gr_immed 1,gr15
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set_gr_addr bad2,gr17
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2003-10-11 03:30:50 +08:00
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bad2: lddi @(sp,0),gr8 ; misaligned reg
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2003-08-30 00:41:31 +08:00
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test_gr_immed 2,gr15
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set_gr_addr bad3,gr17
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2003-10-11 03:30:50 +08:00
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bad3: stdc cpr0,@(sp,gr0) ; misaligned reg
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2003-08-30 00:41:31 +08:00
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test_gr_immed 3,gr15
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set_gr_addr bad4,gr17
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2003-10-11 03:30:50 +08:00
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bad4: lddc @(sp,gr0),cpr8 ; misaligned reg
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2003-08-30 00:41:31 +08:00
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test_gr_immed 4,gr15
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set_gr_addr bad5,gr17
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bad5: stqi gr2,@(sp,0) ; misaligned reg
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test_gr_immed 5,gr15
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set_gr_addr bad6,gr17
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bad6: ldqi @(sp,0),gr10 ; misaligned reg
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test_gr_immed 6,gr15
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set_gr_addr bad7,gr17
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bad7: stqc cpr2,@(sp,gr0) ; misaligned reg
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test_gr_immed 7,gr15
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set_gr_addr bad8,gr17
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bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg
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test_gr_immed 8,gr15
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set_gr_immed 0,gr20 ; PC increment
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set_gr_addr bad9,gr17
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2003-10-11 03:30:50 +08:00
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bad9: stdfi fr0,@(sp,0) ; misaligned reg
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2003-08-30 00:41:31 +08:00
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test_gr_immed 9,gr15
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set_gr_addr bada,gr17
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2003-10-11 03:30:50 +08:00
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bada: lddfi @(sp,0),fr8 ; misaligned reg
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2003-08-30 00:41:31 +08:00
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test_gr_immed 10,gr15
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set_gr_addr badb,gr17
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badb: stqfi fr2,@(sp,0) ; misaligned reg
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test_gr_immed 11,gr15
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set_gr_addr badc,gr17
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badc: ldqfi @(sp,0),fr10 ; misaligned reg
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test_gr_immed 12,gr15
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pass
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; exception handler
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ok1:
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cmpi gr20,0,icc0
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beq icc0,0,float
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; check register_exception
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test_spr_immed 0x1,esfr1 ; esr0 is active
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test_spr_gr epcr0,gr17
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test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
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test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set
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test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set
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test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
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movsg pcsr,gr60
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add gr60,gr20,gr60
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movgs gr60,pcsr
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bra ret
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float:
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; check fp_exception
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test_spr_immed 0,esfr1 ; no esr's active
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ret:
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inc_gr_immed 1,gr15
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rett 0
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fail
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