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https://sourceware.org/git/binutils-gdb.git
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172 lines
2.6 KiB
ArmAsm
172 lines
2.6 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/seq/se_regmv_usp_sysreg/se_regmv_usp_sysreg.dsp
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// Description: RegMV USP to SYSREG
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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//
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// Constants and Defines
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//
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include(selfcheck.inc)
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include(std.inc)
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include(symtable.inc)
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//*********************************************************************
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BEGIN:
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// KLUDGE: from perl script must place cycles 2 write before cycles
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// write, and cycles 2 read AFTER cycles read
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// PUT YOUR TEST HERE!
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R0 = 0;
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SP = R0;
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SYSCFG = R0;
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CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
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R0 = 0x59c4 (Z);
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R0.H = 0x95a6;
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USP = R0;
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ASTAT = USP;
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R1 = ASTAT;
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R0 = 0xd4a4 (Z);
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R0.H = 0xd16c;
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USP = R0;
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RETS = USP;
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R1 = RETS;
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CHECKREG(r1, 3513570468);
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R0 = 0x2bca (Z);
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R0.H = 0x6ad8;
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USP = R0;
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LC0 = USP;
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R1 = LC0;
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CHECKREG(r1, 1792551882);
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R0 = 0x6d4a (Z);
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R0.H = 0xada2;
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USP = R0;
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LT0 = USP;
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R1 = LT0;
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CHECKREG(r1, 2913103178);
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R0 = 0x6b18 (Z);
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R0.H = 0x931c;
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USP = R0;
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LB0 = USP;
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R1 = LB0;
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CHECKREG(r1, 2468113176);
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R0 = 0x62da (Z);
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R0.H = 0x16ee;
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USP = R0;
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LC1 = USP;
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R1 = LC1;
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CHECKREG(r1, 384721626);
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R0 = 0x7c60 (Z);
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R0.H = 0xf7c8;
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USP = R0;
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LT1 = USP;
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R1 = LT1;
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CHECKREG(r1, 4157111392);
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R0 = 0x182 (Z);
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R0.H = 0x942;
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USP = R0;
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LB1 = USP;
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R1 = LB1;
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CHECKREG(r1, 155320706);
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R0 = 0xd5a2 (Z);
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R0.H = 0x8782;
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USP = R0;
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CYCLES2 = USP;
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// KLUDGE - moved read after that for cycles
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R0 = 0x297c (Z);
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R0.H = 0x9d06;
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USP = R0;
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CYCLES = USP;
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R1 = CYCLES;
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CHECKREG(r1, 2634426748);
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R1 = CYCLES2; // KLUDGE moved read after that for cycles
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CHECKREG(r1, 2273498530);
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R0 = 0x8c66 (Z);
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R0.H = 0x3d64;
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USP = R0;
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SEQSTAT = USP;
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R1 = SEQSTAT;
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R0 = 0x3b8c (Z);
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R0.H = 0xdcd4;
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USP = R0;
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SYSCFG = USP;
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R1 = SYSCFG;
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R0 = 0xb1ae (Z);
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R0.H = 0x6f6;
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USP = R0;
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RETI = USP;
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R1 = RETI;
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CHECKREG(r1, 116830638);
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R0 = 0x32b0 (Z);
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R0.H = 0x9b7e;
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USP = R0;
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RETX = USP;
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R1 = RETX;
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CHECKREG(r1, 2608738992);
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R0 = 0xea72 (Z);
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R0.H = 0x11ea;
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USP = R0;
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RETN = USP;
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R1 = RETN;
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CHECKREG(r1, 300608114);
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R0 = 0x2c58 (Z);
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R0.H = 0xb13a;
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USP = R0;
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RETE = USP;
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R1 = RETE;
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CHECKREG(r1, 2973379672);
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// Sanity check
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USP = R0;
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USP = R1;
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USP = R2;
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USP = R3;
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USP = R4;
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USP = R5;
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USP = R6;
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USP = R7;
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USP = P0;
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USP = P1;
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USP = P2;
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USP = P3;
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USP = P4;
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USP = P5;
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USP = SP;
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USP = FP;
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USP = A0.X;
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USP = A0.W;
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USP = A1.X;
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USP = A1.W;
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A0.X = USP;
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A0.W = USP;
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A1.X = USP;
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A1.W = USP;
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END:
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dbg_pass; // End the test
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//*********************************************************************
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