mirror of
https://sourceware.org/git/binutils-gdb.git
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402 lines
9.6 KiB
ArmAsm
402 lines
9.6 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp
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// Description: LMU protection exceptions
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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//-------------------------------------
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// Test LMU/CPLB exceptions
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// Basic outline:
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// Set exception handler
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// program CPLB Entries
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// Enable CPLB in DMEM_CNTL
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// perform access
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// verify exception occurred
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CHECK_INIT(p5, 0xEFFFFFFC);
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A0 = 0;
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//-------------------------
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// Zero the CPLB Address and Data regs.
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LD32(p0, DCPLB_ADDR0);
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R0 = 0;
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[ P0 ++ ] = R0; // 0
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[ P0 ++ ] = R0; // 1
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[ P0 ++ ] = R0; // 2
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[ P0 ++ ] = R0; // 3
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[ P0 ++ ] = R0; // 4
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[ P0 ++ ] = R0; // 5
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[ P0 ++ ] = R0; // 6
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[ P0 ++ ] = R0; // 7
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[ P0 ++ ] = R0; // 8
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[ P0 ++ ] = R0; // 9
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[ P0 ++ ] = R0; // 10
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[ P0 ++ ] = R0; // 11
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[ P0 ++ ] = R0; // 12
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[ P0 ++ ] = R0; // 13
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[ P0 ++ ] = R0; // 14
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[ P0 ++ ] = R0; // 15
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LD32(p0, DCPLB_DATA0);
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[ P0 ++ ] = R0; // 0
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[ P0 ++ ] = R0; // 1
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[ P0 ++ ] = R0; // 2
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[ P0 ++ ] = R0; // 3
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[ P0 ++ ] = R0; // 4
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[ P0 ++ ] = R0; // 5
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[ P0 ++ ] = R0; // 6
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[ P0 ++ ] = R0; // 7
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[ P0 ++ ] = R0; // 8
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[ P0 ++ ] = R0; // 9
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[ P0 ++ ] = R0; // 10
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[ P0 ++ ] = R0; // 11
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[ P0 ++ ] = R0; // 12
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[ P0 ++ ] = R0; // 13
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[ P0 ++ ] = R0; // 14
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[ P0 ++ ] = R0; // 15
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// Now set the CPLB entries we will need
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// Data area for the desired error
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WR_MMR(DCPLB_ADDR0, 0x800, p0, r0);
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WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0);
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WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE, p0, r0);
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WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0);
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WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0);
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WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0);
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WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0);
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WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0);
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WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0);
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// CHECKREG segment
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WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0);
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WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0);
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// MMR space
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WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0);
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WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0);
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// setup interrupt controller with exception handler address
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WR_MMR_LABEL(EVT3, handler, p0, r1);
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WR_MMR_LABEL(EVT15, int_15, p0, r1);
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WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
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WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
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// enable CPLB
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WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
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NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC
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// Address for slot 0 accesses
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// LD32(p4, 0xEFFFFFF8);
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// go to user mode. and enable exceptions
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LD32_LABEL(r0, User);
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RETI = R0;
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// But first raise interrupt 15 so we can do one test
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// in supervisor mode.
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RAISE 15;
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NOP;
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RTI;
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// Nops to work around ICache bug
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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int_15:
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// Interrupt 15 handler - needed to try supervisor access with exceptions enabled
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//-------------------------------------------------------
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// Protection violation - Illegal Supervisor Write Access
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R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
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LD32(i1, 0x800);
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LD32(r1, 0xDEADBEEF);
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LD32(p2, DCPLB_DATA0);
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LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
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LD32(p3, DCPLB_DATA1);
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LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
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X0: //[p1] = r1; // Exception should occur here
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A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
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// Now check that handler read correct values
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CHECKREG(r4,0x23); // supv and EXCPT_PROT
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CHECKREG(r5, 0x800);
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CHECKREG(r6, (FAULT_SUPV|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB0));
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CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!)
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// go to user mode. and enable exceptions
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LD32_LABEL(r0, User);
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RTI;
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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User:
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NOP;NOP;NOP;NOP;NOP;
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//-------------------------------------------------------
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// Protection violation - Illegal User Write Access
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R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
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LD32(i1, 0x1000);
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LD32(r1, 0xDEADBEEF);
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// values to fix up current test
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LD32(p2, DCPLB_DATA1);
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LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
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// values for next test
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LD32(p3, DCPLB_DATA2);
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LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE);
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X1: //[p1] = r1; // Exception should occur here
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A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
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// Now check that handler read correct values
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CHECKREG(r4,0x23); // supv and EXCPT_PROT
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CHECKREG(r5, 0x1000);
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CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB1));
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CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// Protection violation - Illegal User Read Access
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R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
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LD32(i1, 0x2000);
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LD32(r1, 0xDEADBEEF);
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LD32(p2, DCPLB_DATA2);
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LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR);
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LD32(p3, DCPLB_DATA3);
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LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
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X2: //[p1] = r1; // Exception should occur here
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A0 = 0 || NOP || R0 = [ I1 ]; // test access with DAG1
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// Now check that handler read correct values
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CHECKREG(r4,0x23); // supv and EXCPT_PROT
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CHECKREG(r5, 0x2000);
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CHECKREG(r6, (FAULT_USER|FAULT_READ|FAULT_DAG1 | FAULT_CPLB2));
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CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// Protection violation - Illegal Dirty Page Access
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R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
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LD32(i1, 0x3000);
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LD32(r1, 0xDEADBEEF);
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LD32(p2, DCPLB_DATA3);
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LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
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LD32(p3, DCPLB_DATA4);
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LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
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X3: //[p1] = r1; // Exception should occur here
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A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
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// Now check that handler read correct values
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CHECKREG(r4,0x23); // supv and EXCPT_PROT
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CHECKREG(r5, 0x3000);
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CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB3));
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CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// Protection violation - Illegal DAG1 Access
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R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
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LD32(i1, 0x4000);
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LD32(r1, 0xDEADBEEF);
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LD32(p2, DCPLB_DATA4);
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LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
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LD32(p3, DCPLB_DATA5);
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LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
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X4: //[p1] = r1; // Exception should occur here
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A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
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// Now check that handler read correct values
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CHECKREG(r4,0x23); // supv and EXCPT_PROT
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CHECKREG(r5, 0x4000);
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CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB4));
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CHECKREG_SYM(r7, X4, r0); // RETX should be value of X4 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// L1Miss not implemented yet - skip for now....
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// //-------------------------------------------------------
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// // Protection violation - L1 Miss
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// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0;
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//
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// LD32(p1, 0x6000);
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// LD32(r1, 0xDEADBEEF);
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//
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// LD32(p2, DCPLB_DATA6);
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// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
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//
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// LD32(p3, DCPLB_DATA7);
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// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR);
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//
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//
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//X6: //[p1] = r1; // Exception should occur here
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// r0 = [p1];
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//
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//
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// // Now check that handler read correct values
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// CHECKREG(r4,0x23); // supv and EXCPT_PROT
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// CHECKREG(r5, 0x6000);
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// // CHECKREG(r6, FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB6);
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// CHECKREG_SYM(r7, X6, r0); // RETX should be value of X6 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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dbg_pass;
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handler:
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// generic protection exception handler
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// Inputs:
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// p2: addr of CPLB entry to be modified ( current test)
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// r2: new data for CPLB entry
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//
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// p3: addr of CPLB entry to be modified ( next test)
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// r3: new data for CPLB entry
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//
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// Outputs:
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// r4: SEQSTAT
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// r5: DCPLB_FAULT_ADDR
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// r6: DCPLB_STATUS
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// r7: RETX (instruction addr where exception occurred)
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R4 = SEQSTAT; // Get exception cause
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// read data addr which caused exception
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RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
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RD_MMR(DCPLB_STATUS, p0, r6);
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// Reset status regs
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WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r0);
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WR_MMR(DCPLB_STATUS, 0, p0, r0);
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R7 = RETX; // get address of excepting instruction
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||
|
|
|
||
|
|
// modify CPLB to allow access. Main pgm passes in addr and data
|
||
|
|
[ P2 ] = R2;
|
||
|
|
|
||
|
|
// Set up for next test
|
||
|
|
[ P3 ] = R3;
|
||
|
|
|
||
|
|
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC;
|
||
|
|
|
||
|
|
// return from exception and re-execute offending instruction
|
||
|
|
RTX;
|
||
|
|
|
||
|
|
// Nops to work around ICache bug
|
||
|
|
NOP;NOP;NOP;NOP;NOP;
|
||
|
|
NOP;NOP;NOP;NOP;NOP;
|
||
|
|
|
||
|
|
|
||
|
|
.section MEM_0x800,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
|
||
|
|
.section MEM_0x1000,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
|
||
|
|
.section MEM_0x2000,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
|
||
|
|
.section MEM_0x3000,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
|
||
|
|
.section MEM_0x4000,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
|
||
|
|
.section MEM_0x5000,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
|
||
|
|
// Need a cache miss to test CPLB_L1REF
|
||
|
|
//.data 0x6000
|
||
|
|
// .dd 0x00000000
|
||
|
|
// .dd 0x00000000
|
||
|
|
// .dd 0x00000000
|
||
|
|
// .dd 0x00000000
|
||
|
|
|
||
|
|
.section MEM_0x7000,"aw"
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|
||
|
|
.dd 0x00000000
|