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https://sourceware.org/git/binutils-gdb.git
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164 lines
3.1 KiB
ArmAsm
164 lines
3.1 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp
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// Spec Reference: ptr2op preg -= preg
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# mach: bfin
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.include "testutils.inc"
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start
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// check p-reg to p-reg move
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imm32 p1, 0xf0021003;
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imm32 p2, 0x2e041005;
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imm32 p3, 0x20d61007;
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imm32 p4, 0x200a1009;
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imm32 p5, 0x200a300b;
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imm32 sp, 0x200c180d;
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imm32 fp, 0x200e109f;
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P1 -= P1;
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P2 -= P1;
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P3 -= P1;
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P4 -= P1;
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P5 -= P1;
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SP -= P1;
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FP -= P1;
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CHECKREG p1, 0x00000000;
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CHECKREG p2, 0x2E041005;
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CHECKREG p3, 0x20D61007;
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CHECKREG p4, 0x200A1009;
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CHECKREG p5, 0x200A300B;
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CHECKREG sp, 0x200C180D;
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CHECKREG fp, 0x200E109F;
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imm32 p1, 0x50021003;
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imm32 p2, 0x26041005;
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imm32 p3, 0x20761007;
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imm32 p4, 0x20081009;
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imm32 p5, 0x200a900b;
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imm32 sp, 0x200c1a0d;
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imm32 fp, 0x200e10bf;
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P1 -= P2;
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P2 -= P2;
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P3 -= P2;
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P4 -= P2;
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P5 -= P2;
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SP -= P2;
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FP -= P2;
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CHECKREG p1, 0x29FDFFFE;
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CHECKREG p2, 0x00000000;
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CHECKREG p3, 0x20761007;
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CHECKREG p4, 0x20081009;
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CHECKREG p5, 0x200A900B;
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CHECKREG sp, 0x200C1A0D;
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CHECKREG fp, 0x200E10BF;
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imm32 p1, 0x20021003;
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imm32 p2, 0x20041005;
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imm32 p3, 0x20061007;
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imm32 p4, 0x20081009;
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imm32 p5, 0x200a100b;
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imm32 sp, 0x200c100d;
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imm32 fp, 0x200e100f;
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P1 -= P3;
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P2 -= P3;
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P3 -= P3;
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P4 -= P3;
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P5 -= P3;
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SP -= P3;
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FP -= P3;
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CHECKREG p1, 0xFFFBFFFC;
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CHECKREG p2, 0xFFFDFFFE;
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CHECKREG p3, 0x00000000;
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CHECKREG p4, 0x20081009;
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CHECKREG p5, 0x200A100B;
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CHECKREG sp, 0x200C100D;
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CHECKREG fp, 0x200E100F;
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imm32 p1, 0xa0021003;
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imm32 p2, 0x2c041005;
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imm32 p3, 0x20b61007;
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imm32 p4, 0x200d1009;
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imm32 p5, 0x200ae00b;
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imm32 sp, 0x200c110d;
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imm32 fp, 0x200e104f;
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P1 -= P4;
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P2 -= P4;
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P3 -= P4;
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P4 -= P4;
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P5 -= P4;
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SP -= P4;
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FP -= P4;
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CHECKREG p1, 0x7FF4FFFA;
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CHECKREG p2, 0x0BF6FFFC;
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CHECKREG p3, 0x00A8FFFE;
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CHECKREG p4, 0x00000000;
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CHECKREG p5, 0x200AE00B;
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CHECKREG sp, 0x200C110D;
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CHECKREG fp, 0x200E104F;
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imm32 p1, 0x10021003;
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imm32 p2, 0x22041005;
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imm32 p3, 0x20361007;
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imm32 p4, 0x20041009;
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imm32 p5, 0x200aa00b;
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imm32 sp, 0x200c1b0d;
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imm32 fp, 0x200e10cf;
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P1 -= P5;
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P2 -= P5;
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P3 -= P5;
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P4 -= P5;
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P5 -= P5;
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SP -= P5;
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FP -= P5;
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CHECKREG p1, 0xEFF76FF8;
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CHECKREG p2, 0x01F96FFA;
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CHECKREG p3, 0x002B6FFC;
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CHECKREG p4, 0xFFF96FFE;
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CHECKREG p5, 0x00000000;
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CHECKREG sp, 0x200C1B0D;
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CHECKREG fp, 0x200E10CF;
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imm32 p1, 0x20021003;
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imm32 p2, 0x20041005;
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imm32 p3, 0x20061007;
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imm32 p4, 0x20081009;
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imm32 p5, 0x200a100b;
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imm32 sp, 0x200c100d;
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imm32 fp, 0x200e100f;
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P1 -= SP;
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P2 -= SP;
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P3 -= SP;
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P4 -= SP;
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P5 -= SP;
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SP -= SP;
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FP -= SP;
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CHECKREG p1, 0xFFF5FFF6;
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CHECKREG p2, 0xFFF7FFF8;
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CHECKREG p3, 0xFFF9FFFA;
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CHECKREG p4, 0xFFFBFFFC;
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CHECKREG p5, 0xFFFDFFFE;
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CHECKREG sp, 0x00000000;
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CHECKREG fp, 0x200E100F;
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imm32 p1, 0x20021003;
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imm32 p2, 0x20041005;
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imm32 p3, 0x20061007;
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imm32 p4, 0x20081009;
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imm32 p5, 0x200a100b;
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imm32 sp, 0x200c100d;
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imm32 fp, 0x200e100f;
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P1 -= FP;
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P2 -= FP;
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P3 -= FP;
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P4 -= FP;
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P5 -= FP;
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SP -= FP;
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FP -= FP;
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CHECKREG p1, 0xFFF3FFF4;
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CHECKREG p2, 0xFFF5FFF6;
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CHECKREG p3, 0xFFF7FFF8;
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CHECKREG p4, 0xFFF9FFFA;
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CHECKREG p5, 0xFFFBFFFC;
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CHECKREG sp, 0xFFFDFFFE;
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CHECKREG fp, 0x00000000;
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pass
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