mirror of
https://sourceware.org/git/binutils-gdb.git
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418 lines
8.3 KiB
ArmAsm
418 lines
8.3 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp
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// Spec Reference: mmr loop (interr control) no exception
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(gen_int.inc)
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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#ifndef STACKSIZE
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#define STACKSIZE 0x10
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#endif
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//
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////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
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//
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// Reset/Bootstrap Code
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// (Here we set the processor operating modes, initialize registers
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// etc.)
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//
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BOOT:
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INIT_R_REGS(0);
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INIT_P_REGS(0);
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INIT_I_REGS(0); // initialize the dsp address regs
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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//CHECK_INIT(p5, 0xe0000000);
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include(symtable.inc)
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CHECK_INIT_DEF(p5);
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CLI R1; // inhibit events during MMR writes
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LD32_LABEL(sp, USTACK); // setup the user stack pointer
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USP = SP; // and frame pointer
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LD32_LABEL(sp, KSTACK); // setup the stack pointer
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FP = SP; // and frame pointer
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LD32(p0, EVT0); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R1 = -1; // Change this to mask interrupts (*)
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CSYNC; // wait for MMR writes to finish
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STI R1; // sync and reenable events (implicit write to IMASK)
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DUMMY:
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R0 = 0 (Z);
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LT0 = r0; // set loop counters to something deterministic
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LB0 = r0;
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LC0 = r0;
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LT1 = r0;
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LB1 = r0;
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LC1 = r0;
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ASTAT = r0; // reset other internal regs
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SYSCFG = r0;
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RETS = r0; // prevent X's breaking LINK instruction
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// The following code sets up the test for running in USER mode
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LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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// Comment the following line for a USER Mode test
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JUMP STARTSUP; // jump to code start for SUPERVISOR mode
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RTI;
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STARTSUP:
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LD32_LABEL(p1, BEGIN);
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LD32(p0, EVT15);
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CLI R1; // inhibit events during write to MMR
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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CSYNC; // wait for it
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STI R1; // reenable events with proper imask
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RAISE 15; // after we RTI, INT 15 should be taken
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RTI;
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//
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// The Main Program
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//
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STARTUSER:
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LINK 0; // change for how much stack frame space you need.
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JUMP BEGIN;
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//*********************************************************************
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BEGIN:
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// COMMENT the following line for USER MODE tests
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[ -- SP ] = RETI; // enable interrupts in supervisor mode
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// **** YOUR CODE GOES HERE ****
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// EVTx
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// wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000
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LD32(p0, 0xFFE02000);
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LD32(r0, 0x00000000);
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[ P0 ] = R0;
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// wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004
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LD32(p0, 0xFFE02004);
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LD32(r0, 0x00000000);
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[ P0 ] = R0;
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// wrt-rd EVT2 = 0xFFE02008
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LD32(p0, 0xFFE02008);
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LD32(r0, 0xE1DE5D1C);
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[ P0 ] = R0;
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// wrt-rd EVT3 = 0xFFE0200C
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LD32(p0, 0xFFE0200C);
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LD32(r0, 0x9CC20332);
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[ P0 ] = R0;
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// wrt-rd EVT4 = 0xFFE02010
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LD32(p0, 0xFFE02010);
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LD32(r0, 0x00000000); // not implemented
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[ P0 ] = R0;
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// wrt-rd EVT5 = 0xFFE02014
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LD32(p0, 0xFFE02014);
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LD32(r0, 0x55552345);
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[ P0 ] = R0;
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// wrt-rd EVT6 = 0xFFE02018
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LD32(p0, 0xFFE02018);
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LD32(r0, 0x66663456);
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[ P0 ] = R0;
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// wrt-rd EVT7 = 0xFFE0201C
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LD32(p0, 0xFFE0201C);
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LD32(r0, 0x77774567);
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[ P0 ] = R0;
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// wrt-rd EVT8 = 0xFFE02020
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LD32(p0, 0xFFE02020);
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LD32(r0, 0x88885678);
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[ P0 ] = R0;
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// wrt-rd EVT9 = 0xFFE02024
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LD32(p0, 0xFFE02024);
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LD32(r0, 0x99996789);
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[ P0 ] = R0;
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// wrt-rd EVT10 = 0xFFE02028
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LD32(p0, 0xFFE02028);
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LD32(r0, 0xaaaa1234);
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[ P0 ] = R0;
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// wrt-rd EVT11 = 0xFFE0202C
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LD32(p0, 0xFFE0202C);
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LD32(r0, 0xBBBBABC6);
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[ P0 ] = R0;
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// wrt-rd EVT12 = 0xFFE02030
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LD32(p0, 0xFFE02030);
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LD32(r0, 0xCCCCABC6);
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[ P0 ] = R0;
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// wrt-rd EVT13 = 0xFFE02034
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LD32(p0, 0xFFE02034);
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LD32(r0, 0xDDDDABC6);
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[ P0 ] = R0;
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// wrt-rd EVT14 = 0xFFE02038
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LD32(p0, 0xFFE02038);
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LD32(r0, 0xEEEEABC6);
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[ P0 ] = R0;
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// wrt-rd EVT15 = 0xFFE0203C
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LD32(p0, 0xFFE0203C);
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LD32(r0, 0xFFFFABC6);
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[ P0 ] = R0;
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// wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100
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LD32(p0, 0xFFE02100);
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LD32(r0, 0x000001ff);
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[ P0 ] = R0;
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// wrt-rd IMASK: 16 bits = 0xFFE02104
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LD32(p0, 0xFFE02104);
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LD32(r0, 0x00000fe0);
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[ P0 ] = R0;
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// wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108
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LD32(p0, 0xFFE02108);
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LD32(r0, 0x00000000);
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//[p0] = r0;
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RAISE 12;
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RAISE 13;
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// wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C
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LD32(p0, 0xFFE0210C);
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LD32(r0, 0x00000000);
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//[p0] = r0;
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CSYNC;
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//*** read ops
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P1.L = DATA0;
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P1.H = DATA0;
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LD32(p0, 0xFFE02000);
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P2 = 16;
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LSETUP ( start1 , end1 ) LC0 = P2;
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start1:
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R0 = [ P0 ++ ];
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end1: [ P1 ++ ] = R0;
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//nop;
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P1.L = DATA0;
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P1.H = DATA0;
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R0 = [ P1 ++ ];
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R1 = [ P1 ++ ];
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R2 = [ P1 ++ ];
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R3 = [ P1 ++ ];
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R4 = [ P1 ++ ];
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R5 = [ P1 ++ ];
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R6 = [ P1 ++ ];
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R7 = [ P1 ++ ];
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CHECKREG(r0, 0x00000000);
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CHECKREG(r1, 0x00000000);
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CHECKREG(r2, 0xE1DE5D1C);
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CHECKREG(r3, 0x9CC20332);
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CHECKREG(r4, 0x00000000);
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CHECKREG(r5, 0x55552345);
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CHECKREG(r6, 0x66663456);
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CHECKREG(r7, 0x77774567);
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R0 = [ P1 ++ ];
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R1 = [ P1 ++ ];
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R2 = [ P1 ++ ];
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R3 = [ P1 ++ ];
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R4 = [ P1 ++ ];
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R5 = [ P1 ++ ];
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R6 = [ P1 ++ ];
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R7 = [ P1 ++ ];
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CHECKREG(r0, 0x88885678);
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CHECKREG(r1, 0x99996789);
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CHECKREG(r2, 0xAAAA1234);
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CHECKREG(r3, 0xBBBBABC6);
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CHECKREG(r4, 0xCCCCABC6);
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CHECKREG(r5, 0xDDDDABC6);
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CHECKREG(r6, 0xEEEEABC6);
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CHECKREG(r7, 0xFFFFABC6);
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dbg_pass; // End the test
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//*********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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R0 = 2;
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RTN;
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XHANDLE: // Exception Handler 3
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R7 = 0x00006789 (X);
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RTX;
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HWHANDLE: // HW Error Handler 5
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R2 = 5;
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RTI;
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THANDLE: // Timer Handler 6
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R3 = 6;
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RTI;
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I7HANDLE: // IVG 7 Handler
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R4 = 7;
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RTI;
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I8HANDLE: // IVG 8 Handler
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R5 = 8;
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RTI;
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I9HANDLE: // IVG 9 Handler
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R6 = 9;
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RTI;
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I10HANDLE: // IVG 10 Handler
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R7 = 10;
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RTI;
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I11HANDLE: // IVG 11 Handler
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R0 = 11;
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RTI;
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I12HANDLE: // IVG 12 Handler
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R1 = 12;
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RTI;
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I13HANDLE: // IVG 13 Handler
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R2 = 13;
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RTI;
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I14HANDLE: // IVG 14 Handler
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R3 = 14;
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RTI;
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I15HANDLE: // IVG 15 Handler
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R4 = 15;
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RTI;
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NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
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//
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// Data Segment
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//
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.section MEM_DATA_ADDR_1,"aw"
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DATA0:
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.dd 0x000a0000
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|
|
.dd 0x000b0001
|
||
|
|
.dd 0x000c0002
|
||
|
|
.dd 0x000d0003
|
||
|
|
.dd 0x000e0004
|
||
|
|
.dd 0x000f0005
|
||
|
|
.dd 0x00100006
|
||
|
|
.dd 0x00200007
|
||
|
|
.dd 0x00300008
|
||
|
|
.dd 0x00400009
|
||
|
|
.dd 0x0050000a
|
||
|
|
.dd 0x0060000b
|
||
|
|
.dd 0x0070000c
|
||
|
|
.dd 0x0080000d
|
||
|
|
.dd 0x0090000e
|
||
|
|
.dd 0x0100000f
|
||
|
|
.dd 0x02000010
|
||
|
|
.dd 0x03000011
|
||
|
|
.dd 0x04000012
|
||
|
|
.dd 0x05000013
|
||
|
|
.dd 0x06000014
|
||
|
|
.dd 0x001a0000
|
||
|
|
.dd 0x001b0001
|
||
|
|
.dd 0x001c0002
|
||
|
|
// Stack Segments (Both Kernel and User)
|
||
|
|
|
||
|
|
.space (STACKSIZE);
|
||
|
|
KSTACK:
|
||
|
|
|
||
|
|
.space (STACKSIZE);
|
||
|
|
USTACK:
|