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83 lines
1.4 KiB
ArmAsm
83 lines
1.4 KiB
ArmAsm
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//Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp
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// Spec Reference: ldimmhalf h dreg
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS -1;
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// test Dreg
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R0.H = 0x0000;
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R1.H = 0x0002;
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R2.H = 0x0004;
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R3.H = 0x0006;
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R4.H = 0x0008;
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R5.H = 0x000a;
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R6.H = 0x000c;
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R7.H = 0x000e;
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CHECKREG r0, 0x0000ffff;
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CHECKREG r1, 0x0002ffff;
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CHECKREG r2, 0x0004ffff;
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CHECKREG r3, 0x0006ffff;
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CHECKREG r4, 0x0008ffff;
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CHECKREG r5, 0x000affff;
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CHECKREG r6, 0x000cffff;
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CHECKREG r7, 0x000effff;
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R0.H = 0x0000;
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R1.H = 0x0020;
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R2.H = 0x0040;
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R3.H = 0x0060;
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R4.H = 0x0080;
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R5.H = 0x00a0;
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R6.H = 0x00c0;
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R7.H = 0x00e0;
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CHECKREG r0, 0x0000ffff;
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CHECKREG r1, 0x0020ffff;
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CHECKREG r2, 0x0040ffff;
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CHECKREG r3, 0x0060ffff;
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CHECKREG r4, 0x0080ffff;
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CHECKREG r5, 0x00a0ffff;
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CHECKREG r6, 0x00c0ffff;
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CHECKREG r7, 0x00e0ffff;
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R0.H = 0x0000;
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R1.H = 0x0200;
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R2.H = 0x0400;
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R3.H = 0x0600;
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R4.H = 0x0800;
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R5.H = 0x0a00;
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R6.H = 0x0c00;
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R7.H = 0x0e00;
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CHECKREG r0, 0x0000ffff;
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CHECKREG r1, 0x0200ffff;
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CHECKREG r2, 0x0400ffff;
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CHECKREG r3, 0x0600ffff;
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CHECKREG r4, 0x0800ffff;
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CHECKREG r5, 0x0a00ffff;
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CHECKREG r6, 0x0c00ffff;
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CHECKREG r7, 0x0e00ffff;
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R0.H = 0x0000;
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R1.H = 0x2000;
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R2.H = 0x4000;
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R3.H = 0x6000;
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R4.H = 0x8000;
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R5.H = 0xa000;
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R6.H = 0xc000;
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R7.H = 0xe000;
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CHECKREG r0, 0x0000ffff;
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CHECKREG r1, 0x2000ffff;
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CHECKREG r2, 0x4000ffff;
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CHECKREG r3, 0x6000ffff;
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CHECKREG r4, 0x8000ffff;
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CHECKREG r5, 0xa000ffff;
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CHECKREG r6, 0xc000ffff;
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CHECKREG r7, 0xe000ffff;
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pass
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