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61 lines
1.1 KiB
ArmAsm
61 lines
1.1 KiB
ArmAsm
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//Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp
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// Spec Reference: ldimmhalf dreg imm16
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS -1;
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// test Dreg
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R0 = 0x0123 (X);
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R1 = 0x1234 (X);
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R2 = 0x2345 (X);
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R3 = 0x3456 (X);
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R4 = 0x4567 (X);
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R5 = 0x5678 (X);
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R6 = 0x6789 (X);
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R7 = 0x789a (X);
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CHECKREG r0, 0x00000123;
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CHECKREG r1, 0x00001234;
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CHECKREG r2, 0x00002345;
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CHECKREG r3, 0x00003456;
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CHECKREG r4, 0x00004567;
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CHECKREG r5, 0x00005678;
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CHECKREG r6, 0x00006789;
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CHECKREG r7, 0x0000789A;
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R0 = -32768 (X);
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R1 = -1111 (X);
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R2 = -2222 (X);
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R3 = -3333 (X);
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R4 = -4444 (X);
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R5 = -5555 (X);
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R6 = -6666 (X);
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R7 = -7777 (X);
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CHECKREG r0, 0xFFFF8000;
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CHECKREG r1, 0xFFFFFBA9;
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CHECKREG r2, 0xFFFFF752;
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CHECKREG r3, 0xFFFFF2FB;
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CHECKREG r4, 0xFFFFEEA4;
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CHECKREG r5, 0xFFFFEA4D;
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CHECKREG r6, 0xFFFFE5F6;
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CHECKREG r7, 0xFFFFE19F;
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R0 = 0x7fff (X);
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R1 = 0x7ffe (X);
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R2 = 32767 (X);
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R3 = 32766 (X);
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R4 = -32768 (X);
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R5 = -32767 (X);
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CHECKREG r0, 0x00007fff;
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CHECKREG r1, 0x00007ffe;
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CHECKREG r2, 0x00007fff;
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CHECKREG r3, 0x00007ffe;
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CHECKREG r4, 0xFFFF8000;
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CHECKREG r5, 0xFFFF8001;
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pass
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