mirror of
https://sourceware.org/git/binutils-gdb.git
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421 lines
8.6 KiB
ArmAsm
421 lines
8.6 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp
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// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
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# mach: bfin
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.include "testutils.inc"
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start
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// Ashift : positive data, count (+)=right (half reg)
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// d_lo = ashft (d_lo BY d_lo)
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// RLx by RLx
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imm32 r0, 0x00000000;
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R0.L = -1;
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imm32 r1, 0x00010001;
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imm32 r2, 0x00010002;
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imm32 r3, 0x00010003;
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imm32 r4, 0x00010004;
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imm32 r5, 0x00010005;
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imm32 r6, 0x00010006;
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imm32 r7, 0x00010007;
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R0.L = R0.L >>> 1;
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R1.L = R1.L >>> 1;
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R2.L = R2.L >>> 1;
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R3.L = R3.L >>> 1;
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R4.L = R4.L >>> 1;
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R5.L = R5.L >>> 1;
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R6.L = R6.L >>> 1;
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R7.L = R7.L >>> 1;
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CHECKREG r0, 0x0000FFFF;
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CHECKREG r1, 0x00010000;
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CHECKREG r2, 0x00010001;
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CHECKREG r3, 0x00010001;
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CHECKREG r4, 0x00010002;
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CHECKREG r5, 0x00010002;
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CHECKREG r6, 0x00010003;
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CHECKREG r7, 0x00010003;
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imm32 r0, 0x00201001;
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R1.L = -1;
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imm32 r2, 0x00202002;
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imm32 r3, 0x00203003;
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imm32 r4, 0x00204004;
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imm32 r5, 0x00205005;
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imm32 r6, 0x00206006;
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imm32 r7, 0x00207007;
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R7.L = R0.L >>> 5;
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R0.L = R1.L >>> 5;
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R1.L = R2.L >>> 5;
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R2.L = R3.L >>> 5;
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R3.L = R4.L >>> 5;
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R4.L = R5.L >>> 5;
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R5.L = R6.L >>> 5;
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R6.L = R7.L >>> 5;
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CHECKREG r0, 0x0020FFFF;
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CHECKREG r1, 0x00010100;
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CHECKREG r2, 0x00200180;
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CHECKREG r3, 0x00200200;
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CHECKREG r4, 0x00200280;
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CHECKREG r5, 0x00200300;
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CHECKREG r6, 0x00200004;
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CHECKREG r7, 0x00200080;
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imm32 r0, 0x03001001;
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imm32 r1, 0x03001001;
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R2.L = -15;
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imm32 r3, 0x03003003;
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imm32 r4, 0x03004004;
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imm32 r5, 0x03005005;
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imm32 r6, 0x03006006;
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imm32 r7, 0x03007007;
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R6.L = R0.L >>> 2;
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R7.L = R1.L >>> 2;
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R0.L = R2.L >>> 2;
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R1.L = R3.L >>> 2;
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R2.L = R4.L >>> 2;
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R3.L = R5.L >>> 2;
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R4.L = R6.L >>> 2;
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R5.L = R7.L >>> 2;
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CHECKREG r0, 0x0300FFFC;
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CHECKREG r1, 0x03000C00;
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CHECKREG r2, 0x00201001;
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CHECKREG r3, 0x03001401;
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CHECKREG r4, 0x03000100;
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CHECKREG r5, 0x03000100;
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CHECKREG r6, 0x03000400;
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CHECKREG r7, 0x03000400;
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imm32 r0, 0x40001001;
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imm32 r1, 0x40001001;
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imm32 r2, 0x40002002;
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R3.L = -16;
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imm32 r4, 0x40004004;
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imm32 r5, 0x40005005;
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imm32 r6, 0x40006006;
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imm32 r7, 0x40007007;
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R5.L = R0.L >>> 13;
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R6.L = R1.L >>> 13;
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R7.L = R2.L >>> 13;
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R0.L = R3.L >>> 13;
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R1.L = R4.L >>> 13;
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R2.L = R5.L >>> 13;
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R3.L = R6.L >>> 13;
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R4.L = R7.L >>> 13;
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CHECKREG r0, 0x4000FFFF;
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CHECKREG r1, 0x40000002;
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CHECKREG r2, 0x40000000;
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CHECKREG r3, 0x03000000;
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CHECKREG r4, 0x40000000;
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CHECKREG r5, 0x40000000;
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CHECKREG r6, 0x40000000;
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CHECKREG r7, 0x40000001;
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// d_lo = ashift (d_hi BY d_lo)
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// RHx by RLx
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imm32 r0, 0x50000000;
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imm32 r1, 0x50010000;
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imm32 r2, 0x50020000;
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imm32 r3, 0x50030000;
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imm32 r4, 0x50040000;
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imm32 r5, 0x50050000;
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imm32 r6, 0x50060000;
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imm32 r7, 0x50070000;
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R3.L = R0.H >>> 10;
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R4.L = R1.H >>> 10;
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R5.L = R2.H >>> 10;
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R6.L = R3.H >>> 10;
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R7.L = R4.H >>> 10;
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R0.L = R5.H >>> 10;
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R1.L = R6.H >>> 10;
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R2.L = R7.H >>> 10;
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CHECKREG r0, 0x50000014;
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CHECKREG r1, 0x50010014;
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CHECKREG r2, 0x50020014;
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CHECKREG r3, 0x50030014;
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CHECKREG r4, 0x50040014;
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CHECKREG r5, 0x50050014;
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CHECKREG r6, 0x50060014;
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CHECKREG r7, 0x50070014;
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imm32 r0, 0x10016000;
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R1.L = -1;
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imm32 r2, 0x20026000;
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imm32 r3, 0x30036000;
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imm32 r4, 0x40046000;
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imm32 r5, 0x50056000;
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imm32 r6, 0x60060000;
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imm32 r7, 0x70076000;
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R0.L = R0.H >>> 11;
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R1.L = R1.H >>> 11;
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R2.L = R2.H >>> 11;
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R3.L = R3.H >>> 11;
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R4.L = R4.H >>> 11;
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R5.L = R5.H >>> 11;
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R6.L = R6.H >>> 11;
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R7.L = R7.H >>> 11;
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CHECKREG r0, 0x10010002;
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CHECKREG r1, 0x5001000A;
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CHECKREG r2, 0x20020004;
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CHECKREG r3, 0x30030006;
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CHECKREG r4, 0x40040008;
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CHECKREG r5, 0x5005000A;
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CHECKREG r6, 0x6006000C;
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CHECKREG r7, 0x7007000E;
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imm32 r0, 0x10010700;
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imm32 r1, 0x10010700;
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R2.L = -15;
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imm32 r3, 0x30030700;
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imm32 r4, 0x40040000;
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imm32 r5, 0x50050700;
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imm32 r6, 0x60060000;
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imm32 r7, 0x70070700;
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R0.L = R0.H >>> 15;
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R1.L = R1.H >>> 15;
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R2.L = R2.H >>> 15;
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R3.L = R3.H >>> 15;
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R4.L = R4.H >>> 15;
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R5.L = R5.H >>> 15;
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R6.L = R6.H >>> 15;
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R7.L = R7.H >>> 15;
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CHECKREG r0, 0x10010000;
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CHECKREG r1, 0x10010000;
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CHECKREG r2, 0x20020000;
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CHECKREG r3, 0x30030000;
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CHECKREG r4, 0x40040000;
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CHECKREG r5, 0x50050000;
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CHECKREG r6, 0x60060000;
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CHECKREG r7, 0x70070000;
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imm32 r0, 0x18010001;
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imm32 r1, 0x18010001;
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imm32 r2, 0x28020002;
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R3.L = -16;
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imm32 r4, 0x48040004;
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imm32 r5, 0x58050005;
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imm32 r6, 0x68060006;
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imm32 r7, 0x78070007;
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R0.L = R0.H >>> 13;
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R1.L = R1.H >>> 13;
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R2.L = R2.H >>> 13;
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R3.L = R3.H >>> 13;
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R4.L = R4.H >>> 13;
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R5.L = R5.H >>> 13;
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R6.L = R6.H >>> 13;
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R7.L = R7.H >>> 13;
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CHECKREG r0, 0x18010000;
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CHECKREG r1, 0x18010000;
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CHECKREG r2, 0x28020001;
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CHECKREG r3, 0x30030001;
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CHECKREG r4, 0x48040002;
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CHECKREG r5, 0x58050002;
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CHECKREG r6, 0x68060003;
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CHECKREG r7, 0x78070003;
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// d_hi = ashft (d_lo BY d_lo)
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// RLx by RLx
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imm32 r0, 0x09000091;
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imm32 r1, 0x09000091;
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imm32 r2, 0x09000092;
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imm32 r3, 0x09000093;
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imm32 r4, 0x09000090;
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imm32 r5, 0x09000095;
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imm32 r6, 0x09000096;
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imm32 r7, 0x09000097;
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R0.H = R0.L >>> 14;
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R1.H = R1.L >>> 14;
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R2.H = R2.L >>> 14;
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R3.H = R3.L >>> 14;
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R4.H = R4.L >>> 14;
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R5.H = R5.L >>> 14;
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R6.H = R6.L >>> 14;
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R7.H = R7.L >>> 14;
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CHECKREG r0, 0x00000091;
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CHECKREG r1, 0x00000091;
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CHECKREG r2, 0x00000092;
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CHECKREG r3, 0x00000093;
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CHECKREG r4, 0x00000090;
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CHECKREG r5, 0x00000095;
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CHECKREG r6, 0x00000096;
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CHECKREG r7, 0x00000097;
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imm32 r0, 0xa0000001;
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imm32 r1, 0xa0000001;
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imm32 r2, 0xa0000002;
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imm32 r3, 0xa0000003;
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imm32 r4, 0xa0000004;
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R5.L = -1;
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imm32 r6, 0xa0000006;
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imm32 r7, 0xa0000007;
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R0.H = R0.L >>> 15;
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R1.H = R1.L >>> 15;
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R2.H = R2.L >>> 15;
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R3.H = R3.L >>> 15;
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R4.H = R4.L >>> 15;
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R5.H = R5.L >>> 15;
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R6.H = R6.L >>> 15;
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R7.H = R7.L >>> 15;
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x00000002;
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CHECKREG r3, 0x00000003;
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CHECKREG r4, 0x00000004;
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CHECKREG r5, 0xFFFFFFFF;
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CHECKREG r6, 0x00000006;
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CHECKREG r7, 0x00000007;
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imm32 r0, 0xb0001001;
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imm32 r1, 0xb0001001;
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imm32 r1, 0xb0002002;
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imm32 r3, 0xb0003003;
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imm32 r4, 0xb0004004;
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imm32 r5, 0xb0005005;
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R6.L = -15;
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imm32 r7, 0xb0007007;
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R0.H = R0.L >>> 6;
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R1.H = R1.L >>> 6;
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R2.H = R2.L >>> 6;
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R3.H = R3.L >>> 6;
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R4.H = R4.L >>> 6;
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R5.H = R5.L >>> 6;
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R6.H = R6.L >>> 6;
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R7.H = R7.L >>> 6;
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CHECKREG r0, 0x00401001;
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CHECKREG r1, 0x00802002;
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CHECKREG r2, 0x00000002;
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CHECKREG r3, 0x00C03003;
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CHECKREG r4, 0x01004004;
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CHECKREG r5, 0x01405005;
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CHECKREG r6, 0xFFFFFFF1;
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CHECKREG r7, 0x01C07007;
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imm32 r0, 0x0c001c01;
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imm32 r1, 0x0c002c01;
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imm32 r2, 0x0c002c02;
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imm32 r3, 0x0c003c03;
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imm32 r4, 0x0c004c04;
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imm32 r5, 0x0c005c05;
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imm32 r6, 0x0c006c06;
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R7.L = -16;
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R0.H = R0.L >>> 7;
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R1.H = R1.L >>> 7;
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R2.H = R2.L >>> 7;
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R3.H = R3.L >>> 7;
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R4.H = R4.L >>> 7;
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R5.H = R5.L >>> 7;
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R6.H = R6.L >>> 7;
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R7.H = R7.L >>> 7;
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CHECKREG r0, 0x00381C01;
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CHECKREG r1, 0x00582C01;
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CHECKREG r2, 0x00582C02;
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CHECKREG r3, 0x00783C03;
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CHECKREG r4, 0x00984C04;
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CHECKREG r5, 0x00B85C05;
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CHECKREG r6, 0x00D86C06;
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CHECKREG r7, 0xFFFFFFF0;
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// d_lo = ashft (d_hi BY d_lo)
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// RHx by RLx
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imm32 r0, 0x0d01d000;
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imm32 r1, 0x0d01d000;
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imm32 r2, 0x0d02d000;
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imm32 r3, 0x0d03d000;
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R4.L = -1;
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imm32 r5, 0x0d05d000;
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imm32 r6, 0x0d06d000;
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imm32 r7, 0x0d07d000;
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R0.H = R0.H >>> 4;
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R1.H = R1.H >>> 4;
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R2.H = R2.H >>> 4;
|
||
|
|
R3.H = R3.H >>> 4;
|
||
|
|
R4.H = R4.H >>> 4;
|
||
|
|
R5.H = R5.H >>> 4;
|
||
|
|
R6.H = R6.H >>> 4;
|
||
|
|
R7.H = R6.H >>> 4;
|
||
|
|
CHECKREG r0, 0x00D0D000;
|
||
|
|
CHECKREG r1, 0x00D0D000;
|
||
|
|
CHECKREG r2, 0x00D0D000;
|
||
|
|
CHECKREG r3, 0x00D0D000;
|
||
|
|
CHECKREG r4, 0x0009FFFF;
|
||
|
|
CHECKREG r5, 0x00D0D000;
|
||
|
|
CHECKREG r6, 0x00D0D000;
|
||
|
|
CHECKREG r7, 0x000DD000;
|
||
|
|
|
||
|
|
imm32 r0, 0x1e010000;
|
||
|
|
imm32 r1, 0x1e010000;
|
||
|
|
imm32 r2, 0x2e020000;
|
||
|
|
imm32 r3, 0x3e030000;
|
||
|
|
imm32 r4, 0x4e040000;
|
||
|
|
R5.L = -1;
|
||
|
|
imm32 r6, 0x6e060000;
|
||
|
|
imm32 r7, 0x7e070000;
|
||
|
|
R7.H = R0.H >>> 15;
|
||
|
|
R6.H = R1.H >>> 15;
|
||
|
|
R0.H = R2.H >>> 15;
|
||
|
|
R1.H = R3.H >>> 15;
|
||
|
|
R2.H = R4.H >>> 15;
|
||
|
|
R3.H = R5.H >>> 15;
|
||
|
|
R4.H = R6.H >>> 15;
|
||
|
|
R5.H = R7.H >>> 15;
|
||
|
|
CHECKREG r0, 0x00000000;
|
||
|
|
CHECKREG r1, 0x00000000;
|
||
|
|
CHECKREG r2, 0x00000000;
|
||
|
|
CHECKREG r3, 0x00000000;
|
||
|
|
CHECKREG r4, 0x00000000;
|
||
|
|
CHECKREG r5, 0x0000FFFF;
|
||
|
|
CHECKREG r6, 0x00000000;
|
||
|
|
CHECKREG r7, 0x00000000;
|
||
|
|
|
||
|
|
imm32 r0, 0x1f010000;
|
||
|
|
imm32 r1, 0x1f010000;
|
||
|
|
imm32 r2, 0x2f020000;
|
||
|
|
imm32 r3, 0x3f030000;
|
||
|
|
imm32 r4, 0x4f040000;
|
||
|
|
imm32 r5, 0x5f050000;
|
||
|
|
R6.L = -15;
|
||
|
|
imm32 r7, 0x70070000;
|
||
|
|
R6.H = R0.H >>> 6;
|
||
|
|
R7.H = R1.H >>> 6;
|
||
|
|
R5.H = R2.H >>> 6;
|
||
|
|
R0.H = R3.H >>> 6;
|
||
|
|
R1.H = R4.H >>> 6;
|
||
|
|
R2.H = R5.H >>> 6;
|
||
|
|
R3.H = R6.H >>> 6;
|
||
|
|
R4.H = R7.H >>> 6;
|
||
|
|
CHECKREG r0, 0x00FC0000;
|
||
|
|
CHECKREG r1, 0x013C0000;
|
||
|
|
CHECKREG r2, 0x00020000;
|
||
|
|
CHECKREG r3, 0x00010000;
|
||
|
|
CHECKREG r4, 0x00010000;
|
||
|
|
CHECKREG r5, 0x00BC0000;
|
||
|
|
CHECKREG r6, 0x007CFFF1;
|
||
|
|
CHECKREG r7, 0x007C0000;
|
||
|
|
|
||
|
|
imm32 r0, 0x11010a00;
|
||
|
|
imm32 r1, 0x11010b00;
|
||
|
|
imm32 r2, 0x21020d00;
|
||
|
|
imm32 r2, 0x31030c00;
|
||
|
|
imm32 r4, 0x41040d00;
|
||
|
|
imm32 r5, 0x51050e00;
|
||
|
|
imm32 r6, 0x610600f0;
|
||
|
|
R7.L = -16;
|
||
|
|
R5.H = R0.H >>> 7;
|
||
|
|
R6.H = R1.H >>> 7;
|
||
|
|
R7.H = R2.H >>> 7;
|
||
|
|
R2.H = R3.H >>> 7;
|
||
|
|
R3.H = R4.H >>> 7;
|
||
|
|
R4.H = R5.H >>> 7;
|
||
|
|
R0.H = R6.H >>> 7;
|
||
|
|
R1.H = R7.H >>> 7;
|
||
|
|
CHECKREG r0, 0x00000A00;
|
||
|
|
CHECKREG r1, 0x00000B00;
|
||
|
|
CHECKREG r2, 0x00000C00;
|
||
|
|
CHECKREG r3, 0x00820000;
|
||
|
|
CHECKREG r4, 0x00000D00;
|
||
|
|
CHECKREG r5, 0x00220E00;
|
||
|
|
CHECKREG r6, 0x002200F0;
|
||
|
|
CHECKREG r7, 0x0062FFF0;
|
||
|
|
pass
|