mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-06 12:09:26 +08:00
211 lines
4.7 KiB
ArmAsm
211 lines
4.7 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp
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// Spec Reference: dsp32shift align16
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00000001;
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imm32 r1, 0x01000801;
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imm32 r2, 0x08200802;
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imm32 r3, 0x08030803;
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imm32 r4, 0x08004804;
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imm32 r5, 0x08000505;
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imm32 r6, 0x08000866;
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imm32 r7, 0x08000807;
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R1 = ALIGN16 ( R1 , R0 );
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R2 = ALIGN16 ( R2 , R0 );
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R3 = ALIGN16 ( R3 , R0 );
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R4 = ALIGN16 ( R4 , R0 );
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R5 = ALIGN16 ( R5 , R0 );
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R6 = ALIGN16 ( R6 , R0 );
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R7 = ALIGN16 ( R7 , R0 );
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R0 = ALIGN16 ( R0 , R0 );
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CHECKREG r0, 0x00010000;
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CHECKREG r1, 0x08010000;
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CHECKREG r2, 0x08020000;
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CHECKREG r3, 0x08030000;
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CHECKREG r4, 0x48040000;
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CHECKREG r5, 0x05050000;
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CHECKREG r6, 0x08660000;
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CHECKREG r7, 0x08070000;
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imm32 r0, 0x0900d001;
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imm32 r1, 0x09000002;
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imm32 r2, 0x09400002;
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imm32 r3, 0x09100003;
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imm32 r4, 0x09020004;
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imm32 r5, 0x09003005;
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imm32 r6, 0x09000406;
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imm32 r7, 0x09000057;
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R0 = ALIGN16 ( R0 , R1 );
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R2 = ALIGN16 ( R2 , R1 );
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R3 = ALIGN16 ( R3 , R1 );
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R4 = ALIGN16 ( R4 , R1 );
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R5 = ALIGN16 ( R5 , R1 );
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R6 = ALIGN16 ( R6 , R1 );
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R7 = ALIGN16 ( R7 , R1 );
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R1 = ALIGN16 ( R1 , R1 );
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CHECKREG r0, 0xD0010900;
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CHECKREG r1, 0x00020900;
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CHECKREG r2, 0x00020900;
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CHECKREG r3, 0x00030900;
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CHECKREG r4, 0x00040900;
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CHECKREG r5, 0x30050900;
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CHECKREG r6, 0x04060900;
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CHECKREG r7, 0x00570900;
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imm32 r0, 0x0a00e001;
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imm32 r1, 0x0a00e001;
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imm32 r2, 0x0a00000f;
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imm32 r3, 0x0a400010;
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imm32 r4, 0x0a05e004;
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imm32 r5, 0x0a006005;
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imm32 r6, 0x0a00e706;
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imm32 r7, 0x0a00e087;
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R0 = ALIGN16 ( R0 , R2 );
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R1 = ALIGN16 ( R1 , R2 );
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R3 = ALIGN16 ( R3 , R2 );
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R4 = ALIGN16 ( R4 , R2 );
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R5 = ALIGN16 ( R5 , R2 );
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R6 = ALIGN16 ( R6 , R2 );
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R7 = ALIGN16 ( R7 , R2 );
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R2 = ALIGN16 ( R2 , R2 );
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CHECKREG r0, 0xE0010A00;
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CHECKREG r1, 0xE0010A00;
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CHECKREG r2, 0x000F0A00;
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CHECKREG r3, 0x00100A00;
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CHECKREG r4, 0xE0040A00;
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CHECKREG r5, 0x60050A00;
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CHECKREG r6, 0xE7060A00;
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CHECKREG r7, 0xE0870A00;
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imm32 r0, 0x2b00f001;
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imm32 r1, 0x0300f001;
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imm32 r2, 0x0b40f002;
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imm32 r3, 0x0b050010;
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imm32 r4, 0x0b006004;
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imm32 r5, 0x0b00f705;
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imm32 r6, 0x0b00f086;
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imm32 r7, 0x0b00f009;
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R0 = ALIGN16 ( R0 , R3 );
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R1 = ALIGN16 ( R1 , R3 );
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R2 = ALIGN16 ( R2 , R3 );
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R4 = ALIGN16 ( R4 , R3 );
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R5 = ALIGN16 ( R5 , R3 );
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R6 = ALIGN16 ( R6 , R3 );
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R7 = ALIGN16 ( R7 , R3 );
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R3 = ALIGN16 ( R3 , R3 );
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CHECKREG r0, 0xF0010B05;
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CHECKREG r1, 0xF0010B05;
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CHECKREG r2, 0xF0020B05;
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CHECKREG r3, 0x00100B05;
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CHECKREG r4, 0x60040B05;
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CHECKREG r5, 0xF7050B05;
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CHECKREG r6, 0xF0860B05;
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CHECKREG r7, 0xF0090B05;
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imm32 r0, 0x4c0000c0;
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imm32 r1, 0x050100c0;
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imm32 r2, 0x0c6200c0;
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imm32 r3, 0x0c0700c0;
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imm32 r4, 0x0c04800c;
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imm32 r5, 0x0c0509c0;
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imm32 r6, 0x0c060000;
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imm32 r7, 0x0c0700ca;
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R0 = ALIGN16 ( R0 , R4 );
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R1 = ALIGN16 ( R1 , R4 );
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R2 = ALIGN16 ( R2 , R4 );
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R3 = ALIGN16 ( R3 , R4 );
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R5 = ALIGN16 ( R5 , R4 );
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R6 = ALIGN16 ( R6 , R4 );
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R7 = ALIGN16 ( R7 , R4 );
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R4 = ALIGN16 ( R4 , R4 );
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CHECKREG r0, 0x00C00C04;
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CHECKREG r1, 0x00C00C04;
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CHECKREG r2, 0x00C00C04;
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CHECKREG r3, 0x00C00C04;
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CHECKREG r4, 0x800C0C04;
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CHECKREG r5, 0x09C00C04;
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CHECKREG r6, 0x00000C04;
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CHECKREG r7, 0x00CA0C04;
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imm32 r0, 0xa00100d0;
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imm32 r1, 0xa00100d1;
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imm32 r2, 0xa00200d0;
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imm32 r3, 0xa00300d0;
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imm32 r4, 0xa00400d0;
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imm32 r5, 0xa0050007;
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imm32 r6, 0xa00600d0;
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imm32 r7, 0xa00700d0;
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R0 = ALIGN16 ( R0 , R5 );
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R1 = ALIGN16 ( R1 , R5 );
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R2 = ALIGN16 ( R2 , R5 );
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R3 = ALIGN16 ( R3 , R5 );
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R4 = ALIGN16 ( R4 , R5 );
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R6 = ALIGN16 ( R6 , R5 );
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R7 = ALIGN16 ( R7 , R5 );
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R5 = ALIGN16 ( R5 , R5 );
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CHECKREG r0, 0x00D0A005;
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CHECKREG r1, 0x00D1A005;
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CHECKREG r2, 0x00D0A005;
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CHECKREG r3, 0x00D0A005;
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CHECKREG r4, 0x00D0A005;
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CHECKREG r5, 0x0007A005;
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CHECKREG r6, 0x00D0A005;
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CHECKREG r7, 0x00D0A005;
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imm32 r0, 0xb2010000;
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imm32 r1, 0xb0310000;
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imm32 r2, 0xb042000f;
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imm32 r3, 0xbf030000;
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imm32 r4, 0xba040000;
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imm32 r5, 0xbb050000;
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imm32 r6, 0xbc060009;
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imm32 r7, 0xb0e70000;
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R0 = ALIGN16 ( R0 , R6 );
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R1 = ALIGN16 ( R1 , R6 );
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R2 = ALIGN16 ( R2 , R6 );
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R3 = ALIGN16 ( R3 , R6 );
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R4 = ALIGN16 ( R4 , R6 );
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R5 = ALIGN16 ( R5 , R6 );
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R6 = ALIGN16 ( R6 , R6 );
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R7 = ALIGN16 ( R7 , R6 );
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CHECKREG r0, 0x0000BC06;
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CHECKREG r1, 0x0000BC06;
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CHECKREG r2, 0x000FBC06;
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CHECKREG r3, 0x0000BC06;
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CHECKREG r4, 0x0000BC06;
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CHECKREG r5, 0x0000BC06;
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CHECKREG r6, 0x0009BC06;
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CHECKREG r7, 0x00000009;
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imm32 r0, 0xd23100e0;
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imm32 r1, 0xd04500e0;
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imm32 r2, 0xde32f0e0;
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imm32 r3, 0xd90300e0;
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imm32 r4, 0xd07400e0;
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imm32 r5, 0xdef500e0;
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imm32 r6, 0xd06600e0;
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imm32 r7, 0xd0080023;
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R1 = ALIGN16 ( R0 , R7 );
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R2 = ALIGN16 ( R1 , R7 );
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R3 = ALIGN16 ( R2 , R7 );
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R4 = ALIGN16 ( R3 , R7 );
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R5 = ALIGN16 ( R4 , R7 );
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R6 = ALIGN16 ( R5 , R7 );
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R7 = ALIGN16 ( R6 , R7 );
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R0 = ALIGN16 ( R7 , R7 );
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CHECKREG r0, 0xD008D008;
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CHECKREG r1, 0x00E0D008;
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CHECKREG r2, 0xD008D008;
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CHECKREG r3, 0xD008D008;
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CHECKREG r4, 0xD008D008;
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CHECKREG r5, 0xD008D008;
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CHECKREG r6, 0xD008D008;
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CHECKREG r7, 0xD008D008;
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pass
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