mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-06 12:09:26 +08:00
179 lines
3.9 KiB
ArmAsm
179 lines
3.9 KiB
ArmAsm
|
//Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp
|
||
|
|
// Spec Reference: dsp32mult pair MUNOP is
|
||
|
|
# mach: bfin
|
||
|
|
|
||
|
|
.include "testutils.inc"
|
||
|
|
start
|
||
|
|
|
||
|
|
imm32 r0, 0x34235625;
|
||
|
|
imm32 r1, 0x9f7a5127;
|
||
|
|
imm32 r2, 0xa3286725;
|
||
|
|
imm32 r3, 0x00069027;
|
||
|
|
imm32 r4, 0xb0abc029;
|
||
|
|
imm32 r5, 0x10acef2b;
|
||
|
|
imm32 r6, 0xc00c00de;
|
||
|
|
imm32 r7, 0xd246712f;
|
||
|
|
R0 = R0.L * R0.L (ISS2);
|
||
|
|
R2 = R0.L * R1.H (ISS2);
|
||
|
|
R4 = R1.H * R1.H (ISS2);
|
||
|
|
R6 = R0.L * R0.L (ISS2);
|
||
|
|
CHECKREG r0, 0x39F9C2B2;
|
||
|
|
CHECKREG r1, 0x9F7A5127;
|
||
|
|
CHECKREG r2, 0x2E3AADA8;
|
||
|
|
CHECKREG r3, 0x00069027;
|
||
|
|
CHECKREG r4, 0x48C98C48;
|
||
|
|
CHECKREG r5, 0x10ACEF2B;
|
||
|
|
CHECKREG r6, 0x1D5C8788;
|
||
|
|
CHECKREG r7, 0xD246712F;
|
||
|
|
|
||
|
|
imm32 r0, 0x5b23a635;
|
||
|
|
imm32 r1, 0x6fba5137;
|
||
|
|
imm32 r2, 0x1324b735;
|
||
|
|
imm32 r3, 0x90060037;
|
||
|
|
imm32 r4, 0x80abcd39;
|
||
|
|
imm32 r5, 0xb0acef3b;
|
||
|
|
imm32 r6, 0xa00c003d;
|
||
|
|
imm32 r7, 0x12467003;
|
||
|
|
R0 = R2.L * R2.L (ISS2);
|
||
|
|
R2 = R2.L * R3.H (ISS2);
|
||
|
|
R4 = R3.H * R2.H (ISS2);
|
||
|
|
R6 = R2.L * R3.L (ISS2);
|
||
|
|
CHECKREG r0, 0x2965A1F2;
|
||
|
|
CHECKREG r1, 0x6FBA5137;
|
||
|
|
CHECKREG r2, 0x3FAE367C;
|
||
|
|
CHECKREG r3, 0x90060037;
|
||
|
|
CHECKREG r4, 0xC84ABC28;
|
||
|
|
CHECKREG r5, 0xB0ACEF3B;
|
||
|
|
CHECKREG r6, 0x00176948;
|
||
|
|
CHECKREG r7, 0x12467003;
|
||
|
|
|
||
|
|
imm32 r0, 0x1b235655;
|
||
|
|
imm32 r1, 0xc4ba5157;
|
||
|
|
imm32 r2, 0x43246755;
|
||
|
|
imm32 r3, 0x05060055;
|
||
|
|
imm32 r4, 0x906bc509;
|
||
|
|
imm32 r5, 0x10a7ef5b;
|
||
|
|
imm32 r6, 0xb00c805d;
|
||
|
|
imm32 r7, 0x1246795f;
|
||
|
|
R0 = R4.L * R4.L (ISS2);
|
||
|
|
R2 = R4.L * R5.H (ISS2);
|
||
|
|
R4 = R5.H * R5.H (ISS2);
|
||
|
|
R6 = R4.L * R5.L (ISS2);
|
||
|
|
CHECKREG r0, 0x1B29B4A2;
|
||
|
|
CHECKREG r1, 0xC4BA5157;
|
||
|
|
CHECKREG r2, 0xF85431BE;
|
||
|
|
CHECKREG r3, 0x05060055;
|
||
|
|
CHECKREG r4, 0x022A99E2;
|
||
|
|
CHECKREG r5, 0x10A7EF5B;
|
||
|
|
CHECKREG r6, 0x0D4762AC;
|
||
|
|
CHECKREG r7, 0x1246795F;
|
||
|
|
|
||
|
|
imm32 r0, 0xbb235666;
|
||
|
|
imm32 r1, 0xefba5166;
|
||
|
|
imm32 r2, 0x13248766;
|
||
|
|
imm32 r3, 0xf0060066;
|
||
|
|
imm32 r4, 0x90ab9d69;
|
||
|
|
imm32 r5, 0x10acef6b;
|
||
|
|
imm32 r6, 0x800cb06d;
|
||
|
|
imm32 r7, 0x1246706f;
|
||
|
|
R0 = R6.L * R6.L (ISS2);
|
||
|
|
R2 = R6.L * R7.H (ISS2);
|
||
|
|
R4 = R7.H * R7.H (ISS2);
|
||
|
|
R6 = R6.L * R7.L (ISS2);
|
||
|
|
CHECKREG r0, 0x31781CD2;
|
||
|
|
CHECKREG r1, 0xEFBA5166;
|
||
|
|
CHECKREG r2, 0xF4A3CF9C;
|
||
|
|
CHECKREG r3, 0xF0060066;
|
||
|
|
CHECKREG r4, 0x029BD648;
|
||
|
|
CHECKREG r5, 0x10ACEF6B;
|
||
|
|
CHECKREG r6, 0xBA1A5E86;
|
||
|
|
CHECKREG r7, 0x1246706F;
|
||
|
|
|
||
|
|
// mix order
|
||
|
|
imm32 r0, 0xab23a675;
|
||
|
|
imm32 r1, 0xcfba5127;
|
||
|
|
imm32 r2, 0x13246705;
|
||
|
|
imm32 r3, 0x00060007;
|
||
|
|
imm32 r4, 0x90abcd09;
|
||
|
|
imm32 r5, 0x10acdfdb;
|
||
|
|
imm32 r6, 0x000c000d;
|
||
|
|
imm32 r7, 0x1246f00f;
|
||
|
|
R0 = R0.L * R7.L (ISS2);
|
||
|
|
R2 = R1.L * R6.H (ISS2);
|
||
|
|
R4 = R3.H * R4.H (ISS2);
|
||
|
|
R6 = R4.L * R3.L (ISS2);
|
||
|
|
CHECKREG r0, 0x0B26E1B6;
|
||
|
|
CHECKREG r1, 0xCFBA5127;
|
||
|
|
CHECKREG r2, 0x00079BA8;
|
||
|
|
CHECKREG r3, 0x00060007;
|
||
|
|
CHECKREG r4, 0xFFFAC804;
|
||
|
|
CHECKREG r5, 0x10ACDFDB;
|
||
|
|
CHECKREG r6, 0xFFFCF038;
|
||
|
|
CHECKREG r7, 0x1246F00F;
|
||
|
|
|
||
|
|
imm32 r0, 0xab235a75;
|
||
|
|
imm32 r1, 0xcfba5127;
|
||
|
|
imm32 r2, 0x13246905;
|
||
|
|
imm32 r3, 0x00060007;
|
||
|
|
imm32 r4, 0x90abcd09;
|
||
|
|
imm32 r5, 0x10ace9db;
|
||
|
|
imm32 r6, 0x000c0d0d;
|
||
|
|
imm32 r7, 0x1246700f;
|
||
|
|
R1 = R7.H * R0.H (ISS2);
|
||
|
|
R3 = R6.H * R1.H (ISS2);
|
||
|
|
R5 = R5.H * R2.L (ISS2);
|
||
|
|
R7 = R4.L * R3.H (ISS2);
|
||
|
|
CHECKREG r0, 0xAB235A75;
|
||
|
|
CHECKREG r1, 0xF3E28324;
|
||
|
|
CHECKREG r2, 0x13246905;
|
||
|
|
CHECKREG r3, 0xFFFEDD30;
|
||
|
|
CHECKREG r4, 0x90ABCD09;
|
||
|
|
CHECKREG r5, 0x0DADBEB8;
|
||
|
|
CHECKREG r6, 0x000C0D0D;
|
||
|
|
CHECKREG r7, 0x0000CBDC;
|
||
|
|
|
||
|
|
imm32 r0, 0x9b235675;
|
||
|
|
imm32 r1, 0xc9ba5127;
|
||
|
|
imm32 r2, 0x13946705;
|
||
|
|
imm32 r3, 0x00090007;
|
||
|
|
imm32 r4, 0x90ab9d09;
|
||
|
|
imm32 r5, 0x10ace9db;
|
||
|
|
imm32 r6, 0x000c009d;
|
||
|
|
imm32 r7, 0x12467009;
|
||
|
|
R1 = R6.H * R4.L (ISS2);
|
||
|
|
R3 = R5.L * R3.H (ISS2);
|
||
|
|
R5 = R3.H * R1.L (ISS2);
|
||
|
|
R7 = R1.H * R2.H (ISS2);
|
||
|
|
CHECKREG r0, 0x9B235675;
|
||
|
|
CHECKREG r1, 0xFFF6B8D8;
|
||
|
|
CHECKREG r2, 0x13946705;
|
||
|
|
CHECKREG r3, 0xFFFE7166;
|
||
|
|
CHECKREG r4, 0x90AB9D09;
|
||
|
|
CHECKREG r5, 0x00011CA0;
|
||
|
|
CHECKREG r6, 0x000C009D;
|
||
|
|
CHECKREG r7, 0xFFFE7870;
|
||
|
|
|
||
|
|
imm32 r0, 0xeb235675;
|
||
|
|
imm32 r1, 0xceba5127;
|
||
|
|
imm32 r2, 0x13e46705;
|
||
|
|
imm32 r3, 0x000e0007;
|
||
|
|
imm32 r4, 0x90abed09;
|
||
|
|
imm32 r5, 0x10aceedb;
|
||
|
|
imm32 r6, 0x000c00ed;
|
||
|
|
imm32 r7, 0x1246700e;
|
||
|
|
R1 = R4.L * R0.H (ISS2);
|
||
|
|
R3 = R6.H * R1.H (ISS2);
|
||
|
|
R5 = R1.L * R2.L (ISS2);
|
||
|
|
R7 = R4.H * R2.L (ISS2);
|
||
|
|
CHECKREG r0, 0xEB235675;
|
||
|
|
CHECKREG r1, 0x03175676;
|
||
|
|
CHECKREG r2, 0x13E46705;
|
||
|
|
CHECKREG r3, 0x00004A28;
|
||
|
|
CHECKREG r4, 0x90ABED09;
|
||
|
|
CHECKREG r5, 0x4596549C;
|
||
|
|
CHECKREG r6, 0x000C00ED;
|
||
|
|
CHECKREG r7, 0xA66540AE;
|
||
|
|
|
||
|
|
|
||
|
|
pass
|