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128 lines
2.9 KiB
ArmAsm
128 lines
2.9 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp
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// Spec Reference: dsp32mac dr_a0 m
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0xab235675;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x13246705;
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imm32 r3, 0x00060007;
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imm32 r4, 0x90abcd09;
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imm32 r5, 0x10acefdb;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x1246700f;
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A1 = A0 = 0;
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// The result accumulated in A1 , and stored to a reg half
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
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R1 = A0.w;
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A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L );
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R3 = A0.w;
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A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H );
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R5 = A0.w;
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A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H );
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R7 = A0.w;
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CHECKREG r0, 0x1354FF22;
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CHECKREG r1, 0xFF221DD6;
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CHECKREG r2, 0xA124FF27;
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CHECKREG r3, 0xFF274DDE;
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CHECKREG r4, 0xEFBCFCD7;
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CHECKREG r5, 0xFCD701B6;
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CHECKREG r6, 0x000C000B;
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CHECKREG r7, 0x000A846C;
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// The result accumulated in A1, and stored to a reg half (MNOP)
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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R0.L = ( A0 += R6.L * R7.L );
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R1 = A0.w;
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R2.L = ( A0 -= R2.L * R3.H );
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R3 = A0.w;
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R4.L = ( A0 += R4.H * R5.L );
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R5 = A0.w;
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R6.L = ( A0 = R0.H * R1.H );
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R7 = A0.w;
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CHECKREG r0, 0x1354000B;
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CHECKREG r1, 0x000A85F2;
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CHECKREG r2, 0xA1240006;
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CHECKREG r3, 0x00067846;
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CHECKREG r4, 0xEFBC0005;
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CHECKREG r5, 0x0005126E;
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CHECKREG r6, 0x000C0002;
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CHECKREG r7, 0x00018290;
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// The result accumulated in A1 , and stored to a reg half (MNOP)
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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R0.L = ( A0 = R1.L * R0.L );
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R1 = A0.w;
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R2.L = ( A0 += R2.H * R3.L );
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R3 = A0.w;
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R4.L = ( A0 += R4.H * R5.H );
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R5 = A0.w;
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R6.L = ( A0 += R6.L * R7.H );
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R7 = A0.w;
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CHECKREG r0, 0x1354FF22;
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CHECKREG r1, 0xFF221DD6;
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CHECKREG r2, 0xA124FF1D;
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CHECKREG r3, 0xFF1CEDCE;
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CHECKREG r4, 0xEFBCFCCD;
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CHECKREG r5, 0xFCCCA1A6;
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CHECKREG r6, 0x000CFCD7;
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CHECKREG r7, 0xFCD72612;
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// The result accumulated in A1 , and stored to a reg half
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imm32 r0, 0x13545abd;
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imm32 r1, 0xadbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0x00060007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0x1235000b;
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imm32 r6, 0x000c000d;
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imm32 r7, 0x678e000f;
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A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L );
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R7 = A0.w;
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A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L );
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R3 = A0.w;
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A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H );
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R5 = A0.w;
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A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H );
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R1 = A0.w;
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CHECKREG r0, 0x1354000B;
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CHECKREG r1, 0x000A83F2;
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CHECKREG r2, 0xA124FDB0;
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CHECKREG r3, 0xFDAFD834;
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CHECKREG r4, 0xEFBCFDB0;
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CHECKREG r5, 0xFDAFB3D8;
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CHECKREG r6, 0x000CFDB5;
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CHECKREG r7, 0xFDB5083C;
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pass
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