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https://sourceware.org/git/binutils-gdb.git
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125 lines
2.2 KiB
ArmAsm
125 lines
2.2 KiB
ArmAsm
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//Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp
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// Spec Reference: ccmv cc dreg = dreg
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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imm32 r0, 0xa08d2301;
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imm32 r1, 0xd0021053;
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imm32 r2, 0x2f041405;
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imm32 r3, 0x60b61507;
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imm32 r4, 0x50487609;
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imm32 r5, 0x3005900b;
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imm32 r6, 0x2a0c660d;
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imm32 r7, 0xd90e108f;
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IF CC R0 = R0;
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IF CC R1 = R3;
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IF CC R2 = R5;
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IF CC R3 = R2;
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CC = ! CC;
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IF CC R4 = R6;
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IF CC R5 = R1;
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IF CC R6 = R7;
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CC = ! CC;
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IF CC R7 = R4;
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CHECKREG r0, 0xA08D2301;
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CHECKREG r1, 0xD0021053;
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CHECKREG r2, 0x2F041405;
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CHECKREG r3, 0x60B61507;
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CHECKREG r4, 0x2A0C660D;
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CHECKREG r5, 0xD0021053;
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CHECKREG r6, 0xD90E108F;
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CHECKREG r7, 0xD90E108F;
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imm32 r0, 0x308d2301;
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imm32 r1, 0xd4023053;
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imm32 r2, 0x2f041405;
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imm32 r3, 0x60f61507;
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imm32 r4, 0xd0487f09;
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imm32 r5, 0x300b900b;
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imm32 r6, 0x2a0cd60d;
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imm32 r7, 0xd90e189f;
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IF CC R4 = R3;
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IF CC R5 = R7;
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IF CC R6 = R1;
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IF CC R7 = R2;
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CC = ! CC;
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IF CC R0 = R6;
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IF CC R1 = R5;
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IF CC R2 = R4;
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CC = ! CC;
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IF CC R3 = R0;
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CHECKREG r0, 0x2A0CD60D;
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CHECKREG r1, 0x300B900B;
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CHECKREG r2, 0xD0487F09;
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CHECKREG r3, 0x60F61507;
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CHECKREG r4, 0xD0487F09;
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CHECKREG r5, 0x300B900B;
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CHECKREG r6, 0x2A0CD60D;
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CHECKREG r7, 0xD90E189F;
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imm32 r0, 0x708d2301;
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imm32 r1, 0xd8021053;
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imm32 r2, 0x2f041405;
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imm32 r3, 0x65b61507;
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imm32 r4, 0x59487609;
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imm32 r5, 0x3005900b;
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imm32 r6, 0x2abc660d;
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imm32 r7, 0xd90e108f;
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IF CC R0 = R2;
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IF CC R1 = R3;
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CC = ! CC;
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IF CC R2 = R5;
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IF CC R3 = R7;
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CC = ! CC;
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IF CC R4 = R1;
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IF CC R5 = R4;
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IF CC R6 = R7;
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IF CC R7 = R6;
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CHECKREG r0, 0x708D2301;
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CHECKREG r1, 0xD8021053;
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CHECKREG r2, 0x3005900B;
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CHECKREG r3, 0xD90E108F;
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CHECKREG r4, 0x59487609;
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CHECKREG r5, 0x3005900B;
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CHECKREG r6, 0x2ABC660D;
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CHECKREG r7, 0xD90E108F;
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imm32 r0, 0xc08d2301;
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imm32 r1, 0xdb021053;
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imm32 r2, 0x2f041405;
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imm32 r3, 0x64b61507;
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imm32 r4, 0x50487609;
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imm32 r5, 0x30f5900b;
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imm32 r6, 0x2a4c660d;
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imm32 r7, 0x895e108f;
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IF CC R4 = R3;
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IF CC R5 = R7;
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CC = ! CC;
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IF CC R6 = R2;
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IF CC R7 = R6;
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CC = ! CC;
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IF CC R0 = R1;
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IF CC R1 = R2;
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IF CC R2 = R0;
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IF CC R3 = R4;
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CHECKREG r0, 0xC08D2301;
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CHECKREG r1, 0xDB021053;
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CHECKREG r2, 0x2F041405;
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CHECKREG r3, 0x64B61507;
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CHECKREG r4, 0x50487609;
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CHECKREG r5, 0x30F5900B;
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CHECKREG r6, 0x2F041405;
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CHECKREG r7, 0x2F041405;
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pass
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